1 | /* |
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2 | * Generic UART Serial driver for SH-4 processors |
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3 | * |
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4 | * This driver uses variable SH4_CPU_HZ_Frequency, |
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5 | * which should be defined in bsp to HZ macro. |
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6 | * |
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7 | * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russian Fed. |
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8 | * Author: Alexandra Kossovsky <sasha@oktet.ru> |
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9 | * |
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10 | * COPYRIGHT (c) 1989-2000. |
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11 | * On-Line Applications Research Corporation (OAR). |
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12 | * Copyright assigned to U.S. Government, 1994. |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in the file LICENSE in this distribution or at |
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16 | * |
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17 | * http://www.OARcorp.com/rtems/license.html. |
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18 | * |
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19 | * $Id$ |
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20 | * |
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21 | */ |
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22 | |
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23 | #include <rtems.h> |
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24 | #include <termios.h> |
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25 | #include <rtems/libio.h> |
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26 | #include "sh/sh4uart.h" |
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27 | |
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28 | #ifndef SH4_UART_INTERRUPT_LEVEL |
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29 | #define SH4_UART_INTERRUPT_LEVEL 4 |
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30 | #endif |
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31 | |
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32 | /* Forward function declarations */ |
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33 | static rtems_isr |
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34 | sh4uart1_interrupt_transmit(rtems_vector_number vec); |
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35 | static rtems_isr |
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36 | sh4uart1_interrupt_receive(rtems_vector_number vec); |
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37 | static rtems_isr |
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38 | sh4uart2_interrupt_transmit(rtems_vector_number vec); |
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39 | static rtems_isr |
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40 | sh4uart2_interrupt_receive(rtems_vector_number vec); |
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41 | |
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42 | /* |
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43 | * sh4uart_init -- |
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44 | * This function verifies the input parameters and perform initialization |
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45 | * of the SH-4 on-chip UART descriptor structure. |
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46 | * |
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47 | * PARAMETERS: |
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48 | * uart - pointer to the UART channel descriptor structure |
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49 | * tty - pointer to termios structure |
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50 | * chn - channel number (SH4_SCI/SH4_SCIF -- 1/2) |
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51 | * int_driven - interrupt-driven (1) or polled (0) I/O mode |
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52 | * |
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53 | * RETURNS: |
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54 | * RTEMS_SUCCESSFUL if all parameters are valid, or error code |
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55 | */ |
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56 | rtems_status_code |
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57 | sh4uart_init(sh4uart *uart, void *tty, int chn, int int_driven) |
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58 | { |
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59 | if (uart == NULL) |
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60 | return RTEMS_INVALID_ADDRESS; |
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61 | |
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62 | if ((chn != SH4_SCI) && (chn != SH4_SCIF)) |
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63 | return RTEMS_INVALID_NUMBER; |
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64 | |
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65 | uart->chn = chn; |
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66 | uart->tty = tty; |
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67 | uart->int_driven = int_driven; |
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68 | |
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69 | #if 0 |
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70 | sh4uart_poll_write(uart, "init", 4); |
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71 | #endif |
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72 | return RTEMS_SUCCESSFUL; |
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73 | } |
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74 | |
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75 | /* |
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76 | * sh4uart_get_Pph -- |
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77 | * Get current peripheral module clock. |
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78 | * |
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79 | * PARAMETERS: none; |
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80 | * Cpu clock is get from SH4_CPU_HZ_Frequency. |
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81 | * This variable should be defined in bsp. |
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82 | * |
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83 | * RETURNS: |
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84 | * peripheral module clock in Hz. |
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85 | */ |
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86 | rtems_unsigned32 |
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87 | sh4uart_get_Pph(void) |
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88 | { |
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89 | rtems_unsigned16 frqcr = *(volatile rtems_unsigned16 *)SH7750_FRQCR; |
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90 | rtems_unsigned32 Pph = SH4_CPU_HZ_Frequency; |
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91 | |
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92 | switch (frqcr & SH7750_FRQCR_IFC) |
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93 | { |
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94 | case SH7750_FRQCR_IFCDIV1: |
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95 | break; |
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96 | |
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97 | case SH7750_FRQCR_IFCDIV2: |
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98 | Pph *= 2; |
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99 | break; |
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100 | |
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101 | case SH7750_FRQCR_IFCDIV3: |
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102 | Pph *= 3; |
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103 | break; |
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104 | |
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105 | case SH7750_FRQCR_IFCDIV4: |
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106 | Pph *= 4; |
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107 | break; |
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108 | |
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109 | case SH7750_FRQCR_IFCDIV6: |
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110 | Pph *= 6; |
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111 | break; |
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112 | |
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113 | case SH7750_FRQCR_IFCDIV8: |
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114 | Pph *= 8; |
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115 | break; |
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116 | |
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117 | default: /* unreachable */ |
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118 | break; |
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119 | } |
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120 | |
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121 | switch (frqcr & SH7750_FRQCR_PFC) |
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122 | { |
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123 | case SH7750_FRQCR_PFCDIV2: |
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124 | Pph /= 2; |
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125 | break; |
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126 | |
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127 | case SH7750_FRQCR_PFCDIV3: |
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128 | Pph /= 3; |
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129 | break; |
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130 | |
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131 | case SH7750_FRQCR_PFCDIV4: |
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132 | Pph /= 4; |
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133 | break; |
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134 | |
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135 | case SH7750_FRQCR_PFCDIV6: |
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136 | Pph /= 6; |
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137 | break; |
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138 | |
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139 | case SH7750_FRQCR_PFCDIV8: |
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140 | Pph /= 8; |
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141 | break; |
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142 | |
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143 | default: /* unreachable */ |
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144 | break; |
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145 | } |
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146 | |
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147 | return Pph; |
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148 | } |
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149 | |
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150 | /* |
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151 | * sh4uart_set_baudrate -- |
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152 | * Program the UART timer to specified baudrate |
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153 | * |
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154 | * PARAMETERS: |
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155 | * uart - pointer to UART descriptor structure |
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156 | * baud - termios baud rate (B50, B9600, etc...) |
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157 | * |
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158 | * ALGORITHM: |
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159 | * see SH7750 Hardware Manual. |
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160 | * |
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161 | * RETURNS: |
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162 | * none |
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163 | */ |
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164 | static void |
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165 | sh4uart_set_baudrate(sh4uart *uart, speed_t baud) |
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166 | { |
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167 | rtems_unsigned32 rate; |
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168 | rtems_signed16 div; |
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169 | int n; |
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170 | rtems_unsigned32 Pph = sh4uart_get_Pph(); |
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171 | |
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172 | switch (baud) |
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173 | { |
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174 | case B50: rate = 50; break; |
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175 | case B75: rate = 75; break; |
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176 | case B110: rate = 110; break; |
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177 | case B134: rate = 134; break; |
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178 | case B150: rate = 150; break; |
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179 | case B200: rate = 200; break; |
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180 | case B300: rate = 300; break; |
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181 | case B600: rate = 600; break; |
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182 | case B1200: rate = 1200; break; |
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183 | case B2400: rate = 2400; break; |
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184 | case B4800: rate = 4800; break; |
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185 | case B9600: rate = 9600; break; |
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186 | case B19200: rate = 19200; break; |
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187 | case B38400: rate = 38400; break; |
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188 | case B57600: rate = 57600; break; |
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189 | #ifdef B115200 |
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190 | case B115200: rate = 115200; break; |
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191 | #endif |
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192 | #ifdef B230400 |
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193 | case B230400: rate = 230400; break; |
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194 | #endif |
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195 | default: rate = 9600; break; |
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196 | } |
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197 | |
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198 | for (n = 0; n < 4; n++) |
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199 | { |
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200 | div = Pph / (32 * (1 << (2 * n)) * rate) - 1; |
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201 | if (div < 0x100) |
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202 | break; |
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203 | } |
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204 | |
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205 | /* Set default baudrate if specified baudrate is impossible */ |
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206 | if (n >= 4) |
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207 | sh4uart_set_baudrate(uart, B9600); |
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208 | |
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209 | SCSMR(uart->chn) &= ~SH7750_SCSMR_CKS; |
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210 | SCSMR(uart->chn) |= n << SH7750_SCSMR_CKS_S; |
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211 | SCBRR(uart->chn) = div; |
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212 | /* Whait at least 1 bit interwal */ |
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213 | rtems_task_wake_after(RTEMS_MILLISECONDS_TO_TICKS(1000 / rate)); |
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214 | } |
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215 | |
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216 | /* |
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217 | * sh4uart_reset -- |
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218 | * This function perform the hardware initialization of SH-4 |
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219 | * on-chip UART controller using parameters |
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220 | * filled by the sh4uart_init function. |
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221 | * |
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222 | * PARAMETERS: |
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223 | * uart - pointer to UART channel descriptor structure |
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224 | * |
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225 | * RETURNS: |
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226 | * RTEMS_SUCCESSFUL if channel is initialized successfully, error |
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227 | * code in other case |
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228 | */ |
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229 | rtems_status_code |
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230 | sh4uart_reset(sh4uart *uart) |
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231 | { |
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232 | register int chn; |
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233 | register int int_driven; |
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234 | rtems_status_code rc; |
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235 | |
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236 | if (uart == NULL) |
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237 | return RTEMS_INVALID_ADDRESS; |
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238 | |
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239 | chn = uart->chn; |
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240 | int_driven = uart->int_driven; |
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241 | |
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242 | SCSCR(chn) = 0x0; /* Is set properly at the end of this function */ |
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243 | SCSMR(chn) = 0x0; /* 8-bit, non-parity, 1 stop bit, pf/1 clock */ |
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244 | |
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245 | if (chn == SH4_SCIF) |
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246 | SCFCR2 = SH7750_SCFCR2_TFRST | SH7750_SCFCR2_RFRST | |
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247 | SH7750_SCFCR2_RTRG_1 | SH7750_SCFCR2_TTRG_4; |
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248 | |
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249 | if (chn == SH4_SCI) |
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250 | SCSPTR1 = int_driven ? 0x0 : SH7750_SCSPTR1_EIO; |
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251 | else |
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252 | SCSPTR2 = SH7750_SCSPTR2_RTSDT; |
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253 | |
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254 | if (int_driven) |
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255 | { |
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256 | rtems_unsigned16 ipr; |
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257 | |
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258 | if (chn == SH4_SCI) |
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259 | { |
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260 | ipr = IPRB; |
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261 | ipr &= ~SH7750_IPRB_SCI1; |
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262 | ipr |= SH4_UART_INTERRUPT_LEVEL << SH7750_IPRB_SCI1_S; |
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263 | IPRB = ipr; |
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264 | |
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265 | rc = rtems_interrupt_catch(sh4uart1_interrupt_transmit, |
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266 | SH7750_EVT_TO_NUM(SH7750_EVT_SCI_TXI), |
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267 | &uart->old_handler_transmit); |
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268 | if (rc != RTEMS_SUCCESSFUL) |
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269 | return rc; |
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270 | rc = rtems_interrupt_catch(sh4uart1_interrupt_receive, |
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271 | SH7750_EVT_TO_NUM(SH7750_EVT_SCI_RXI), |
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272 | &uart->old_handler_receive); |
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273 | if (rc != RTEMS_SUCCESSFUL) |
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274 | return rc; |
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275 | } |
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276 | else |
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277 | { |
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278 | ipr = IPRC; |
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279 | ipr &= ~SH7750_IPRC_SCIF; |
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280 | ipr |= SH4_UART_INTERRUPT_LEVEL << SH7750_IPRC_SCIF_S; |
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281 | IPRC = ipr; |
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282 | |
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283 | rc = rtems_interrupt_catch(sh4uart2_interrupt_transmit, |
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284 | SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_TXI), |
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285 | &uart->old_handler_transmit); |
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286 | if (rc != RTEMS_SUCCESSFUL) |
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287 | return rc; |
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288 | rc = rtems_interrupt_catch(sh4uart2_interrupt_receive, |
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289 | SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_RXI), |
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290 | &uart->old_handler_receive); |
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291 | if (rc != RTEMS_SUCCESSFUL) |
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292 | return rc; |
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293 | } |
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294 | uart->tx_buf = NULL; |
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295 | uart->tx_ptr = uart->tx_buf_len = 0; |
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296 | } |
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297 | |
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298 | sh4uart_set_baudrate(uart, B38400); /* debug defaults (unfortunately, |
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299 | it is differ to termios default */ |
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300 | |
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301 | SCSCR(chn) = SH7750_SCSCR_TE | SH7750_SCSCR_RE | |
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302 | (chn == SH4_SCI ? 0x0 : SH7750_SCSCR2_REIE) | |
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303 | (int_driven ? (SH7750_SCSCR_RIE | SH7750_SCSCR_TIE) : 0x0); |
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304 | |
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305 | return RTEMS_SUCCESSFUL; |
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306 | } |
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307 | |
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308 | /* |
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309 | * sh4uart_disable -- |
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310 | * This function disable the operations on SH-4 UART controller |
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311 | * |
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312 | * PARAMETERS: |
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313 | * uart - pointer to UART channel descriptor structure |
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314 | * |
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315 | * RETURNS: |
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316 | * RTEMS_SUCCESSFUL if UART closed successfuly, or error code in |
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317 | * other case |
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318 | */ |
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319 | rtems_status_code |
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320 | sh4uart_disable(sh4uart *uart) |
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321 | { |
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322 | rtems_status_code rc; |
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323 | |
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324 | SCSCR(uart->chn) &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE); |
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325 | |
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326 | if (uart->int_driven) |
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327 | { |
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328 | rc = rtems_interrupt_catch(uart->old_handler_transmit, |
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329 | uart->chn == SH4_SCI ? |
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330 | SH7750_EVT_SCI_TXI : SH7750_EVT_SCIF_TXI, |
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331 | NULL); |
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332 | if (rc != RTEMS_SUCCESSFUL) |
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333 | return rc; |
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334 | rc = rtems_interrupt_catch(uart->old_handler_receive, |
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335 | uart->chn == SH4_SCI ? |
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336 | SH7750_EVT_SCI_RXI : SH7750_EVT_SCIF_RXI, |
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337 | NULL); |
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338 | if (rc != RTEMS_SUCCESSFUL) |
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339 | return rc; |
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340 | } |
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341 | |
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342 | return RTEMS_SUCCESSFUL; |
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343 | } |
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344 | |
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345 | /* |
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346 | * sh4uart_set_attributes -- |
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347 | * This function parse the termios attributes structure and perform |
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348 | * the appropriate settings in hardware. |
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349 | * |
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350 | * PARAMETERS: |
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351 | * uart - pointer to the UART descriptor structure |
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352 | * t - pointer to termios parameters |
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353 | * |
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354 | * RETURNS: |
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355 | * RTEMS_SUCCESSFUL |
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356 | */ |
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357 | rtems_status_code |
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358 | sh4uart_set_attributes(sh4uart *uart, const struct termios *t) |
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359 | { |
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360 | int level; |
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361 | speed_t baud; |
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362 | rtems_unsigned16 smr; |
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363 | |
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364 | smr = (rtems_unsigned16)(*(rtems_unsigned8 *)SH7750_SCSMR(uart->chn)); |
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365 | |
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366 | baud = cfgetospeed(t); |
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367 | |
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368 | /* Set flow control XXX*/ |
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369 | if ((t->c_cflag & CRTSCTS) != 0) |
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370 | { |
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371 | } |
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372 | |
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373 | /* Set character size -- only 7 or 8 bit */ |
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374 | switch (t->c_cflag & CSIZE) |
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375 | { |
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376 | case CS5: |
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377 | case CS6: |
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378 | case CS7: smr |= SH7750_SCSMR_CHR_7; break; |
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379 | case CS8: smr &= ~SH7750_SCSMR_CHR_7; break; |
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380 | } |
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381 | |
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382 | /* Set number of stop bits */ |
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383 | if ((t->c_cflag & CSTOPB) != 0) |
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384 | smr |= SH7750_SCSMR_STOP_2; |
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385 | else |
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386 | smr &= ~SH7750_SCSMR_STOP_2; |
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387 | |
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388 | /* Set parity mode */ |
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389 | if ((t->c_cflag & PARENB) != 0) |
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390 | { |
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391 | smr |= SH7750_SCSMR_PE; |
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392 | if ((t->c_cflag & PARODD) != 0) |
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393 | smr |= SH7750_SCSMR_PM_ODD; |
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394 | else |
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395 | smr &= ~SH7750_SCSMR_PM_ODD; |
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396 | } |
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397 | else |
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398 | smr &= ~SH7750_SCSMR_PE; |
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399 | |
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400 | rtems_interrupt_disable(level); |
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401 | /* wait untill all data is transmitted */ |
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402 | rtems_task_wake_after(RTEMS_MILLISECONDS_TO_TICKS(100)); |
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403 | /* disable operations */ |
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404 | SCSCR(uart->chn) &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE); |
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405 | |
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406 | sh4uart_set_baudrate(uart, baud); |
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407 | SCSMR(uart->chn) = (rtems_unsigned8)smr; |
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408 | |
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409 | /* enable operations */ |
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410 | SCSCR(uart->chn) |= SH7750_SCSCR_TE | SH7750_SCSCR_RE; |
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411 | rtems_interrupt_enable(level); |
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412 | |
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413 | return RTEMS_SUCCESSFUL; |
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414 | } |
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415 | |
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416 | /* |
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417 | * sh4uart_handle_error -- |
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418 | * Perfoms error (Overrun, Framing & Parity) handling |
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419 | * |
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420 | * PARAMETERS: |
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421 | * uart - pointer to UART descriptor structure |
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422 | * |
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423 | * RETURNS: |
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424 | * nothing |
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425 | */ |
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426 | void |
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427 | sh4uart_handle_error(sh4uart *uart) |
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428 | { |
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429 | #if 0 |
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430 | int status_reg = SCSSR(uart->chn); |
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431 | #endif |
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432 | |
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433 | if(uart->chn == SH4_SCI) |
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434 | { |
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435 | SCSSR1 &= ~(SH7750_SCSSR1_ORER | SH7750_SCSSR1_FER | SH7750_SCSSR1_PER); |
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436 | } |
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437 | else |
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438 | { |
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439 | SCSSR2 &= ~(SH7750_SCSSR2_ER | SH7750_SCSSR2_BRK | SH7750_SCSSR2_FER); |
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440 | SCLSR2 &= ~(SH7750_SCLSR2_ORER); |
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441 | } |
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442 | } |
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443 | |
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444 | /* |
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445 | * sh4uart_poll_read -- |
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446 | * This function tried to read character from SH-4 UART and perform |
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447 | * error handling. When parity or framing error occured, return |
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448 | * value dependent on termios input mode flags: |
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449 | * - received character, if IGNPAR == 1 |
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450 | * - 0, if IGNPAR == 0 and PARMRK == 0 |
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451 | * - 0xff and 0x00 on next poll_read invocation, if IGNPAR == 0 and |
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452 | * PARMRK == 1 |
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453 | * |
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454 | * PARAMETERS: |
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455 | * uart - pointer to UART descriptor structure |
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456 | * |
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457 | * RETURNS: |
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458 | * code of received character or -1 if no characters received. |
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459 | */ |
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460 | int |
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461 | sh4uart_poll_read(sh4uart *uart) |
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462 | { |
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463 | int chn = uart->chn; |
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464 | int error_occured = 0; |
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465 | int parity_error = 0; |
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466 | int break_occured = 0; |
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467 | int ch; |
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468 | |
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469 | if (uart->parerr_mark_flag == 1) |
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470 | { |
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471 | uart->parerr_mark_flag = 0; |
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472 | return 0; |
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473 | } |
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474 | |
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475 | if (chn == SH4_SCI) |
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476 | { |
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477 | if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER | |
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478 | SH7750_SCSSR1_ORER)) != 0) |
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479 | { |
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480 | error_occured = 1; |
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481 | if (SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER)) |
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482 | parity_error = 1; |
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483 | sh4uart_handle_error(uart); |
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484 | } |
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485 | if ((SCSSR1 & SH7750_SCSSR1_RDRF) == 0) |
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486 | return -1; |
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487 | } |
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488 | else |
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489 | { |
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490 | if ((SCSSR2 & (SH7750_SCSSR2_ER | SH7750_SCSSR2_DR | |
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491 | SH7750_SCSSR2_BRK)) != 0 || |
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492 | (SCLSR2 & SH7750_SCLSR2_ORER) != 0) |
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493 | { |
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494 | error_occured = 1; |
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495 | if (SCSSR2 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER)) |
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496 | parity_error = 1; |
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497 | if (SCSSR2 & SH7750_SCSSR2_BRK) |
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498 | break_occured = 1; |
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499 | sh4uart_handle_error(uart); |
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500 | } |
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501 | if ((SCSSR2 & SH7750_SCSSR2_RDF) == 0) |
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502 | return -1; |
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503 | } |
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504 | |
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505 | if (parity_error && !(uart->c_iflag & IGNPAR)) |
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506 | { |
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507 | if (uart->c_iflag & PARMRK) |
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508 | { |
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509 | uart->parerr_mark_flag = 1; |
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510 | return 0xff; |
---|
511 | } |
---|
512 | else |
---|
513 | return 0; |
---|
514 | } |
---|
515 | |
---|
516 | if (break_occured && !(uart->c_iflag & BRKINT)) |
---|
517 | { |
---|
518 | if (uart->c_iflag & IGNBRK) |
---|
519 | return 0; |
---|
520 | else |
---|
521 | return 0; /* XXX -- SIGINT */ |
---|
522 | } |
---|
523 | |
---|
524 | ch = SCRDR(chn); |
---|
525 | if (uart->chn == SH4_SCI) |
---|
526 | SCSSR1 &= ~SH7750_SCSSR1_RDRF; |
---|
527 | else |
---|
528 | SCSSR2 &= ~SH7750_SCSSR2_RDF; |
---|
529 | |
---|
530 | return ch; |
---|
531 | } |
---|
532 | |
---|
533 | /* |
---|
534 | * sh4uart_poll_write -- |
---|
535 | * This function transmit buffer byte-by-byte in polling mode. |
---|
536 | * |
---|
537 | * PARAMETERS: |
---|
538 | * uart - pointer to the UART descriptor structure |
---|
539 | * buf - pointer to transmit buffer |
---|
540 | * len - transmit buffer length |
---|
541 | * |
---|
542 | * RETURNS: |
---|
543 | * 0 |
---|
544 | */ |
---|
545 | int |
---|
546 | sh4uart_poll_write(sh4uart *uart, const char *buf, int len) |
---|
547 | { |
---|
548 | while (len) |
---|
549 | { |
---|
550 | if (uart->chn == SH4_SCI) |
---|
551 | { |
---|
552 | while ((SCSSR1 & SH7750_SCSSR1_TDRE) != 0) |
---|
553 | { |
---|
554 | SCTDR1 = *buf++; |
---|
555 | len--; |
---|
556 | SCSSR1 &= ~SH7750_SCSSR1_TDRE; |
---|
557 | } |
---|
558 | } |
---|
559 | else |
---|
560 | { |
---|
561 | while ((SCSSR2 & SH7750_SCSSR2_TDFE) != 0) |
---|
562 | { |
---|
563 | int i; |
---|
564 | for (i = 0; |
---|
565 | i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 & |
---|
566 | SH7750_SCFCR2_TTRG); |
---|
567 | i++) |
---|
568 | { |
---|
569 | SCTDR2 = *buf++; |
---|
570 | len--; |
---|
571 | } |
---|
572 | while ((SCSSR2 & SH7750_SCSSR2_TDFE) == 0 || |
---|
573 | (SCSSR2 & SH7750_SCSSR2_TEND) == 0); |
---|
574 | SCSSR2 &= ~(SH7750_SCSSR1_TDRE | SH7750_SCSSR2_TEND); |
---|
575 | } |
---|
576 | } |
---|
577 | } |
---|
578 | return 0; |
---|
579 | } |
---|
580 | |
---|
581 | /********************************** |
---|
582 | * Functions to handle interrupts * |
---|
583 | **********************************/ |
---|
584 | /* sh4uart1_interrupt_receive -- |
---|
585 | * UART interrupt handler routine -- SCI |
---|
586 | * Receiving data |
---|
587 | * |
---|
588 | * PARAMETERS: |
---|
589 | * vec - interrupt vector number |
---|
590 | * |
---|
591 | * RETURNS: |
---|
592 | * none |
---|
593 | */ |
---|
594 | static rtems_isr |
---|
595 | sh4uart1_interrupt_receive(rtems_vector_number vec) |
---|
596 | { |
---|
597 | register int bp = 0; |
---|
598 | char buf[32]; |
---|
599 | |
---|
600 | /* Find UART descriptor from vector number */ |
---|
601 | sh4uart *uart = &sh4_uarts[0]; |
---|
602 | |
---|
603 | while (1) |
---|
604 | { |
---|
605 | if ((bp < sizeof(buf) - 1) && ((SCSSR1 & SH7750_SCSSR1_RDRF) != 0)) |
---|
606 | { |
---|
607 | /* Receive character and handle frame/parity errors */ |
---|
608 | if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER | |
---|
609 | SH7750_SCSSR1_ORER)) != 0) |
---|
610 | { |
---|
611 | if (SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER)) |
---|
612 | { |
---|
613 | if(!(uart->c_iflag & IGNPAR)) |
---|
614 | { |
---|
615 | if (uart->c_iflag & PARMRK) |
---|
616 | { |
---|
617 | buf[bp++] = 0xff; |
---|
618 | buf[bp++] = 0x00; |
---|
619 | } |
---|
620 | else |
---|
621 | buf[bp++] = 0x00; |
---|
622 | } |
---|
623 | else |
---|
624 | buf[bp++] = SCRDR1; |
---|
625 | } |
---|
626 | sh4uart_handle_error(uart); |
---|
627 | } |
---|
628 | else |
---|
629 | buf[bp++] = SCRDR1; |
---|
630 | SCSSR1 &= ~SH7750_SCSSR1_RDRF; |
---|
631 | } |
---|
632 | else |
---|
633 | { |
---|
634 | if (bp != 0) |
---|
635 | rtems_termios_enqueue_raw_characters(uart->tty, buf, bp); |
---|
636 | break; |
---|
637 | } |
---|
638 | } |
---|
639 | } |
---|
640 | |
---|
641 | /* sh4uart2_interrupt_receive -- |
---|
642 | * UART interrupt handler routine -- SCIF |
---|
643 | * Receiving data |
---|
644 | * |
---|
645 | * PARAMETERS: |
---|
646 | * vec - interrupt vector number |
---|
647 | * |
---|
648 | * RETURNS: |
---|
649 | * none |
---|
650 | */ |
---|
651 | static rtems_isr |
---|
652 | sh4uart2_interrupt_receive(rtems_vector_number vec) |
---|
653 | { |
---|
654 | register int bp = 0; |
---|
655 | char buf[32]; |
---|
656 | |
---|
657 | /* Find UART descriptor from vector number */ |
---|
658 | sh4uart *uart = &sh4_uarts[1]; |
---|
659 | |
---|
660 | while (1) |
---|
661 | { |
---|
662 | if ((bp < sizeof(buf) - 1) && ((SCSSR2 & SH7750_SCSSR2_RDF) != 0)) |
---|
663 | { |
---|
664 | if ((SCSSR2 & (SH7750_SCSSR2_ER | SH7750_SCSSR2_DR | |
---|
665 | SH7750_SCSSR2_BRK)) != 0 || |
---|
666 | (SH7750_SCLSR2 & SH7750_SCLSR2_ORER) != 0) |
---|
667 | { |
---|
668 | if (SCSSR2 & SH7750_SCSSR2_ER) |
---|
669 | { |
---|
670 | if(!(uart->c_iflag & IGNPAR)) |
---|
671 | { |
---|
672 | if (uart->c_iflag & PARMRK) |
---|
673 | { |
---|
674 | buf[bp++] = 0xff; |
---|
675 | buf[bp++] = 0x00; |
---|
676 | } |
---|
677 | else |
---|
678 | buf[bp++] = 0x00; |
---|
679 | } |
---|
680 | else |
---|
681 | buf[bp++] = SCRDR1; |
---|
682 | } |
---|
683 | |
---|
684 | if (SCSSR2 & SH7750_SCSSR2_BRK) |
---|
685 | { |
---|
686 | if (uart->c_iflag & IGNBRK) |
---|
687 | buf[bp++] = 0x00; |
---|
688 | else |
---|
689 | buf[bp++] = 0x00; /* XXX -- SIGINT */ |
---|
690 | } |
---|
691 | |
---|
692 | sh4uart_handle_error(uart); |
---|
693 | } |
---|
694 | else |
---|
695 | buf[bp++] = SCRDR1; |
---|
696 | SCSSR2 &= ~SH7750_SCSSR2_RDF; |
---|
697 | } |
---|
698 | else |
---|
699 | { |
---|
700 | if (bp != 0) |
---|
701 | rtems_termios_enqueue_raw_characters(uart->tty, buf, bp); |
---|
702 | break; |
---|
703 | } |
---|
704 | } |
---|
705 | } |
---|
706 | |
---|
707 | |
---|
708 | /* sh4uart1_interrupt_transmit -- |
---|
709 | * UART interrupt handler routine -- SCI |
---|
710 | * It continues transmit data when old part of data is transmitted |
---|
711 | * |
---|
712 | * PARAMETERS: |
---|
713 | * vec - interrupt vector number |
---|
714 | * |
---|
715 | * RETURNS: |
---|
716 | * none |
---|
717 | */ |
---|
718 | static rtems_isr |
---|
719 | sh4uart1_interrupt_transmit(rtems_vector_number vec) |
---|
720 | { |
---|
721 | /* Find UART descriptor from vector number */ |
---|
722 | sh4uart *uart = &sh4_uarts[0]; |
---|
723 | |
---|
724 | if (uart->tx_buf != NULL && uart->tx_ptr < uart->tx_buf_len) |
---|
725 | { |
---|
726 | while ((SCSSR1 & SH7750_SCSSR1_TDRE) != 0 && |
---|
727 | uart->tx_ptr < uart->tx_buf_len) |
---|
728 | { |
---|
729 | SCTDR1 = uart->tx_buf[uart->tx_ptr++]; |
---|
730 | SCSSR1 &= ~SH7750_SCSSR1_TDRE; |
---|
731 | } |
---|
732 | } |
---|
733 | else |
---|
734 | { |
---|
735 | register int dequeue = uart->tx_buf_len; |
---|
736 | |
---|
737 | uart->tx_buf = NULL; |
---|
738 | uart->tx_ptr = uart->tx_buf_len = 0; |
---|
739 | |
---|
740 | /* Disable interrupts while we do not have any data to transmit */ |
---|
741 | SCSCR1 &= ~SH7750_SCSCR_TIE; |
---|
742 | |
---|
743 | rtems_termios_dequeue_characters(uart->tty, dequeue); |
---|
744 | } |
---|
745 | } |
---|
746 | |
---|
747 | /* sh4uart2_interrupt_transmit -- |
---|
748 | * UART interrupt handler routine -- SCI |
---|
749 | * It continues transmit data when old part of data is transmitted |
---|
750 | * |
---|
751 | * PARAMETERS: |
---|
752 | * vec - interrupt vector number |
---|
753 | * |
---|
754 | * RETURNS: |
---|
755 | * none |
---|
756 | */ |
---|
757 | static rtems_isr |
---|
758 | sh4uart2_interrupt_transmit(rtems_vector_number vec) |
---|
759 | { |
---|
760 | /* Find UART descriptor from vector number */ |
---|
761 | sh4uart *uart = &sh4_uarts[1]; |
---|
762 | |
---|
763 | if (uart->tx_buf != NULL && uart->tx_ptr < uart->tx_buf_len) |
---|
764 | { |
---|
765 | while ((SCSSR2 & SH7750_SCSSR2_TDFE) != 0) |
---|
766 | { |
---|
767 | int i; |
---|
768 | for (i = 0; |
---|
769 | i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 & |
---|
770 | SH7750_SCFCR2_TTRG); |
---|
771 | i++) |
---|
772 | SCTDR2 = uart->tx_buf[uart->tx_ptr++]; |
---|
773 | while ((SCSSR1 & SH7750_SCSSR1_TDRE) == 0 || |
---|
774 | (SCSSR1 & SH7750_SCSSR1_TEND) == 0); |
---|
775 | SCSSR1 &= ~(SH7750_SCSSR1_TDRE | SH7750_SCSSR2_TEND); |
---|
776 | } |
---|
777 | } |
---|
778 | else |
---|
779 | { |
---|
780 | register int dequeue = uart->tx_buf_len; |
---|
781 | |
---|
782 | uart->tx_buf = NULL; |
---|
783 | uart->tx_ptr = uart->tx_buf_len = 0; |
---|
784 | |
---|
785 | /* Disable interrupts while we do not have any data to transmit */ |
---|
786 | SCSCR2 &= ~SH7750_SCSCR_TIE; |
---|
787 | |
---|
788 | rtems_termios_dequeue_characters(uart->tty, dequeue); |
---|
789 | } |
---|
790 | } |
---|
791 | |
---|
792 | /* sh4uart_interrupt_write -- |
---|
793 | * This function initiate transmitting of the buffer in interrupt mode. |
---|
794 | * |
---|
795 | * PARAMETERS: |
---|
796 | * uart - pointer to the UART descriptor structure |
---|
797 | * buf - pointer to transmit buffer |
---|
798 | * len - transmit buffer length |
---|
799 | * |
---|
800 | * RETURNS: |
---|
801 | * 0 |
---|
802 | */ |
---|
803 | rtems_status_code |
---|
804 | sh4uart_interrupt_write(sh4uart *uart, const char *buf, int len) |
---|
805 | { |
---|
806 | int level; |
---|
807 | |
---|
808 | while ((SCSSR1 & SH7750_SCSSR1_TEND) == 0); |
---|
809 | |
---|
810 | rtems_interrupt_disable(level); |
---|
811 | |
---|
812 | uart->tx_buf = buf; |
---|
813 | uart->tx_buf_len = len; |
---|
814 | uart->tx_ptr = 0; |
---|
815 | |
---|
816 | if (uart->chn == SH4_SCI) |
---|
817 | { |
---|
818 | SCSCR1 |= SH7750_SCSCR_TIE; |
---|
819 | } |
---|
820 | else |
---|
821 | SCSCR2 |= SH7750_SCSCR_TIE; |
---|
822 | |
---|
823 | rtems_interrupt_enable(level); |
---|
824 | |
---|
825 | return RTEMS_SUCCESSFUL; |
---|
826 | } |
---|
827 | |
---|
828 | /* sh4uart_stop_remote_tx -- |
---|
829 | * This function stop data flow from remote device. |
---|
830 | * |
---|
831 | * PARAMETERS: |
---|
832 | * uart - pointer to the UART descriptor structure |
---|
833 | * |
---|
834 | * RETURNS: |
---|
835 | * RTEMS_SUCCESSFUL |
---|
836 | */ |
---|
837 | rtems_status_code |
---|
838 | sh4uart_stop_remote_tx(sh4uart *uart) |
---|
839 | { |
---|
840 | SCSCR(uart->chn) &= ~(SH7750_SCSCR_RIE | SH7750_SCSCR_RE); |
---|
841 | return RTEMS_SUCCESSFUL; |
---|
842 | } |
---|
843 | |
---|
844 | /* sh4uart_start_remote_tx -- |
---|
845 | * This function resume data flow from remote device. |
---|
846 | * |
---|
847 | * PARAMETERS: |
---|
848 | * uart - pointer to the UART descriptor structure |
---|
849 | * |
---|
850 | * RETURNS: |
---|
851 | * RTEMS_SUCCESSFUL |
---|
852 | */ |
---|
853 | rtems_status_code |
---|
854 | sh4uart_start_remote_tx(sh4uart *uart) |
---|
855 | { |
---|
856 | SCSCR(uart->chn) |= SH7750_SCSCR_RIE | SH7750_SCSCR_RE; |
---|
857 | return RTEMS_SUCCESSFUL; |
---|
858 | } |
---|
859 | |
---|
860 | #ifdef SH4_WITH_IPL |
---|
861 | /********************************* |
---|
862 | * Functions for SH-IPL gdb stub * |
---|
863 | *********************************/ |
---|
864 | |
---|
865 | /* |
---|
866 | * ipl_finish -- |
---|
867 | * Says gdb that program finished to get out from it. |
---|
868 | */ |
---|
869 | extern void ipl_finish(void); |
---|
870 | asm( |
---|
871 | " .global _ipl_finish\n" |
---|
872 | "_ipl_finish:\n" |
---|
873 | " mov.l __ipl_finish_value, r0\n" |
---|
874 | " trapa #0x3f\n" |
---|
875 | " nop\n" |
---|
876 | " rts\n" |
---|
877 | " nop\n" |
---|
878 | " .align 4\n" |
---|
879 | "__ipl_finish_value:\n" |
---|
880 | " .long 255" |
---|
881 | ); |
---|
882 | |
---|
883 | extern int ipl_serial_input(int poll_count); |
---|
884 | asm( |
---|
885 | " .global _ipl_serial_input\n" |
---|
886 | "_ipl_serial_input:\n" |
---|
887 | " mov #1,r0\n" |
---|
888 | " trapa #0x3f\n" |
---|
889 | " nop\n" |
---|
890 | " rts\n" |
---|
891 | " nop\n"); |
---|
892 | |
---|
893 | extern void ipl_serial_output(const char *buf, int len); |
---|
894 | asm ( |
---|
895 | " .global _ipl_serial_output\n" |
---|
896 | "_ipl_serial_output:\n" |
---|
897 | " mov #0,r0\n" |
---|
898 | " trapa #0x3f\n" |
---|
899 | " nop\n" |
---|
900 | " rts\n" |
---|
901 | " nop\n"); |
---|
902 | |
---|
903 | /* ipl_console_poll_read -- |
---|
904 | * poll read operation for simulator console through ipl mechanism. |
---|
905 | * |
---|
906 | * PARAMETERS: |
---|
907 | * minor - minor device number |
---|
908 | * |
---|
909 | * RETURNS: |
---|
910 | * character code red from UART, or -1 if there is no characters |
---|
911 | * available |
---|
912 | */ |
---|
913 | int |
---|
914 | ipl_console_poll_read(int minor) |
---|
915 | { |
---|
916 | unsigned char buf; |
---|
917 | buf = ipl_serial_input(0x100000); |
---|
918 | return buf; |
---|
919 | } |
---|
920 | |
---|
921 | /* ipl_console_poll_write -- |
---|
922 | * wrapper for polling mode write function |
---|
923 | * |
---|
924 | * PARAMETERS: |
---|
925 | * minor - minor device number |
---|
926 | * buf - output buffer |
---|
927 | * len - output buffer length |
---|
928 | * |
---|
929 | * RETURNS: |
---|
930 | * result code (0) |
---|
931 | */ |
---|
932 | int |
---|
933 | ipl_console_poll_write(int minor, const char *buf, int len) |
---|
934 | { |
---|
935 | int c; |
---|
936 | while (len > 0) |
---|
937 | { |
---|
938 | c = (len < 64 ? len : 64); |
---|
939 | ipl_serial_output(buf, c); |
---|
940 | len -= c; |
---|
941 | buf += c; |
---|
942 | } |
---|
943 | return 0; |
---|
944 | } |
---|
945 | #endif |
---|