[ba71076] | 1 | /* |
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| 2 | * Generic UART Serial driver for SH-4 processors |
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| 3 | * |
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| 4 | * This driver uses variable SH4_CPU_HZ_Frequency, |
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| 5 | * which should be defined in bsp to HZ macro. |
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| 6 | * |
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| 7 | * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russian Fed. |
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| 8 | * Author: Alexandra Kossovsky <sasha@oktet.ru> |
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| 9 | * |
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| 10 | * COPYRIGHT (c) 1989-2000. |
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| 11 | * On-Line Applications Research Corporation (OAR). |
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| 12 | * |
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| 13 | * The license and distribution terms for this file may be |
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| 14 | * found in the file LICENSE in this distribution or at |
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| 15 | * |
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| 16 | * http://www.OARcorp.com/rtems/license.html. |
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| 17 | * |
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| 18 | * $Id$ |
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| 19 | * |
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| 20 | */ |
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| 21 | |
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| 22 | #include <rtems.h> |
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| 23 | #include <termios.h> |
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| 24 | #include <rtems/libio.h> |
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| 25 | #include "sh/sh4uart.h" |
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| 26 | |
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| 27 | #ifndef SH4_UART_INTERRUPT_LEVEL |
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| 28 | #define SH4_UART_INTERRUPT_LEVEL 4 |
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| 29 | #endif |
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| 30 | |
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| 31 | /* Forward function declarations */ |
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| 32 | static rtems_isr |
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| 33 | sh4uart1_interrupt_transmit(rtems_vector_number vec); |
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| 34 | static rtems_isr |
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| 35 | sh4uart1_interrupt_receive(rtems_vector_number vec); |
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| 36 | static rtems_isr |
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| 37 | sh4uart2_interrupt_transmit(rtems_vector_number vec); |
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| 38 | static rtems_isr |
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| 39 | sh4uart2_interrupt_receive(rtems_vector_number vec); |
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| 40 | |
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| 41 | /* |
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| 42 | * sh4uart_init -- |
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| 43 | * This function verifies the input parameters and perform initialization |
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| 44 | * of the SH-4 on-chip UART descriptor structure. |
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| 45 | * |
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| 46 | * PARAMETERS: |
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| 47 | * uart - pointer to the UART channel descriptor structure |
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| 48 | * tty - pointer to termios structure |
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| 49 | * chn - channel number (SH4_SCI/SH4_SCIF -- 1/2) |
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| 50 | * int_driven - interrupt-driven (1) or polled (0) I/O mode |
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| 51 | * |
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| 52 | * RETURNS: |
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| 53 | * RTEMS_SUCCESSFUL if all parameters are valid, or error code |
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| 54 | */ |
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| 55 | rtems_status_code |
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| 56 | sh4uart_init(sh4uart *uart, void *tty, int chn, int int_driven) |
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| 57 | { |
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| 58 | if (uart == NULL) |
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| 59 | return RTEMS_INVALID_ADDRESS; |
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| 60 | |
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| 61 | if ((chn != SH4_SCI) && (chn != SH4_SCIF)) |
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| 62 | return RTEMS_INVALID_NUMBER; |
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| 63 | |
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| 64 | uart->chn = chn; |
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| 65 | uart->tty = tty; |
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| 66 | uart->int_driven = int_driven; |
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| 67 | |
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| 68 | #if 0 |
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| 69 | sh4uart_poll_write(uart, "init", 4); |
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| 70 | #endif |
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| 71 | return RTEMS_SUCCESSFUL; |
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| 72 | } |
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| 73 | |
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| 74 | /* |
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| 75 | * sh4uart_get_Pph -- |
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| 76 | * Get current peripheral module clock. |
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| 77 | * |
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| 78 | * PARAMETERS: none; |
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| 79 | * Cpu clock is get from SH4_CPU_HZ_Frequency. |
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| 80 | * This variable should be defined in bsp. |
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| 81 | * |
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| 82 | * RETURNS: |
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| 83 | * peripheral module clock in Hz. |
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| 84 | */ |
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| 85 | rtems_unsigned32 |
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| 86 | sh4uart_get_Pph(void) |
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| 87 | { |
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| 88 | rtems_unsigned16 frqcr = *(volatile rtems_unsigned16 *)SH7750_FRQCR; |
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| 89 | rtems_unsigned32 Pph = SH4_CPU_HZ_Frequency; |
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| 90 | |
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| 91 | switch (frqcr & SH7750_FRQCR_IFC) |
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| 92 | { |
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| 93 | case SH7750_FRQCR_IFCDIV1: |
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| 94 | break; |
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| 95 | |
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| 96 | case SH7750_FRQCR_IFCDIV2: |
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| 97 | Pph *= 2; |
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| 98 | break; |
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| 99 | |
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| 100 | case SH7750_FRQCR_IFCDIV3: |
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| 101 | Pph *= 3; |
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| 102 | break; |
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| 103 | |
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| 104 | case SH7750_FRQCR_IFCDIV4: |
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| 105 | Pph *= 4; |
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| 106 | break; |
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| 107 | |
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| 108 | case SH7750_FRQCR_IFCDIV6: |
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| 109 | Pph *= 6; |
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| 110 | break; |
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| 111 | |
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| 112 | case SH7750_FRQCR_IFCDIV8: |
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| 113 | Pph *= 8; |
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| 114 | break; |
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| 115 | |
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| 116 | default: /* unreachable */ |
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| 117 | break; |
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| 118 | } |
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| 119 | |
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| 120 | switch (frqcr & SH7750_FRQCR_PFC) |
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| 121 | { |
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| 122 | case SH7750_FRQCR_PFCDIV2: |
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| 123 | Pph /= 2; |
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| 124 | break; |
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| 125 | |
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| 126 | case SH7750_FRQCR_PFCDIV3: |
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| 127 | Pph /= 3; |
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| 128 | break; |
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| 129 | |
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| 130 | case SH7750_FRQCR_PFCDIV4: |
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| 131 | Pph /= 4; |
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| 132 | break; |
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| 133 | |
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| 134 | case SH7750_FRQCR_PFCDIV6: |
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| 135 | Pph /= 6; |
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| 136 | break; |
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| 137 | |
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| 138 | case SH7750_FRQCR_PFCDIV8: |
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| 139 | Pph /= 8; |
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| 140 | break; |
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| 141 | |
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| 142 | default: /* unreachable */ |
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| 143 | break; |
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| 144 | } |
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| 145 | |
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| 146 | return Pph; |
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| 147 | } |
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| 148 | |
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| 149 | /* |
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| 150 | * sh4uart_set_baudrate -- |
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| 151 | * Program the UART timer to specified baudrate |
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| 152 | * |
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| 153 | * PARAMETERS: |
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| 154 | * uart - pointer to UART descriptor structure |
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| 155 | * baud - termios baud rate (B50, B9600, etc...) |
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| 156 | * |
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| 157 | * ALGORITHM: |
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| 158 | * see SH7750 Hardware Manual. |
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| 159 | * |
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| 160 | * RETURNS: |
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| 161 | * none |
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| 162 | */ |
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| 163 | static void |
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| 164 | sh4uart_set_baudrate(sh4uart *uart, speed_t baud) |
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| 165 | { |
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| 166 | rtems_unsigned32 rate; |
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| 167 | rtems_signed16 div; |
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| 168 | int n; |
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| 169 | rtems_unsigned32 Pph = sh4uart_get_Pph(); |
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| 170 | |
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| 171 | switch (baud) |
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| 172 | { |
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| 173 | case B50: rate = 50; break; |
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| 174 | case B75: rate = 75; break; |
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| 175 | case B110: rate = 110; break; |
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| 176 | case B134: rate = 134; break; |
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| 177 | case B150: rate = 150; break; |
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| 178 | case B200: rate = 200; break; |
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| 179 | case B300: rate = 300; break; |
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| 180 | case B600: rate = 600; break; |
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| 181 | case B1200: rate = 1200; break; |
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| 182 | case B2400: rate = 2400; break; |
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| 183 | case B4800: rate = 4800; break; |
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| 184 | case B9600: rate = 9600; break; |
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| 185 | case B19200: rate = 19200; break; |
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| 186 | case B38400: rate = 38400; break; |
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| 187 | case B57600: rate = 57600; break; |
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| 188 | #ifdef B115200 |
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| 189 | case B115200: rate = 115200; break; |
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| 190 | #endif |
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| 191 | #ifdef B230400 |
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| 192 | case B230400: rate = 230400; break; |
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| 193 | #endif |
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| 194 | default: rate = 9600; break; |
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| 195 | } |
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| 196 | |
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| 197 | for (n = 0; n < 4; n++) |
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| 198 | { |
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| 199 | div = Pph / (32 * (1 << (2 * n)) * rate) - 1; |
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| 200 | if (div < 0x100) |
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| 201 | break; |
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| 202 | } |
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| 203 | |
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| 204 | /* Set default baudrate if specified baudrate is impossible */ |
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| 205 | if (n >= 4) |
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| 206 | sh4uart_set_baudrate(uart, B9600); |
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| 207 | |
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| 208 | SCSMR(uart->chn) &= ~SH7750_SCSMR_CKS; |
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| 209 | SCSMR(uart->chn) |= n << SH7750_SCSMR_CKS_S; |
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| 210 | SCBRR(uart->chn) = div; |
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| 211 | /* Whait at least 1 bit interwal */ |
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| 212 | rtems_task_wake_after(RTEMS_MILLISECONDS_TO_TICKS(1000 / rate)); |
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| 213 | } |
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| 214 | |
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| 215 | /* |
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| 216 | * sh4uart_reset -- |
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| 217 | * This function perform the hardware initialization of SH-4 |
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| 218 | * on-chip UART controller using parameters |
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| 219 | * filled by the sh4uart_init function. |
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| 220 | * |
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| 221 | * PARAMETERS: |
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| 222 | * uart - pointer to UART channel descriptor structure |
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| 223 | * |
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| 224 | * RETURNS: |
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| 225 | * RTEMS_SUCCESSFUL if channel is initialized successfully, error |
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| 226 | * code in other case |
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| 227 | */ |
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| 228 | rtems_status_code |
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| 229 | sh4uart_reset(sh4uart *uart) |
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| 230 | { |
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| 231 | register int chn; |
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| 232 | register int int_driven; |
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| 233 | rtems_status_code rc; |
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| 234 | |
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| 235 | if (uart == NULL) |
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| 236 | return RTEMS_INVALID_ADDRESS; |
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| 237 | |
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| 238 | chn = uart->chn; |
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| 239 | int_driven = uart->int_driven; |
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| 240 | |
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| 241 | SCSCR(chn) = 0x0; /* Is set properly at the end of this function */ |
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| 242 | SCSMR(chn) = 0x0; /* 8-bit, non-parity, 1 stop bit, pf/1 clock */ |
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| 243 | |
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| 244 | if (chn == SH4_SCIF) |
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| 245 | SCFCR2 = SH7750_SCFCR2_TFRST | SH7750_SCFCR2_RFRST | |
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| 246 | SH7750_SCFCR2_RTRG_1 | SH7750_SCFCR2_TTRG_4; |
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| 247 | |
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| 248 | if (chn == SH4_SCI) |
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| 249 | SCSPTR1 = int_driven ? 0x0 : SH7750_SCSPTR1_EIO; |
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| 250 | else |
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| 251 | SCSPTR2 = SH7750_SCSPTR2_RTSDT; |
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| 252 | |
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| 253 | if (int_driven) |
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| 254 | { |
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| 255 | rtems_unsigned16 ipr; |
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| 256 | |
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| 257 | if (chn == SH4_SCI) |
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| 258 | { |
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| 259 | ipr = IPRB; |
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| 260 | ipr &= ~SH7750_IPRB_SCI1; |
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| 261 | ipr |= SH4_UART_INTERRUPT_LEVEL << SH7750_IPRB_SCI1_S; |
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| 262 | IPRB = ipr; |
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| 263 | |
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| 264 | rc = rtems_interrupt_catch(sh4uart1_interrupt_transmit, |
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| 265 | SH7750_EVT_TO_NUM(SH7750_EVT_SCI_TXI), |
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| 266 | &uart->old_handler_transmit); |
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| 267 | if (rc != RTEMS_SUCCESSFUL) |
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| 268 | return rc; |
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| 269 | rc = rtems_interrupt_catch(sh4uart1_interrupt_receive, |
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| 270 | SH7750_EVT_TO_NUM(SH7750_EVT_SCI_RXI), |
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| 271 | &uart->old_handler_receive); |
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| 272 | if (rc != RTEMS_SUCCESSFUL) |
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| 273 | return rc; |
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| 274 | } |
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| 275 | else |
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| 276 | { |
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| 277 | ipr = IPRC; |
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| 278 | ipr &= ~SH7750_IPRC_SCIF; |
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| 279 | ipr |= SH4_UART_INTERRUPT_LEVEL << SH7750_IPRC_SCIF_S; |
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| 280 | IPRC = ipr; |
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| 281 | |
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| 282 | rc = rtems_interrupt_catch(sh4uart2_interrupt_transmit, |
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| 283 | SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_TXI), |
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| 284 | &uart->old_handler_transmit); |
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| 285 | if (rc != RTEMS_SUCCESSFUL) |
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| 286 | return rc; |
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| 287 | rc = rtems_interrupt_catch(sh4uart2_interrupt_receive, |
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| 288 | SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_RXI), |
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| 289 | &uart->old_handler_receive); |
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| 290 | if (rc != RTEMS_SUCCESSFUL) |
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| 291 | return rc; |
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| 292 | } |
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| 293 | uart->tx_buf = NULL; |
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| 294 | uart->tx_ptr = uart->tx_buf_len = 0; |
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| 295 | } |
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| 296 | |
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| 297 | sh4uart_set_baudrate(uart, B38400); /* debug defaults (unfortunately, |
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| 298 | it is differ to termios default */ |
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| 299 | |
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| 300 | SCSCR(chn) = SH7750_SCSCR_TE | SH7750_SCSCR_RE | |
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| 301 | (chn == SH4_SCI ? 0x0 : SH7750_SCSCR2_REIE) | |
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| 302 | (int_driven ? (SH7750_SCSCR_RIE | SH7750_SCSCR_TIE) : 0x0); |
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| 303 | |
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| 304 | return RTEMS_SUCCESSFUL; |
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| 305 | } |
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| 306 | |
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| 307 | /* |
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| 308 | * sh4uart_disable -- |
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| 309 | * This function disable the operations on SH-4 UART controller |
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| 310 | * |
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| 311 | * PARAMETERS: |
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| 312 | * uart - pointer to UART channel descriptor structure |
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| 313 | * |
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| 314 | * RETURNS: |
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| 315 | * RTEMS_SUCCESSFUL if UART closed successfuly, or error code in |
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| 316 | * other case |
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| 317 | */ |
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| 318 | rtems_status_code |
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| 319 | sh4uart_disable(sh4uart *uart) |
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| 320 | { |
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| 321 | rtems_status_code rc; |
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| 322 | |
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| 323 | SCSCR(uart->chn) &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE); |
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| 324 | |
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| 325 | if (uart->int_driven) |
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| 326 | { |
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| 327 | rc = rtems_interrupt_catch(uart->old_handler_transmit, |
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| 328 | uart->chn == SH4_SCI ? |
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| 329 | SH7750_EVT_SCI_TXI : SH7750_EVT_SCIF_TXI, |
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| 330 | NULL); |
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| 331 | if (rc != RTEMS_SUCCESSFUL) |
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| 332 | return rc; |
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| 333 | rc = rtems_interrupt_catch(uart->old_handler_receive, |
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| 334 | uart->chn == SH4_SCI ? |
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| 335 | SH7750_EVT_SCI_RXI : SH7750_EVT_SCIF_RXI, |
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| 336 | NULL); |
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| 337 | if (rc != RTEMS_SUCCESSFUL) |
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| 338 | return rc; |
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| 339 | } |
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| 340 | |
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| 341 | return RTEMS_SUCCESSFUL; |
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| 342 | } |
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| 343 | |
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| 344 | /* |
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| 345 | * sh4uart_set_attributes -- |
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| 346 | * This function parse the termios attributes structure and perform |
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| 347 | * the appropriate settings in hardware. |
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| 348 | * |
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| 349 | * PARAMETERS: |
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| 350 | * uart - pointer to the UART descriptor structure |
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| 351 | * t - pointer to termios parameters |
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| 352 | * |
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| 353 | * RETURNS: |
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| 354 | * RTEMS_SUCCESSFUL |
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| 355 | */ |
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| 356 | rtems_status_code |
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| 357 | sh4uart_set_attributes(sh4uart *uart, const struct termios *t) |
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| 358 | { |
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| 359 | int level; |
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| 360 | speed_t baud; |
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| 361 | rtems_unsigned16 smr; |
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| 362 | |
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| 363 | smr = (rtems_unsigned16)(*(rtems_unsigned8 *)SH7750_SCSMR(uart->chn)); |
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| 364 | |
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| 365 | baud = cfgetospeed(t); |
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| 366 | |
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| 367 | /* Set flow control XXX*/ |
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| 368 | if ((t->c_cflag & CRTSCTS) != 0) |
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| 369 | { |
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| 370 | } |
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| 371 | |
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| 372 | /* Set character size -- only 7 or 8 bit */ |
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| 373 | switch (t->c_cflag & CSIZE) |
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| 374 | { |
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| 375 | case CS5: |
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| 376 | case CS6: |
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| 377 | case CS7: smr |= SH7750_SCSMR_CHR_7; break; |
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| 378 | case CS8: smr &= ~SH7750_SCSMR_CHR_7; break; |
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| 379 | } |
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| 380 | |
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| 381 | /* Set number of stop bits */ |
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| 382 | if ((t->c_cflag & CSTOPB) != 0) |
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| 383 | smr |= SH7750_SCSMR_STOP_2; |
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| 384 | else |
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| 385 | smr &= ~SH7750_SCSMR_STOP_2; |
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| 386 | |
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| 387 | /* Set parity mode */ |
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| 388 | if ((t->c_cflag & PARENB) != 0) |
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| 389 | { |
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| 390 | smr |= SH7750_SCSMR_PE; |
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| 391 | if ((t->c_cflag & PARODD) != 0) |
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| 392 | smr |= SH7750_SCSMR_PM_ODD; |
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| 393 | else |
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| 394 | smr &= ~SH7750_SCSMR_PM_ODD; |
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| 395 | } |
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| 396 | else |
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| 397 | smr &= ~SH7750_SCSMR_PE; |
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| 398 | |
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| 399 | rtems_interrupt_disable(level); |
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| 400 | /* wait untill all data is transmitted */ |
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| 401 | rtems_task_wake_after(RTEMS_MILLISECONDS_TO_TICKS(100)); |
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| 402 | /* disable operations */ |
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| 403 | SCSCR(uart->chn) &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE); |
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| 404 | |
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| 405 | sh4uart_set_baudrate(uart, baud); |
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| 406 | SCSMR(uart->chn) = (rtems_unsigned8)smr; |
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| 407 | |
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| 408 | /* enable operations */ |
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| 409 | SCSCR(uart->chn) |= SH7750_SCSCR_TE | SH7750_SCSCR_RE; |
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| 410 | rtems_interrupt_enable(level); |
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| 411 | |
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| 412 | return RTEMS_SUCCESSFUL; |
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| 413 | } |
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| 414 | |
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| 415 | /* |
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| 416 | * sh4uart_handle_error -- |
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| 417 | * Perfoms error (Overrun, Framing & Parity) handling |
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| 418 | * |
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| 419 | * PARAMETERS: |
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| 420 | * uart - pointer to UART descriptor structure |
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| 421 | * |
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| 422 | * RETURNS: |
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| 423 | * nothing |
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| 424 | */ |
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| 425 | void |
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| 426 | sh4uart_handle_error(sh4uart *uart) |
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| 427 | { |
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| 428 | #if 0 |
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| 429 | int status_reg = SCSSR(uart->chn); |
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| 430 | #endif |
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| 431 | |
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| 432 | if(uart->chn == SH4_SCI) |
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| 433 | { |
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| 434 | SCSSR1 &= ~(SH7750_SCSSR1_ORER | SH7750_SCSSR1_FER | SH7750_SCSSR1_PER); |
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| 435 | } |
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| 436 | else |
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| 437 | { |
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| 438 | SCSSR2 &= ~(SH7750_SCSSR2_ER | SH7750_SCSSR2_BRK | SH7750_SCSSR2_FER); |
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| 439 | SCLSR2 &= ~(SH7750_SCLSR2_ORER); |
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| 440 | } |
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| 441 | } |
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| 442 | |
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| 443 | /* |
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| 444 | * sh4uart_poll_read -- |
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| 445 | * This function tried to read character from SH-4 UART and perform |
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| 446 | * error handling. When parity or framing error occured, return |
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| 447 | * value dependent on termios input mode flags: |
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| 448 | * - received character, if IGNPAR == 1 |
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| 449 | * - 0, if IGNPAR == 0 and PARMRK == 0 |
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| 450 | * - 0xff and 0x00 on next poll_read invocation, if IGNPAR == 0 and |
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| 451 | * PARMRK == 1 |
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| 452 | * |
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| 453 | * PARAMETERS: |
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| 454 | * uart - pointer to UART descriptor structure |
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| 455 | * |
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| 456 | * RETURNS: |
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| 457 | * code of received character or -1 if no characters received. |
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| 458 | */ |
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| 459 | int |
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| 460 | sh4uart_poll_read(sh4uart *uart) |
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| 461 | { |
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| 462 | int chn = uart->chn; |
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| 463 | int error_occured = 0; |
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| 464 | int parity_error = 0; |
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| 465 | int break_occured = 0; |
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| 466 | int ch; |
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| 467 | |
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| 468 | if (uart->parerr_mark_flag == 1) |
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| 469 | { |
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| 470 | uart->parerr_mark_flag = 0; |
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| 471 | return 0; |
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| 472 | } |
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| 473 | |
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| 474 | if (chn == SH4_SCI) |
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| 475 | { |
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| 476 | if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER | |
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| 477 | SH7750_SCSSR1_ORER)) != 0) |
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| 478 | { |
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| 479 | error_occured = 1; |
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| 480 | if (SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER)) |
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| 481 | parity_error = 1; |
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| 482 | sh4uart_handle_error(uart); |
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| 483 | } |
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| 484 | if ((SCSSR1 & SH7750_SCSSR1_RDRF) == 0) |
---|
| 485 | return -1; |
---|
| 486 | } |
---|
| 487 | else |
---|
| 488 | { |
---|
| 489 | if ((SCSSR2 & (SH7750_SCSSR2_ER | SH7750_SCSSR2_DR | |
---|
| 490 | SH7750_SCSSR2_BRK)) != 0 || |
---|
| 491 | (SCLSR2 & SH7750_SCLSR2_ORER) != 0) |
---|
| 492 | { |
---|
| 493 | error_occured = 1; |
---|
| 494 | if (SCSSR2 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER)) |
---|
| 495 | parity_error = 1; |
---|
| 496 | if (SCSSR2 & SH7750_SCSSR2_BRK) |
---|
| 497 | break_occured = 1; |
---|
| 498 | sh4uart_handle_error(uart); |
---|
| 499 | } |
---|
| 500 | if ((SCSSR2 & SH7750_SCSSR2_RDF) == 0) |
---|
| 501 | return -1; |
---|
| 502 | } |
---|
| 503 | |
---|
| 504 | if (parity_error && !(uart->c_iflag & IGNPAR)) |
---|
| 505 | { |
---|
| 506 | if (uart->c_iflag & PARMRK) |
---|
| 507 | { |
---|
| 508 | uart->parerr_mark_flag = 1; |
---|
| 509 | return 0xff; |
---|
| 510 | } |
---|
| 511 | else |
---|
| 512 | return 0; |
---|
| 513 | } |
---|
| 514 | |
---|
| 515 | if (break_occured && !(uart->c_iflag & BRKINT)) |
---|
| 516 | { |
---|
| 517 | if (uart->c_iflag & IGNBRK) |
---|
| 518 | return 0; |
---|
| 519 | else |
---|
| 520 | return 0; /* XXX -- SIGINT */ |
---|
| 521 | } |
---|
| 522 | |
---|
| 523 | ch = SCRDR(chn); |
---|
| 524 | if (uart->chn == SH4_SCI) |
---|
| 525 | SCSSR1 &= ~SH7750_SCSSR1_RDRF; |
---|
| 526 | else |
---|
| 527 | SCSSR2 &= ~SH7750_SCSSR2_RDF; |
---|
| 528 | |
---|
| 529 | return ch; |
---|
| 530 | } |
---|
| 531 | |
---|
| 532 | /* |
---|
| 533 | * sh4uart_poll_write -- |
---|
| 534 | * This function transmit buffer byte-by-byte in polling mode. |
---|
| 535 | * |
---|
| 536 | * PARAMETERS: |
---|
| 537 | * uart - pointer to the UART descriptor structure |
---|
| 538 | * buf - pointer to transmit buffer |
---|
| 539 | * len - transmit buffer length |
---|
| 540 | * |
---|
| 541 | * RETURNS: |
---|
| 542 | * 0 |
---|
| 543 | */ |
---|
| 544 | int |
---|
| 545 | sh4uart_poll_write(sh4uart *uart, const char *buf, int len) |
---|
| 546 | { |
---|
| 547 | while (len) |
---|
| 548 | { |
---|
| 549 | if (uart->chn == SH4_SCI) |
---|
| 550 | { |
---|
| 551 | while ((SCSSR1 & SH7750_SCSSR1_TDRE) != 0) |
---|
| 552 | { |
---|
| 553 | SCTDR1 = *buf++; |
---|
| 554 | len--; |
---|
| 555 | SCSSR1 &= ~SH7750_SCSSR1_TDRE; |
---|
| 556 | } |
---|
| 557 | } |
---|
| 558 | else |
---|
| 559 | { |
---|
| 560 | while ((SCSSR2 & SH7750_SCSSR2_TDFE) != 0) |
---|
| 561 | { |
---|
| 562 | int i; |
---|
| 563 | for (i = 0; |
---|
| 564 | i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 & |
---|
| 565 | SH7750_SCFCR2_TTRG); |
---|
| 566 | i++) |
---|
| 567 | { |
---|
| 568 | SCTDR2 = *buf++; |
---|
| 569 | len--; |
---|
| 570 | } |
---|
| 571 | while ((SCSSR2 & SH7750_SCSSR2_TDFE) == 0 || |
---|
| 572 | (SCSSR2 & SH7750_SCSSR2_TEND) == 0); |
---|
| 573 | SCSSR2 &= ~(SH7750_SCSSR1_TDRE | SH7750_SCSSR2_TEND); |
---|
| 574 | } |
---|
| 575 | } |
---|
| 576 | } |
---|
| 577 | return 0; |
---|
| 578 | } |
---|
| 579 | |
---|
| 580 | /********************************** |
---|
| 581 | * Functions to handle interrupts * |
---|
| 582 | **********************************/ |
---|
| 583 | /* sh4uart1_interrupt_receive -- |
---|
| 584 | * UART interrupt handler routine -- SCI |
---|
| 585 | * Receiving data |
---|
| 586 | * |
---|
| 587 | * PARAMETERS: |
---|
| 588 | * vec - interrupt vector number |
---|
| 589 | * |
---|
| 590 | * RETURNS: |
---|
| 591 | * none |
---|
| 592 | */ |
---|
| 593 | static rtems_isr |
---|
| 594 | sh4uart1_interrupt_receive(rtems_vector_number vec) |
---|
| 595 | { |
---|
| 596 | register int bp = 0; |
---|
| 597 | char buf[32]; |
---|
| 598 | |
---|
| 599 | /* Find UART descriptor from vector number */ |
---|
| 600 | sh4uart *uart = &sh4_uarts[0]; |
---|
| 601 | |
---|
| 602 | while (1) |
---|
| 603 | { |
---|
| 604 | if ((bp < sizeof(buf) - 1) && ((SCSSR1 & SH7750_SCSSR1_RDRF) != 0)) |
---|
| 605 | { |
---|
| 606 | /* Receive character and handle frame/parity errors */ |
---|
| 607 | if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER | |
---|
| 608 | SH7750_SCSSR1_ORER)) != 0) |
---|
| 609 | { |
---|
| 610 | if (SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER)) |
---|
| 611 | { |
---|
| 612 | if(!(uart->c_iflag & IGNPAR)) |
---|
| 613 | { |
---|
| 614 | if (uart->c_iflag & PARMRK) |
---|
| 615 | { |
---|
| 616 | buf[bp++] = 0xff; |
---|
| 617 | buf[bp++] = 0x00; |
---|
| 618 | } |
---|
| 619 | else |
---|
| 620 | buf[bp++] = 0x00; |
---|
| 621 | } |
---|
| 622 | else |
---|
| 623 | buf[bp++] = SCRDR1; |
---|
| 624 | } |
---|
| 625 | sh4uart_handle_error(uart); |
---|
| 626 | } |
---|
| 627 | else |
---|
| 628 | buf[bp++] = SCRDR1; |
---|
| 629 | SCSSR1 &= ~SH7750_SCSSR1_RDRF; |
---|
| 630 | } |
---|
| 631 | else |
---|
| 632 | { |
---|
| 633 | if (bp != 0) |
---|
| 634 | rtems_termios_enqueue_raw_characters(uart->tty, buf, bp); |
---|
| 635 | break; |
---|
| 636 | } |
---|
| 637 | } |
---|
| 638 | } |
---|
| 639 | |
---|
| 640 | /* sh4uart2_interrupt_receive -- |
---|
| 641 | * UART interrupt handler routine -- SCIF |
---|
| 642 | * Receiving data |
---|
| 643 | * |
---|
| 644 | * PARAMETERS: |
---|
| 645 | * vec - interrupt vector number |
---|
| 646 | * |
---|
| 647 | * RETURNS: |
---|
| 648 | * none |
---|
| 649 | */ |
---|
| 650 | static rtems_isr |
---|
| 651 | sh4uart2_interrupt_receive(rtems_vector_number vec) |
---|
| 652 | { |
---|
| 653 | register int bp = 0; |
---|
| 654 | char buf[32]; |
---|
| 655 | |
---|
| 656 | /* Find UART descriptor from vector number */ |
---|
| 657 | sh4uart *uart = &sh4_uarts[1]; |
---|
| 658 | |
---|
| 659 | while (1) |
---|
| 660 | { |
---|
| 661 | if ((bp < sizeof(buf) - 1) && ((SCSSR2 & SH7750_SCSSR2_RDF) != 0)) |
---|
| 662 | { |
---|
| 663 | if ((SCSSR2 & (SH7750_SCSSR2_ER | SH7750_SCSSR2_DR | |
---|
| 664 | SH7750_SCSSR2_BRK)) != 0 || |
---|
| 665 | (SH7750_SCLSR2 & SH7750_SCLSR2_ORER) != 0) |
---|
| 666 | { |
---|
| 667 | if (SCSSR2 & SH7750_SCSSR2_ER) |
---|
| 668 | { |
---|
| 669 | if(!(uart->c_iflag & IGNPAR)) |
---|
| 670 | { |
---|
| 671 | if (uart->c_iflag & PARMRK) |
---|
| 672 | { |
---|
| 673 | buf[bp++] = 0xff; |
---|
| 674 | buf[bp++] = 0x00; |
---|
| 675 | } |
---|
| 676 | else |
---|
| 677 | buf[bp++] = 0x00; |
---|
| 678 | } |
---|
| 679 | else |
---|
| 680 | buf[bp++] = SCRDR1; |
---|
| 681 | } |
---|
| 682 | |
---|
| 683 | if (SCSSR2 & SH7750_SCSSR2_BRK) |
---|
| 684 | { |
---|
| 685 | if (uart->c_iflag & IGNBRK) |
---|
| 686 | buf[bp++] = 0x00; |
---|
| 687 | else |
---|
| 688 | buf[bp++] = 0x00; /* XXX -- SIGINT */ |
---|
| 689 | } |
---|
| 690 | |
---|
| 691 | sh4uart_handle_error(uart); |
---|
| 692 | } |
---|
| 693 | else |
---|
| 694 | buf[bp++] = SCRDR1; |
---|
| 695 | SCSSR2 &= ~SH7750_SCSSR2_RDF; |
---|
| 696 | } |
---|
| 697 | else |
---|
| 698 | { |
---|
| 699 | if (bp != 0) |
---|
| 700 | rtems_termios_enqueue_raw_characters(uart->tty, buf, bp); |
---|
| 701 | break; |
---|
| 702 | } |
---|
| 703 | } |
---|
| 704 | } |
---|
| 705 | |
---|
| 706 | |
---|
| 707 | /* sh4uart1_interrupt_transmit -- |
---|
| 708 | * UART interrupt handler routine -- SCI |
---|
| 709 | * It continues transmit data when old part of data is transmitted |
---|
| 710 | * |
---|
| 711 | * PARAMETERS: |
---|
| 712 | * vec - interrupt vector number |
---|
| 713 | * |
---|
| 714 | * RETURNS: |
---|
| 715 | * none |
---|
| 716 | */ |
---|
| 717 | static rtems_isr |
---|
| 718 | sh4uart1_interrupt_transmit(rtems_vector_number vec) |
---|
| 719 | { |
---|
| 720 | /* Find UART descriptor from vector number */ |
---|
| 721 | sh4uart *uart = &sh4_uarts[0]; |
---|
| 722 | |
---|
| 723 | if (uart->tx_buf != NULL && uart->tx_ptr < uart->tx_buf_len) |
---|
| 724 | { |
---|
| 725 | while ((SCSSR1 & SH7750_SCSSR1_TDRE) != 0 && |
---|
| 726 | uart->tx_ptr < uart->tx_buf_len) |
---|
| 727 | { |
---|
| 728 | SCTDR1 = uart->tx_buf[uart->tx_ptr++]; |
---|
| 729 | SCSSR1 &= ~SH7750_SCSSR1_TDRE; |
---|
| 730 | } |
---|
| 731 | } |
---|
| 732 | else |
---|
| 733 | { |
---|
| 734 | register int dequeue = uart->tx_buf_len; |
---|
| 735 | |
---|
| 736 | uart->tx_buf = NULL; |
---|
| 737 | uart->tx_ptr = uart->tx_buf_len = 0; |
---|
| 738 | |
---|
| 739 | /* Disable interrupts while we do not have any data to transmit */ |
---|
| 740 | SCSCR1 &= ~SH7750_SCSCR_TIE; |
---|
| 741 | |
---|
| 742 | rtems_termios_dequeue_characters(uart->tty, dequeue); |
---|
| 743 | } |
---|
| 744 | } |
---|
| 745 | |
---|
| 746 | /* sh4uart2_interrupt_transmit -- |
---|
| 747 | * UART interrupt handler routine -- SCI |
---|
| 748 | * It continues transmit data when old part of data is transmitted |
---|
| 749 | * |
---|
| 750 | * PARAMETERS: |
---|
| 751 | * vec - interrupt vector number |
---|
| 752 | * |
---|
| 753 | * RETURNS: |
---|
| 754 | * none |
---|
| 755 | */ |
---|
| 756 | static rtems_isr |
---|
| 757 | sh4uart2_interrupt_transmit(rtems_vector_number vec) |
---|
| 758 | { |
---|
| 759 | /* Find UART descriptor from vector number */ |
---|
| 760 | sh4uart *uart = &sh4_uarts[1]; |
---|
| 761 | |
---|
| 762 | if (uart->tx_buf != NULL && uart->tx_ptr < uart->tx_buf_len) |
---|
| 763 | { |
---|
| 764 | while ((SCSSR2 & SH7750_SCSSR2_TDFE) != 0) |
---|
| 765 | { |
---|
| 766 | int i; |
---|
| 767 | for (i = 0; |
---|
| 768 | i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 & |
---|
| 769 | SH7750_SCFCR2_TTRG); |
---|
| 770 | i++) |
---|
| 771 | SCTDR2 = uart->tx_buf[uart->tx_ptr++]; |
---|
| 772 | while ((SCSSR1 & SH7750_SCSSR1_TDRE) == 0 || |
---|
| 773 | (SCSSR1 & SH7750_SCSSR1_TEND) == 0); |
---|
| 774 | SCSSR1 &= ~(SH7750_SCSSR1_TDRE | SH7750_SCSSR2_TEND); |
---|
| 775 | } |
---|
| 776 | } |
---|
| 777 | else |
---|
| 778 | { |
---|
| 779 | register int dequeue = uart->tx_buf_len; |
---|
| 780 | |
---|
| 781 | uart->tx_buf = NULL; |
---|
| 782 | uart->tx_ptr = uart->tx_buf_len = 0; |
---|
| 783 | |
---|
| 784 | /* Disable interrupts while we do not have any data to transmit */ |
---|
| 785 | SCSCR2 &= ~SH7750_SCSCR_TIE; |
---|
| 786 | |
---|
| 787 | rtems_termios_dequeue_characters(uart->tty, dequeue); |
---|
| 788 | } |
---|
| 789 | } |
---|
| 790 | |
---|
| 791 | /* sh4uart_interrupt_write -- |
---|
| 792 | * This function initiate transmitting of the buffer in interrupt mode. |
---|
| 793 | * |
---|
| 794 | * PARAMETERS: |
---|
| 795 | * uart - pointer to the UART descriptor structure |
---|
| 796 | * buf - pointer to transmit buffer |
---|
| 797 | * len - transmit buffer length |
---|
| 798 | * |
---|
| 799 | * RETURNS: |
---|
| 800 | * 0 |
---|
| 801 | */ |
---|
| 802 | rtems_status_code |
---|
| 803 | sh4uart_interrupt_write(sh4uart *uart, const char *buf, int len) |
---|
| 804 | { |
---|
| 805 | int level; |
---|
| 806 | |
---|
| 807 | while ((SCSSR1 & SH7750_SCSSR1_TEND) == 0); |
---|
| 808 | |
---|
| 809 | rtems_interrupt_disable(level); |
---|
| 810 | |
---|
| 811 | uart->tx_buf = buf; |
---|
| 812 | uart->tx_buf_len = len; |
---|
| 813 | uart->tx_ptr = 0; |
---|
| 814 | |
---|
| 815 | if (uart->chn == SH4_SCI) |
---|
| 816 | { |
---|
| 817 | SCSCR1 |= SH7750_SCSCR_TIE; |
---|
| 818 | } |
---|
| 819 | else |
---|
| 820 | SCSCR2 |= SH7750_SCSCR_TIE; |
---|
| 821 | |
---|
| 822 | rtems_interrupt_enable(level); |
---|
| 823 | |
---|
| 824 | return RTEMS_SUCCESSFUL; |
---|
| 825 | } |
---|
| 826 | |
---|
| 827 | /* sh4uart_stop_remote_tx -- |
---|
| 828 | * This function stop data flow from remote device. |
---|
| 829 | * |
---|
| 830 | * PARAMETERS: |
---|
| 831 | * uart - pointer to the UART descriptor structure |
---|
| 832 | * |
---|
| 833 | * RETURNS: |
---|
| 834 | * RTEMS_SUCCESSFUL |
---|
| 835 | */ |
---|
| 836 | rtems_status_code |
---|
| 837 | sh4uart_stop_remote_tx(sh4uart *uart) |
---|
| 838 | { |
---|
| 839 | SCSCR(uart->chn) &= ~(SH7750_SCSCR_RIE | SH7750_SCSCR_RE); |
---|
| 840 | return RTEMS_SUCCESSFUL; |
---|
| 841 | } |
---|
| 842 | |
---|
| 843 | /* sh4uart_start_remote_tx -- |
---|
| 844 | * This function resume data flow from remote device. |
---|
| 845 | * |
---|
| 846 | * PARAMETERS: |
---|
| 847 | * uart - pointer to the UART descriptor structure |
---|
| 848 | * |
---|
| 849 | * RETURNS: |
---|
| 850 | * RTEMS_SUCCESSFUL |
---|
| 851 | */ |
---|
| 852 | rtems_status_code |
---|
| 853 | sh4uart_start_remote_tx(sh4uart *uart) |
---|
| 854 | { |
---|
| 855 | SCSCR(uart->chn) |= SH7750_SCSCR_RIE | SH7750_SCSCR_RE; |
---|
| 856 | return RTEMS_SUCCESSFUL; |
---|
| 857 | } |
---|
| 858 | |
---|
| 859 | #ifdef SH4_WITH_IPL |
---|
| 860 | /********************************* |
---|
| 861 | * Functions for SH-IPL gdb stub * |
---|
| 862 | *********************************/ |
---|
| 863 | |
---|
| 864 | /* |
---|
| 865 | * ipl_finish -- |
---|
| 866 | * Says gdb that program finished to get out from it. |
---|
| 867 | */ |
---|
| 868 | extern void ipl_finish(void); |
---|
| 869 | asm( |
---|
| 870 | " .global _ipl_finish\n" |
---|
| 871 | "_ipl_finish:\n" |
---|
| 872 | " mov.l __ipl_finish_value, r0\n" |
---|
| 873 | " trapa #0x3f\n" |
---|
| 874 | " nop\n" |
---|
| 875 | " rts\n" |
---|
| 876 | " nop\n" |
---|
| 877 | " .align 4\n" |
---|
| 878 | "__ipl_finish_value:\n" |
---|
| 879 | " .long 255" |
---|
| 880 | ); |
---|
| 881 | |
---|
| 882 | extern int ipl_serial_input(int poll_count); |
---|
| 883 | asm( |
---|
| 884 | " .global _ipl_serial_input\n" |
---|
| 885 | "_ipl_serial_input:\n" |
---|
| 886 | " mov #1,r0\n" |
---|
| 887 | " trapa #0x3f\n" |
---|
| 888 | " nop\n" |
---|
| 889 | " rts\n" |
---|
| 890 | " nop\n"); |
---|
| 891 | |
---|
| 892 | extern void ipl_serial_output(const char *buf, int len); |
---|
| 893 | asm ( |
---|
| 894 | " .global _ipl_serial_output\n" |
---|
| 895 | "_ipl_serial_output:\n" |
---|
| 896 | " mov #0,r0\n" |
---|
| 897 | " trapa #0x3f\n" |
---|
| 898 | " nop\n" |
---|
| 899 | " rts\n" |
---|
| 900 | " nop\n"); |
---|
| 901 | |
---|
| 902 | /* ipl_console_poll_read -- |
---|
| 903 | * poll read operation for simulator console through ipl mechanism. |
---|
| 904 | * |
---|
| 905 | * PARAMETERS: |
---|
| 906 | * minor - minor device number |
---|
| 907 | * |
---|
| 908 | * RETURNS: |
---|
| 909 | * character code red from UART, or -1 if there is no characters |
---|
| 910 | * available |
---|
| 911 | */ |
---|
| 912 | int |
---|
| 913 | ipl_console_poll_read(int minor) |
---|
| 914 | { |
---|
| 915 | unsigned char buf; |
---|
| 916 | buf = ipl_serial_input(0x100000); |
---|
| 917 | return buf; |
---|
| 918 | } |
---|
| 919 | |
---|
| 920 | /* ipl_console_poll_write -- |
---|
| 921 | * wrapper for polling mode write function |
---|
| 922 | * |
---|
| 923 | * PARAMETERS: |
---|
| 924 | * minor - minor device number |
---|
| 925 | * buf - output buffer |
---|
| 926 | * len - output buffer length |
---|
| 927 | * |
---|
| 928 | * RETURNS: |
---|
| 929 | * result code (0) |
---|
| 930 | */ |
---|
| 931 | int |
---|
| 932 | ipl_console_poll_write(int minor, const char *buf, int len) |
---|
| 933 | { |
---|
| 934 | int c; |
---|
| 935 | while (len > 0) |
---|
| 936 | { |
---|
| 937 | c = (len < 64 ? len : 64); |
---|
| 938 | ipl_serial_output(buf, c); |
---|
| 939 | len -= c; |
---|
| 940 | buf += c; |
---|
| 941 | } |
---|
| 942 | return 0; |
---|
| 943 | } |
---|
| 944 | #endif |
---|