[ba71076] | 1 | /* |
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| 2 | * Generic UART Serial driver for SH-4 processors |
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| 3 | * |
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| 4 | * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russian Fed. |
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| 5 | * Author: Alexandra Kossovsky <sasha@oktet.ru> |
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| 6 | * |
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| 7 | * COPYRIGHT (c) 1989-2000. |
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| 8 | * On-Line Applications Research Corporation (OAR). |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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[c499856] | 12 | * http://www.rtems.org/license/LICENSE. |
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[ba71076] | 13 | * |
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| 14 | */ |
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| 15 | |
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| 16 | #include <rtems.h> |
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| 17 | #include <termios.h> |
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| 18 | #include <rtems/libio.h> |
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[baef9d91] | 19 | #include <bsp.h> |
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| 20 | #include "sh/sh4uart.h" |
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[ba71076] | 21 | |
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| 22 | #ifndef SH4_UART_INTERRUPT_LEVEL |
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| 23 | #define SH4_UART_INTERRUPT_LEVEL 4 |
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| 24 | #endif |
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| 25 | |
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| 26 | /* Forward function declarations */ |
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| 27 | static rtems_isr |
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| 28 | sh4uart1_interrupt_transmit(rtems_vector_number vec); |
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| 29 | static rtems_isr |
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| 30 | sh4uart1_interrupt_receive(rtems_vector_number vec); |
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| 31 | static rtems_isr |
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| 32 | sh4uart2_interrupt_transmit(rtems_vector_number vec); |
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| 33 | static rtems_isr |
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| 34 | sh4uart2_interrupt_receive(rtems_vector_number vec); |
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| 35 | |
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| 36 | /* |
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| 37 | * sh4uart_init -- |
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| 38 | * This function verifies the input parameters and perform initialization |
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| 39 | * of the SH-4 on-chip UART descriptor structure. |
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| 40 | * |
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| 41 | * PARAMETERS: |
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| 42 | * uart - pointer to the UART channel descriptor structure |
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| 43 | * tty - pointer to termios structure |
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| 44 | * chn - channel number (SH4_SCI/SH4_SCIF -- 1/2) |
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| 45 | * int_driven - interrupt-driven (1) or polled (0) I/O mode |
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| 46 | * |
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| 47 | * RETURNS: |
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| 48 | * RTEMS_SUCCESSFUL if all parameters are valid, or error code |
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| 49 | */ |
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| 50 | rtems_status_code |
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| 51 | sh4uart_init(sh4uart *uart, void *tty, int chn, int int_driven) |
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| 52 | { |
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[cd53898] | 53 | if (uart == NULL) |
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| 54 | return RTEMS_INVALID_ADDRESS; |
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[ba71076] | 55 | |
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[cd53898] | 56 | if ((chn != SH4_SCI) && (chn != SH4_SCIF)) |
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| 57 | return RTEMS_INVALID_NUMBER; |
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[ba71076] | 58 | |
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[cd53898] | 59 | uart->chn = chn; |
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| 60 | uart->tty = tty; |
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| 61 | uart->int_driven = int_driven; |
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[ba71076] | 62 | |
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| 63 | #if 0 |
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[cd53898] | 64 | sh4uart_poll_write(uart, "init", 4); |
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[ba71076] | 65 | #endif |
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[cd53898] | 66 | return RTEMS_SUCCESSFUL; |
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[ba71076] | 67 | } |
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| 68 | |
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| 69 | /* |
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| 70 | * sh4uart_get_Pph -- |
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| 71 | * Get current peripheral module clock. |
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[3906b3ea] | 72 | * |
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[ba71076] | 73 | * PARAMETERS: none; |
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[3906b3ea] | 74 | * Cpu clock is get from CPU_CLOCK_RATE_HZ marco |
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[baef9d91] | 75 | * (defined in bspopts.h, included from bsp.h) |
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[ba71076] | 76 | * |
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| 77 | * RETURNS: |
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| 78 | * peripheral module clock in Hz. |
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| 79 | */ |
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[0626dba] | 80 | static uint32_t |
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[ba71076] | 81 | sh4uart_get_Pph(void) |
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| 82 | { |
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[cd53898] | 83 | uint16_t frqcr = *(volatile uint16_t*)SH7750_FRQCR; |
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| 84 | uint32_t Pph = CPU_CLOCK_RATE_HZ; |
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| 85 | |
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| 86 | switch (frqcr & SH7750_FRQCR_IFC) { |
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| 87 | case SH7750_FRQCR_IFCDIV1: break; |
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| 88 | case SH7750_FRQCR_IFCDIV2: Pph *= 2; break; |
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| 89 | case SH7750_FRQCR_IFCDIV3: Pph *= 3; break; |
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| 90 | case SH7750_FRQCR_IFCDIV4: Pph *= 4; break; |
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| 91 | case SH7750_FRQCR_IFCDIV6: Pph *= 6; break; |
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| 92 | case SH7750_FRQCR_IFCDIV8: Pph *= 8; break; |
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| 93 | default: /* unreachable */ |
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| 94 | break; |
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| 95 | } |
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| 96 | |
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| 97 | switch (frqcr & SH7750_FRQCR_PFC) { |
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| 98 | case SH7750_FRQCR_PFCDIV2: Pph /= 2; break; |
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| 99 | case SH7750_FRQCR_PFCDIV3: Pph /= 3; break; |
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| 100 | case SH7750_FRQCR_PFCDIV4: Pph /= 4; break; |
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| 101 | case SH7750_FRQCR_PFCDIV6: Pph /= 6; break; |
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| 102 | case SH7750_FRQCR_PFCDIV8: Pph /= 8; break; |
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| 103 | default: /* unreachable */ |
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| 104 | break; |
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| 105 | } |
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| 106 | |
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| 107 | return Pph; |
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[ba71076] | 108 | } |
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| 109 | |
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| 110 | /* |
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| 111 | * sh4uart_set_baudrate -- |
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| 112 | * Program the UART timer to specified baudrate |
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| 113 | * |
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| 114 | * PARAMETERS: |
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| 115 | * uart - pointer to UART descriptor structure |
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| 116 | * baud - termios baud rate (B50, B9600, etc...) |
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| 117 | * |
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| 118 | * ALGORITHM: |
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| 119 | * see SH7750 Hardware Manual. |
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| 120 | * |
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| 121 | * RETURNS: |
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| 122 | * none |
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| 123 | */ |
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| 124 | static void |
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| 125 | sh4uart_set_baudrate(sh4uart *uart, speed_t baud) |
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| 126 | { |
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[cd53898] | 127 | uint32_t rate; |
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| 128 | int16_t div; |
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| 129 | int n; |
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| 130 | uint32_t Pph = sh4uart_get_Pph(); |
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| 131 | |
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| 132 | switch (baud) { |
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| 133 | case B50: rate = 50; break; |
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| 134 | case B75: rate = 75; break; |
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| 135 | case B110: rate = 110; break; |
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| 136 | case B134: rate = 134; break; |
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| 137 | case B150: rate = 150; break; |
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| 138 | case B200: rate = 200; break; |
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| 139 | case B300: rate = 300; break; |
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| 140 | case B600: rate = 600; break; |
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| 141 | case B1200: rate = 1200; break; |
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| 142 | case B2400: rate = 2400; break; |
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| 143 | case B4800: rate = 4800; break; |
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| 144 | case B9600: rate = 9600; break; |
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| 145 | case B19200: rate = 19200; break; |
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| 146 | case B38400: rate = 38400; break; |
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| 147 | case B57600: rate = 57600; break; |
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[ba71076] | 148 | #ifdef B115200 |
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[cd53898] | 149 | case B115200: rate = 115200; break; |
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[ba71076] | 150 | #endif |
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| 151 | #ifdef B230400 |
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[cd53898] | 152 | case B230400: rate = 230400; break; |
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[ba71076] | 153 | #endif |
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[cd53898] | 154 | default: rate = 9600; break; |
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| 155 | } |
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| 156 | |
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| 157 | for (n = 0; n < 4; n++) { |
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| 158 | div = Pph / (32 * (1 << (2 * n)) * rate) - 1; |
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| 159 | if (div < 0x100) |
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| 160 | break; |
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| 161 | } |
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| 162 | |
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| 163 | /* Set default baudrate if specified baudrate is impossible */ |
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| 164 | if (n >= 4) |
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| 165 | sh4uart_set_baudrate(uart, B9600); |
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| 166 | |
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| 167 | if ( uart->chn == 1 ) { |
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| 168 | volatile uint8_t *smr1 = (volatile uint8_t *)SH7750_SCSMR1; |
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| 169 | *smr1 &= ~SH7750_SCSMR_CKS; |
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| 170 | *smr1 |= n << SH7750_SCSMR_CKS_S; |
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[359e537] | 171 | } else { |
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[cd53898] | 172 | volatile uint16_t *smr2 = (volatile uint16_t *)SH7750_SCSMR2; |
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| 173 | *smr2 &= ~SH7750_SCSMR_CKS; |
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| 174 | *smr2 |= n << SH7750_SCSMR_CKS_S; |
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| 175 | } |
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| 176 | |
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| 177 | SCBRR(uart->chn) = div; |
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| 178 | /* Wait at least 1 bit interwal */ |
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| 179 | rtems_task_wake_after(RTEMS_MILLISECONDS_TO_TICKS(1000 / rate)); |
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[ba71076] | 180 | } |
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| 181 | |
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| 182 | /* |
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| 183 | * sh4uart_reset -- |
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| 184 | * This function perform the hardware initialization of SH-4 |
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| 185 | * on-chip UART controller using parameters |
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| 186 | * filled by the sh4uart_init function. |
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| 187 | * |
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| 188 | * PARAMETERS: |
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| 189 | * uart - pointer to UART channel descriptor structure |
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| 190 | * |
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| 191 | * RETURNS: |
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| 192 | * RTEMS_SUCCESSFUL if channel is initialized successfully, error |
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| 193 | * code in other case |
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| 194 | */ |
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| 195 | rtems_status_code |
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| 196 | sh4uart_reset(sh4uart *uart) |
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| 197 | { |
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[cd53898] | 198 | register int chn; |
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| 199 | register int int_driven; |
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| 200 | rtems_status_code rc; |
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| 201 | uint16_t tmp; |
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| 202 | |
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| 203 | if (uart == NULL) |
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| 204 | return RTEMS_INVALID_ADDRESS; |
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| 205 | |
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| 206 | chn = uart->chn; |
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| 207 | int_driven = uart->int_driven; |
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| 208 | |
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| 209 | if ( chn == 1 ) { |
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| 210 | volatile uint8_t *scr1 = (volatile uint8_t *)SH7750_SCSCR1; |
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| 211 | volatile uint8_t *smr1 = (volatile uint8_t *)SH7750_SCSMR1; |
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| 212 | *scr1 = 0x0; /* Is set properly at the end of this function */ |
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| 213 | *smr1 = 0x0; /* 8-bit, non-parity, 1 stop bit, pf/1 clock */ |
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| 214 | } else { |
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| 215 | volatile uint16_t *scr2 = (volatile uint16_t *)SH7750_SCSCR2; |
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| 216 | volatile uint16_t *smr2 = (volatile uint16_t *)SH7750_SCSMR2; |
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| 217 | *scr2 = 0x0; /* Is set properly at the end of this function */ |
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| 218 | *smr2 = 0x0; /* 8-bit, non-parity, 1 stop bit, pf/1 clock */ |
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| 219 | } |
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| 220 | |
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| 221 | if (chn == SH4_SCIF) |
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| 222 | SCFCR2 = SH7750_SCFCR2_TFRST | SH7750_SCFCR2_RFRST | |
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| 223 | SH7750_SCFCR2_RTRG_1 | SH7750_SCFCR2_TTRG_4; |
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| 224 | |
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| 225 | if (chn == SH4_SCI) |
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| 226 | SCSPTR1 = int_driven ? 0x0 : SH7750_SCSPTR1_EIO; |
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| 227 | else |
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| 228 | SCSPTR2 = SH7750_SCSPTR2_RTSDT; |
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| 229 | |
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| 230 | if (int_driven) { |
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| 231 | uint16_t ipr; |
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| 232 | |
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| 233 | if (chn == SH4_SCI) { |
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| 234 | ipr = IPRB; |
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| 235 | ipr &= ~SH7750_IPRB_SCI1; |
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| 236 | ipr |= SH4_UART_INTERRUPT_LEVEL << SH7750_IPRB_SCI1_S; |
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| 237 | IPRB = ipr; |
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| 238 | |
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| 239 | rc = rtems_interrupt_catch(sh4uart1_interrupt_transmit, |
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| 240 | SH7750_EVT_TO_NUM(SH7750_EVT_SCI_TXI), |
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| 241 | &uart->old_handler_transmit); |
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| 242 | if (rc != RTEMS_SUCCESSFUL) |
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| 243 | return rc; |
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| 244 | |
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| 245 | rc = rtems_interrupt_catch(sh4uart1_interrupt_receive, |
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| 246 | SH7750_EVT_TO_NUM(SH7750_EVT_SCI_RXI), |
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| 247 | &uart->old_handler_receive); |
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| 248 | if (rc != RTEMS_SUCCESSFUL) |
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| 249 | return rc; |
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| 250 | } else { |
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| 251 | ipr = IPRC; |
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| 252 | ipr &= ~SH7750_IPRC_SCIF; |
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| 253 | ipr |= SH4_UART_INTERRUPT_LEVEL << SH7750_IPRC_SCIF_S; |
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| 254 | IPRC = ipr; |
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| 255 | |
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| 256 | rc = rtems_interrupt_catch(sh4uart2_interrupt_transmit, |
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| 257 | SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_TXI), |
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| 258 | &uart->old_handler_transmit); |
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| 259 | if (rc != RTEMS_SUCCESSFUL) |
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| 260 | return rc; |
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| 261 | rc = rtems_interrupt_catch(sh4uart2_interrupt_receive, |
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| 262 | SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_RXI), |
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| 263 | &uart->old_handler_receive); |
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| 264 | if (rc != RTEMS_SUCCESSFUL) |
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| 265 | return rc; |
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[ba71076] | 266 | } |
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[cd53898] | 267 | uart->tx_buf = NULL; |
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| 268 | uart->tx_ptr = uart->tx_buf_len = 0; |
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| 269 | } |
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| 270 | |
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| 271 | sh4uart_set_baudrate(uart, B38400); /* debug defaults (unfortunately, |
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| 272 | it is differ to termios default */ |
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| 273 | |
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| 274 | tmp = SH7750_SCSCR_TE | SH7750_SCSCR_RE | |
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| 275 | (chn == SH4_SCI ? 0x0 : SH7750_SCSCR2_REIE) | |
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| 276 | (int_driven ? (SH7750_SCSCR_RIE | SH7750_SCSCR_TIE) : 0x0); |
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| 277 | |
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| 278 | if ( chn == 1 ) { |
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| 279 | volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1; |
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| 280 | *scr = tmp; |
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| 281 | } else { |
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| 282 | volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2; |
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| 283 | *scr = tmp; |
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| 284 | } |
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| 285 | |
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| 286 | return RTEMS_SUCCESSFUL; |
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[ba71076] | 287 | } |
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| 288 | |
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| 289 | /* |
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| 290 | * sh4uart_disable -- |
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| 291 | * This function disable the operations on SH-4 UART controller |
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| 292 | * |
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| 293 | * PARAMETERS: |
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| 294 | * uart - pointer to UART channel descriptor structure |
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[baef9d91] | 295 | * disable_port - disable receive and transmit on the port |
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[ba71076] | 296 | * |
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| 297 | * RETURNS: |
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| 298 | * RTEMS_SUCCESSFUL if UART closed successfuly, or error code in |
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| 299 | * other case |
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| 300 | */ |
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| 301 | rtems_status_code |
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[baef9d91] | 302 | sh4uart_disable(sh4uart *uart, int disable_port) |
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[ba71076] | 303 | { |
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[cd53898] | 304 | rtems_status_code rc; |
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| 305 | |
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| 306 | if (disable_port) { |
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| 307 | if ( uart->chn == 1 ) { |
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| 308 | volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1; |
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| 309 | *scr &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE); |
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| 310 | } else { |
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| 311 | volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2; |
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| 312 | *scr &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE); |
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[ba71076] | 313 | } |
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[cd53898] | 314 | } |
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| 315 | |
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| 316 | if (uart->int_driven) { |
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| 317 | rc = rtems_interrupt_catch(uart->old_handler_transmit, |
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| 318 | uart->chn == SH4_SCI ? SH7750_EVT_SCI_TXI : SH7750_EVT_SCIF_TXI, |
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| 319 | NULL); |
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| 320 | if (rc != RTEMS_SUCCESSFUL) |
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| 321 | return rc; |
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| 322 | rc = rtems_interrupt_catch(uart->old_handler_receive, |
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| 323 | uart->chn == SH4_SCI ? SH7750_EVT_SCI_RXI : SH7750_EVT_SCIF_RXI, |
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| 324 | NULL); |
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| 325 | if (rc != RTEMS_SUCCESSFUL) |
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| 326 | return rc; |
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| 327 | } |
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| 328 | |
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| 329 | return RTEMS_SUCCESSFUL; |
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[ba71076] | 330 | } |
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| 331 | |
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| 332 | /* |
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| 333 | * sh4uart_set_attributes -- |
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| 334 | * This function parse the termios attributes structure and perform |
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| 335 | * the appropriate settings in hardware. |
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| 336 | * |
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| 337 | * PARAMETERS: |
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| 338 | * uart - pointer to the UART descriptor structure |
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| 339 | * t - pointer to termios parameters |
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| 340 | * |
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| 341 | * RETURNS: |
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| 342 | * RTEMS_SUCCESSFUL |
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| 343 | */ |
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| 344 | rtems_status_code |
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| 345 | sh4uart_set_attributes(sh4uart *uart, const struct termios *t) |
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| 346 | { |
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[cd53898] | 347 | int level; |
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| 348 | speed_t baud; |
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| 349 | uint16_t smr; |
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[3906b3ea] | 350 | |
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[cd53898] | 351 | smr = (uint16_t)(*(uint8_t*)SH7750_SCSMR(uart->chn)); |
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[ba71076] | 352 | |
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[cd53898] | 353 | baud = cfgetospeed(t); |
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[ba71076] | 354 | |
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[cd53898] | 355 | /* Set flow control XXX*/ |
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| 356 | if ((t->c_cflag & CRTSCTS) != 0) { |
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| 357 | } |
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[ba71076] | 358 | |
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[cd53898] | 359 | /* Set character size -- only 7 or 8 bit */ |
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| 360 | switch (t->c_cflag & CSIZE) { |
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| 361 | case CS5: |
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| 362 | case CS6: |
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| 363 | case CS7: smr |= SH7750_SCSMR_CHR_7; break; |
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| 364 | case CS8: smr &= ~SH7750_SCSMR_CHR_7; break; |
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| 365 | } |
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[ba71076] | 366 | |
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| 367 | /* Set number of stop bits */ |
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[cd53898] | 368 | if ((t->c_cflag & CSTOPB) != 0) |
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| 369 | smr |= SH7750_SCSMR_STOP_2; |
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| 370 | else |
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| 371 | smr &= ~SH7750_SCSMR_STOP_2; |
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| 372 | |
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| 373 | /* Set parity mode */ |
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| 374 | if ((t->c_cflag & PARENB) != 0) { |
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| 375 | smr |= SH7750_SCSMR_PE; |
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| 376 | if ((t->c_cflag & PARODD) != 0) |
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| 377 | smr |= SH7750_SCSMR_PM_ODD; |
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[ba71076] | 378 | else |
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[cd53898] | 379 | smr &= ~SH7750_SCSMR_PM_ODD; |
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| 380 | } else |
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| 381 | smr &= ~SH7750_SCSMR_PE; |
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[ba71076] | 382 | |
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[cd53898] | 383 | rtems_interrupt_disable(level); |
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| 384 | /* wait untill all data is transmitted */ |
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| 385 | /* XXX JOEL says this is broken -- interrupts are OFF so NO ticks */ |
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| 386 | rtems_task_wake_after(RTEMS_MILLISECONDS_TO_TICKS(100)); |
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[ba71076] | 387 | |
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[cd53898] | 388 | if ( uart->chn == 1 ) { |
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| 389 | volatile uint8_t *scrP = (volatile uint8_t *)SH7750_SCSCR1; |
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| 390 | volatile uint8_t *smrP = (volatile uint8_t *)SH7750_SCSMR1; |
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| 391 | |
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| 392 | *scrP &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE); /* disable operations */ |
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| 393 | sh4uart_set_baudrate(uart, baud); |
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| 394 | *smrP = (uint8_t)smr; |
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| 395 | *scrP |= SH7750_SCSCR_TE | SH7750_SCSCR_RE; /* enable operations */ |
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| 396 | } else { |
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| 397 | volatile uint16_t *scrP = (volatile uint16_t *)SH7750_SCSCR2; |
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| 398 | volatile uint16_t *smrP = (volatile uint16_t *)SH7750_SCSMR2; |
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| 399 | |
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| 400 | *scrP &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE); /* disable operations */ |
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[ba71076] | 401 | sh4uart_set_baudrate(uart, baud); |
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[cd53898] | 402 | *smrP = (uint8_t)smr; |
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| 403 | *scrP |= SH7750_SCSCR_TE | SH7750_SCSCR_RE; /* enable operations */ |
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| 404 | } |
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[ba71076] | 405 | |
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[cd53898] | 406 | rtems_interrupt_enable(level); |
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[ba71076] | 407 | |
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[cd53898] | 408 | return RTEMS_SUCCESSFUL; |
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[ba71076] | 409 | } |
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| 410 | |
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| 411 | /* |
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| 412 | * sh4uart_handle_error -- |
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| 413 | * Perfoms error (Overrun, Framing & Parity) handling |
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| 414 | * |
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| 415 | * PARAMETERS: |
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| 416 | * uart - pointer to UART descriptor structure |
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| 417 | * |
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| 418 | * RETURNS: |
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| 419 | * nothing |
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| 420 | */ |
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[0626dba] | 421 | static void |
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[ba71076] | 422 | sh4uart_handle_error(sh4uart *uart) |
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| 423 | { |
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[cd53898] | 424 | if (uart->chn == SH4_SCI) { |
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| 425 | volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1; |
---|
| 426 | *scr &= ~(SH7750_SCSSR1_ORER | SH7750_SCSSR1_FER | SH7750_SCSSR1_PER); |
---|
| 427 | } else { |
---|
| 428 | volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2; |
---|
| 429 | *scr &= ~(SH7750_SCSSR2_ER | SH7750_SCSSR2_BRK | SH7750_SCSSR2_FER); |
---|
| 430 | *scr &= ~(SH7750_SCLSR2_ORER); |
---|
| 431 | } |
---|
[ba71076] | 432 | } |
---|
| 433 | |
---|
| 434 | /* |
---|
| 435 | * sh4uart_poll_read -- |
---|
| 436 | * This function tried to read character from SH-4 UART and perform |
---|
| 437 | * error handling. When parity or framing error occured, return |
---|
| 438 | * value dependent on termios input mode flags: |
---|
| 439 | * - received character, if IGNPAR == 1 |
---|
| 440 | * - 0, if IGNPAR == 0 and PARMRK == 0 |
---|
| 441 | * - 0xff and 0x00 on next poll_read invocation, if IGNPAR == 0 and |
---|
| 442 | * PARMRK == 1 |
---|
| 443 | * |
---|
| 444 | * PARAMETERS: |
---|
| 445 | * uart - pointer to UART descriptor structure |
---|
| 446 | * |
---|
| 447 | * RETURNS: |
---|
| 448 | * code of received character or -1 if no characters received. |
---|
| 449 | */ |
---|
| 450 | int |
---|
| 451 | sh4uart_poll_read(sh4uart *uart) |
---|
| 452 | { |
---|
[cd53898] | 453 | int chn = uart->chn; |
---|
| 454 | int parity_error = 0; |
---|
| 455 | int break_occured = 0; |
---|
| 456 | int ch; |
---|
| 457 | |
---|
[3938b437] | 458 | if (uart->parerr_mark_flag == true) { |
---|
| 459 | uart->parerr_mark_flag = false; |
---|
[cd53898] | 460 | return 0; |
---|
| 461 | } |
---|
| 462 | |
---|
| 463 | if (chn == SH4_SCI) { |
---|
| 464 | if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER | |
---|
| 465 | SH7750_SCSSR1_ORER)) != 0) { |
---|
| 466 | if (SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER)) |
---|
| 467 | parity_error = 1; |
---|
| 468 | sh4uart_handle_error(uart); |
---|
[ba71076] | 469 | } |
---|
[cd53898] | 470 | if ((SCSSR1 & SH7750_SCSSR1_RDRF) == 0) |
---|
| 471 | return -1; |
---|
| 472 | } else { |
---|
| 473 | if ((SCSSR2 & (SH7750_SCSSR2_ER | SH7750_SCSSR2_DR | |
---|
| 474 | SH7750_SCSSR2_BRK)) != 0 || |
---|
| 475 | (SCLSR2 & SH7750_SCLSR2_ORER) != 0) { |
---|
| 476 | if (SCSSR2 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER)) |
---|
| 477 | parity_error = 1; |
---|
| 478 | if (SCSSR2 & SH7750_SCSSR2_BRK) |
---|
| 479 | break_occured = 1; |
---|
| 480 | sh4uart_handle_error(uart); |
---|
[ba71076] | 481 | } |
---|
[cd53898] | 482 | if ((SCSSR2 & SH7750_SCSSR2_RDF) == 0) |
---|
| 483 | return -1; |
---|
| 484 | } |
---|
| 485 | |
---|
| 486 | if (parity_error && !(uart->c_iflag & IGNPAR)) { |
---|
| 487 | if (uart->c_iflag & PARMRK) { |
---|
[3938b437] | 488 | uart->parerr_mark_flag = true; |
---|
[cd53898] | 489 | return 0xff; |
---|
| 490 | } else |
---|
| 491 | return 0; |
---|
| 492 | } |
---|
| 493 | |
---|
| 494 | if (break_occured && !(uart->c_iflag & BRKINT)) { |
---|
| 495 | if (uart->c_iflag & IGNBRK) |
---|
| 496 | return 0; |
---|
[ba71076] | 497 | else |
---|
[cd53898] | 498 | return 0; /* XXX -- SIGINT */ |
---|
| 499 | } |
---|
[ba71076] | 500 | |
---|
[cd53898] | 501 | ch = SCRDR(chn); |
---|
[ba71076] | 502 | |
---|
[cd53898] | 503 | if (uart->chn == SH4_SCI) { |
---|
| 504 | volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1; |
---|
| 505 | *scr &= ~SH7750_SCSSR1_RDRF; |
---|
| 506 | } else { |
---|
| 507 | volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2; |
---|
| 508 | *scr &= ~SH7750_SCSSR2_RDF; |
---|
| 509 | } |
---|
[ba71076] | 510 | |
---|
[cd53898] | 511 | return ch; |
---|
[ba71076] | 512 | } |
---|
| 513 | |
---|
| 514 | /* |
---|
| 515 | * sh4uart_poll_write -- |
---|
| 516 | * This function transmit buffer byte-by-byte in polling mode. |
---|
| 517 | * |
---|
| 518 | * PARAMETERS: |
---|
| 519 | * uart - pointer to the UART descriptor structure |
---|
| 520 | * buf - pointer to transmit buffer |
---|
| 521 | * len - transmit buffer length |
---|
| 522 | * |
---|
| 523 | * RETURNS: |
---|
| 524 | * 0 |
---|
| 525 | */ |
---|
| 526 | int |
---|
| 527 | sh4uart_poll_write(sh4uart *uart, const char *buf, int len) |
---|
| 528 | { |
---|
[cd53898] | 529 | volatile uint8_t *ssr1 = (volatile uint8_t *)SH7750_SCSSR1; |
---|
| 530 | volatile uint16_t *ssr2 = (volatile uint16_t *)SH7750_SCSSR2; |
---|
| 531 | |
---|
| 532 | while (len) { |
---|
| 533 | if (uart->chn == SH4_SCI) { |
---|
| 534 | while ((SCSSR1 & SH7750_SCSSR1_TDRE) != 0) { |
---|
| 535 | SCTDR1 = *buf++; |
---|
| 536 | len--; |
---|
| 537 | *ssr1 &= ~SH7750_SCSSR1_TDRE; |
---|
| 538 | } |
---|
| 539 | } else { |
---|
| 540 | while ((SCSSR2 & SH7750_SCSSR2_TDFE) != 0) { |
---|
| 541 | int i; |
---|
| 542 | for (i = 0; |
---|
| 543 | i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 & |
---|
| 544 | SH7750_SCFCR2_TTRG); |
---|
| 545 | i++) { |
---|
| 546 | SCTDR2 = *buf++; |
---|
| 547 | len--; |
---|
[ba71076] | 548 | } |
---|
[cd53898] | 549 | while ((SCSSR2 & SH7750_SCSSR2_TDFE) == 0 || |
---|
| 550 | (SCSSR2 & SH7750_SCSSR2_TEND) == 0); |
---|
[0d01cdd6] | 551 | *ssr2 &= ~(SH7750_SCSSR1_TDRE | SH7750_SCSSR2_TEND); |
---|
[cd53898] | 552 | } |
---|
[ba71076] | 553 | } |
---|
[cd53898] | 554 | } |
---|
| 555 | return 0; |
---|
[ba71076] | 556 | } |
---|
| 557 | |
---|
| 558 | /********************************** |
---|
| 559 | * Functions to handle interrupts * |
---|
| 560 | **********************************/ |
---|
| 561 | /* sh4uart1_interrupt_receive -- |
---|
| 562 | * UART interrupt handler routine -- SCI |
---|
| 563 | * Receiving data |
---|
| 564 | * |
---|
| 565 | * PARAMETERS: |
---|
| 566 | * vec - interrupt vector number |
---|
| 567 | * |
---|
| 568 | * RETURNS: |
---|
| 569 | * none |
---|
| 570 | */ |
---|
| 571 | static rtems_isr |
---|
| 572 | sh4uart1_interrupt_receive(rtems_vector_number vec) |
---|
| 573 | { |
---|
[cd53898] | 574 | register int bp = 0; |
---|
| 575 | char buf[32]; |
---|
| 576 | volatile uint8_t *ssr1 = (volatile uint8_t *)SH7750_SCSSR1; |
---|
| 577 | |
---|
| 578 | |
---|
| 579 | /* Find UART descriptor from vector number */ |
---|
| 580 | sh4uart *uart = &sh4_uarts[0]; |
---|
| 581 | |
---|
| 582 | while (1) { |
---|
| 583 | if ((bp < sizeof(buf) - 1) && ((SCSSR1 & SH7750_SCSSR1_RDRF) != 0)) { |
---|
| 584 | /* Receive character and handle frame/parity errors */ |
---|
| 585 | if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER | |
---|
| 586 | SH7750_SCSSR1_ORER)) != 0) { |
---|
| 587 | if (SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER)) { |
---|
| 588 | if (!(uart->c_iflag & IGNPAR)) { |
---|
| 589 | if (uart->c_iflag & PARMRK) { |
---|
| 590 | buf[bp++] = 0xff; |
---|
| 591 | buf[bp++] = 0x00; |
---|
| 592 | } else |
---|
| 593 | buf[bp++] = 0x00; |
---|
| 594 | } else |
---|
| 595 | buf[bp++] = SCRDR1; |
---|
| 596 | } |
---|
| 597 | sh4uart_handle_error(uart); |
---|
| 598 | } else |
---|
| 599 | buf[bp++] = SCRDR1; |
---|
| 600 | *ssr1 &= ~SH7750_SCSSR1_RDRF; |
---|
| 601 | } else { |
---|
| 602 | if (bp != 0) |
---|
| 603 | rtems_termios_enqueue_raw_characters(uart->tty, buf, bp); |
---|
| 604 | break; |
---|
[ba71076] | 605 | } |
---|
[cd53898] | 606 | } |
---|
[ba71076] | 607 | } |
---|
| 608 | |
---|
| 609 | /* sh4uart2_interrupt_receive -- |
---|
| 610 | * UART interrupt handler routine -- SCIF |
---|
| 611 | * Receiving data |
---|
| 612 | * |
---|
| 613 | * PARAMETERS: |
---|
| 614 | * vec - interrupt vector number |
---|
| 615 | * |
---|
| 616 | * RETURNS: |
---|
| 617 | * none |
---|
| 618 | */ |
---|
| 619 | static rtems_isr |
---|
| 620 | sh4uart2_interrupt_receive(rtems_vector_number vec) |
---|
| 621 | { |
---|
[cd53898] | 622 | register int bp = 0; |
---|
| 623 | char buf[32]; |
---|
| 624 | volatile uint16_t *ssr2 = (volatile uint16_t *)SH7750_SCSSR2; |
---|
| 625 | |
---|
| 626 | |
---|
| 627 | /* Find UART descriptor from vector number */ |
---|
| 628 | sh4uart *uart = &sh4_uarts[1]; |
---|
| 629 | |
---|
| 630 | while (1) { |
---|
| 631 | if ((bp < sizeof(buf) - 1) && ((SCSSR2 & SH7750_SCSSR2_RDF) != 0)) { |
---|
| 632 | if ((SCSSR2 & (SH7750_SCSSR2_ER | SH7750_SCSSR2_DR | |
---|
| 633 | SH7750_SCSSR2_BRK)) != 0 || |
---|
| 634 | (SH7750_SCLSR2 & SH7750_SCLSR2_ORER) != 0) { |
---|
| 635 | if (SCSSR2 & SH7750_SCSSR2_ER) { |
---|
| 636 | if (!(uart->c_iflag & IGNPAR)) { |
---|
| 637 | if (uart->c_iflag & PARMRK) { |
---|
| 638 | buf[bp++] = 0xff; |
---|
| 639 | buf[bp++] = 0x00; |
---|
| 640 | } else |
---|
| 641 | buf[bp++] = 0x00; |
---|
| 642 | } else |
---|
| 643 | buf[bp++] = SCRDR1; |
---|
[ba71076] | 644 | } |
---|
[cd53898] | 645 | |
---|
| 646 | if (SCSSR2 & SH7750_SCSSR2_BRK) { |
---|
| 647 | if (uart->c_iflag & IGNBRK) |
---|
| 648 | buf[bp++] = 0x00; |
---|
| 649 | else |
---|
| 650 | buf[bp++] = 0x00; /* XXX -- SIGINT */ |
---|
[ba71076] | 651 | } |
---|
[cd53898] | 652 | |
---|
| 653 | sh4uart_handle_error(uart); |
---|
| 654 | } else |
---|
| 655 | buf[bp++] = SCRDR1; |
---|
| 656 | *ssr2 &= ~SH7750_SCSSR2_RDF; |
---|
| 657 | } else { |
---|
| 658 | if (bp != 0) |
---|
| 659 | rtems_termios_enqueue_raw_characters(uart->tty, buf, bp); |
---|
| 660 | break; |
---|
[ba71076] | 661 | } |
---|
[cd53898] | 662 | } |
---|
[ba71076] | 663 | } |
---|
| 664 | |
---|
| 665 | |
---|
| 666 | /* sh4uart1_interrupt_transmit -- |
---|
| 667 | * UART interrupt handler routine -- SCI |
---|
| 668 | * It continues transmit data when old part of data is transmitted |
---|
| 669 | * |
---|
| 670 | * PARAMETERS: |
---|
| 671 | * vec - interrupt vector number |
---|
| 672 | * |
---|
| 673 | * RETURNS: |
---|
| 674 | * none |
---|
| 675 | */ |
---|
| 676 | static rtems_isr |
---|
| 677 | sh4uart1_interrupt_transmit(rtems_vector_number vec) |
---|
| 678 | { |
---|
[cd53898] | 679 | volatile uint8_t *scr1 = (volatile uint8_t *)SH7750_SCSCR1; |
---|
| 680 | volatile uint8_t *ssr1 = (volatile uint8_t *)SH7750_SCSSR1; |
---|
| 681 | |
---|
| 682 | /* Find UART descriptor from vector number */ |
---|
| 683 | sh4uart *uart = &sh4_uarts[0]; |
---|
| 684 | |
---|
| 685 | if (uart->tx_buf != NULL && uart->tx_ptr < uart->tx_buf_len) { |
---|
| 686 | while ((SCSSR1 & SH7750_SCSSR1_TDRE) != 0 && |
---|
| 687 | uart->tx_ptr < uart->tx_buf_len) { |
---|
| 688 | SCTDR1 = uart->tx_buf[uart->tx_ptr++]; |
---|
| 689 | *ssr1 &= ~SH7750_SCSSR1_TDRE; |
---|
[ba71076] | 690 | } |
---|
[cd53898] | 691 | } else { |
---|
| 692 | register int dequeue = uart->tx_buf_len; |
---|
[ba71076] | 693 | |
---|
[cd53898] | 694 | uart->tx_buf = NULL; |
---|
| 695 | uart->tx_ptr = uart->tx_buf_len = 0; |
---|
[ba71076] | 696 | |
---|
[cd53898] | 697 | /* Disable interrupts while we do not have any data to transmit */ |
---|
| 698 | *scr1 &= ~SH7750_SCSCR_TIE; |
---|
[ba71076] | 699 | |
---|
[cd53898] | 700 | rtems_termios_dequeue_characters(uart->tty, dequeue); |
---|
| 701 | } |
---|
[ba71076] | 702 | } |
---|
| 703 | |
---|
| 704 | /* sh4uart2_interrupt_transmit -- |
---|
| 705 | * UART interrupt handler routine -- SCI |
---|
| 706 | * It continues transmit data when old part of data is transmitted |
---|
| 707 | * |
---|
| 708 | * PARAMETERS: |
---|
| 709 | * vec - interrupt vector number |
---|
| 710 | * |
---|
| 711 | * RETURNS: |
---|
| 712 | * none |
---|
| 713 | */ |
---|
| 714 | static rtems_isr |
---|
| 715 | sh4uart2_interrupt_transmit(rtems_vector_number vec) |
---|
| 716 | { |
---|
[cd53898] | 717 | volatile uint8_t *ssr1 = (volatile uint8_t *)SH7750_SCSSR1; |
---|
| 718 | volatile uint16_t *scr2 = (volatile uint16_t *)SH7750_SCSCR2; |
---|
| 719 | |
---|
| 720 | /* Find UART descriptor from vector number */ |
---|
| 721 | sh4uart *uart = &sh4_uarts[1]; |
---|
| 722 | |
---|
| 723 | if (uart->tx_buf != NULL && uart->tx_ptr < uart->tx_buf_len) { |
---|
| 724 | while ((SCSSR2 & SH7750_SCSSR2_TDFE) != 0) { |
---|
| 725 | int i; |
---|
| 726 | for (i = 0; |
---|
| 727 | i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 & SH7750_SCFCR2_TTRG); |
---|
| 728 | i++) |
---|
| 729 | SCTDR2 = uart->tx_buf[uart->tx_ptr++]; |
---|
| 730 | while ((SCSSR1 & SH7750_SCSSR1_TDRE) == 0 || |
---|
| 731 | (SCSSR1 & SH7750_SCSSR1_TEND) == 0); |
---|
| 732 | *ssr1 &= ~(SH7750_SCSSR1_TDRE | SH7750_SCSSR2_TEND); |
---|
[ba71076] | 733 | } |
---|
[cd53898] | 734 | } else { |
---|
| 735 | register int dequeue = uart->tx_buf_len; |
---|
[ba71076] | 736 | |
---|
[cd53898] | 737 | uart->tx_buf = NULL; |
---|
| 738 | uart->tx_ptr = uart->tx_buf_len = 0; |
---|
[ba71076] | 739 | |
---|
[cd53898] | 740 | /* Disable interrupts while we do not have any data to transmit */ |
---|
| 741 | *scr2 &= ~SH7750_SCSCR_TIE; |
---|
[ba71076] | 742 | |
---|
[cd53898] | 743 | rtems_termios_dequeue_characters(uart->tty, dequeue); |
---|
| 744 | } |
---|
[ba71076] | 745 | } |
---|
| 746 | |
---|
| 747 | /* sh4uart_interrupt_write -- |
---|
| 748 | * This function initiate transmitting of the buffer in interrupt mode. |
---|
| 749 | * |
---|
| 750 | * PARAMETERS: |
---|
| 751 | * uart - pointer to the UART descriptor structure |
---|
| 752 | * buf - pointer to transmit buffer |
---|
| 753 | * len - transmit buffer length |
---|
| 754 | * |
---|
| 755 | * RETURNS: |
---|
| 756 | * 0 |
---|
| 757 | */ |
---|
| 758 | rtems_status_code |
---|
| 759 | sh4uart_interrupt_write(sh4uart *uart, const char *buf, int len) |
---|
| 760 | { |
---|
[e18db9f] | 761 | if (len > 0) { |
---|
| 762 | volatile uint8_t *scr1 = (volatile uint8_t *)SH7750_SCSCR1; |
---|
| 763 | volatile uint16_t *scr2 = (volatile uint16_t *)SH7750_SCSCR2; |
---|
[3906b3ea] | 764 | |
---|
[e18db9f] | 765 | while ((SCSSR1 & SH7750_SCSSR1_TEND) == 0); |
---|
[ba71076] | 766 | |
---|
[e18db9f] | 767 | uart->tx_buf = buf; |
---|
| 768 | uart->tx_buf_len = len; |
---|
| 769 | uart->tx_ptr = 0; |
---|
[ba71076] | 770 | |
---|
[e18db9f] | 771 | if (uart->chn == SH4_SCI) |
---|
| 772 | *scr1 |= SH7750_SCSCR_TIE; |
---|
| 773 | else |
---|
| 774 | *scr2 |= SH7750_SCSCR_TIE; |
---|
| 775 | } |
---|
[ba71076] | 776 | |
---|
[cd53898] | 777 | return RTEMS_SUCCESSFUL; |
---|
[ba71076] | 778 | } |
---|
| 779 | |
---|
| 780 | /* sh4uart_stop_remote_tx -- |
---|
| 781 | * This function stop data flow from remote device. |
---|
| 782 | * |
---|
| 783 | * PARAMETERS: |
---|
| 784 | * uart - pointer to the UART descriptor structure |
---|
| 785 | * |
---|
| 786 | * RETURNS: |
---|
| 787 | * RTEMS_SUCCESSFUL |
---|
| 788 | */ |
---|
| 789 | rtems_status_code |
---|
| 790 | sh4uart_stop_remote_tx(sh4uart *uart) |
---|
| 791 | { |
---|
[cd53898] | 792 | if ( uart->chn == 1 ) { |
---|
| 793 | volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1; |
---|
| 794 | *scr &= ~(SH7750_SCSCR_RIE | SH7750_SCSCR_RE); |
---|
| 795 | } else { |
---|
| 796 | volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2; |
---|
| 797 | *scr &= ~(SH7750_SCSCR_RIE | SH7750_SCSCR_RE); |
---|
| 798 | } |
---|
| 799 | |
---|
| 800 | return RTEMS_SUCCESSFUL; |
---|
[ba71076] | 801 | } |
---|
| 802 | |
---|
| 803 | /* sh4uart_start_remote_tx -- |
---|
| 804 | * This function resume data flow from remote device. |
---|
| 805 | * |
---|
| 806 | * PARAMETERS: |
---|
| 807 | * uart - pointer to the UART descriptor structure |
---|
| 808 | * |
---|
| 809 | * RETURNS: |
---|
| 810 | * RTEMS_SUCCESSFUL |
---|
| 811 | */ |
---|
| 812 | rtems_status_code |
---|
| 813 | sh4uart_start_remote_tx(sh4uart *uart) |
---|
| 814 | { |
---|
[cd53898] | 815 | if ( uart->chn == 1 ) { |
---|
| 816 | volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1; |
---|
| 817 | *scr |= SH7750_SCSCR_RIE | SH7750_SCSCR_RE; |
---|
| 818 | } else { |
---|
| 819 | volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2; |
---|
| 820 | *scr |= SH7750_SCSCR_RIE | SH7750_SCSCR_RE; |
---|
| 821 | } |
---|
| 822 | |
---|
| 823 | return RTEMS_SUCCESSFUL; |
---|
[ba71076] | 824 | } |
---|
| 825 | |
---|
| 826 | #ifdef SH4_WITH_IPL |
---|
| 827 | /********************************* |
---|
| 828 | * Functions for SH-IPL gdb stub * |
---|
| 829 | *********************************/ |
---|
| 830 | |
---|
| 831 | /* |
---|
| 832 | * ipl_finish -- |
---|
| 833 | * Says gdb that program finished to get out from it. |
---|
| 834 | */ |
---|
| 835 | extern void ipl_finish(void); |
---|
[3d0af835] | 836 | __asm__ ( |
---|
[ba71076] | 837 | " .global _ipl_finish\n" |
---|
| 838 | "_ipl_finish:\n" |
---|
| 839 | " mov.l __ipl_finish_value, r0\n" |
---|
| 840 | " trapa #0x3f\n" |
---|
| 841 | " nop\n" |
---|
| 842 | " rts\n" |
---|
| 843 | " nop\n" |
---|
| 844 | " .align 4\n" |
---|
| 845 | "__ipl_finish_value:\n" |
---|
| 846 | " .long 255" |
---|
| 847 | ); |
---|
| 848 | |
---|
| 849 | extern int ipl_serial_input(int poll_count); |
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[3d0af835] | 850 | __asm__ ( |
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[ba71076] | 851 | " .global _ipl_serial_input\n" |
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| 852 | "_ipl_serial_input:\n" |
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| 853 | " mov #1,r0\n" |
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| 854 | " trapa #0x3f\n" |
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| 855 | " nop\n" |
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| 856 | " rts\n" |
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| 857 | " nop\n"); |
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| 858 | |
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| 859 | extern void ipl_serial_output(const char *buf, int len); |
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[099ea991] | 860 | __asm__ ( |
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[ba71076] | 861 | " .global _ipl_serial_output\n" |
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| 862 | "_ipl_serial_output:\n" |
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| 863 | " mov #0,r0\n" |
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| 864 | " trapa #0x3f\n" |
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| 865 | " nop\n" |
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| 866 | " rts\n" |
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| 867 | " nop\n"); |
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| 868 | |
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| 869 | /* ipl_console_poll_read -- |
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| 870 | * poll read operation for simulator console through ipl mechanism. |
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| 871 | * |
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| 872 | * PARAMETERS: |
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| 873 | * minor - minor device number |
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| 874 | * |
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| 875 | * RETURNS: |
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| 876 | * character code red from UART, or -1 if there is no characters |
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| 877 | * available |
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| 878 | */ |
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| 879 | int |
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| 880 | ipl_console_poll_read(int minor) |
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| 881 | { |
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| 882 | unsigned char buf; |
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| 883 | buf = ipl_serial_input(0x100000); |
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| 884 | return buf; |
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| 885 | } |
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| 886 | |
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| 887 | /* ipl_console_poll_write -- |
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| 888 | * wrapper for polling mode write function |
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| 889 | * |
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| 890 | * PARAMETERS: |
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| 891 | * minor - minor device number |
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| 892 | * buf - output buffer |
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| 893 | * len - output buffer length |
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| 894 | * |
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| 895 | * RETURNS: |
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| 896 | * result code (0) |
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| 897 | */ |
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| 898 | int |
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| 899 | ipl_console_poll_write(int minor, const char *buf, int len) |
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| 900 | { |
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[cd53898] | 901 | int c; |
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| 902 | while (len > 0) { |
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| 903 | c = (len < 64 ? len : 64); |
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| 904 | ipl_serial_output(buf, c); |
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| 905 | len -= c; |
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| 906 | buf += c; |
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| 907 | } |
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| 908 | return 0; |
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[ba71076] | 909 | } |
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| 910 | #endif |
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