[ba71076] | 1 | /* |
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| 2 | * Generic UART Serial driver for SH-4 processors definitions |
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| 3 | * |
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| 4 | * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russian Fed. |
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| 5 | * Author: Alexandra Kossovsky <sasha@oktet.ru> |
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| 6 | * |
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| 7 | * The license and distribution terms for this file may be |
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| 8 | * found in the file LICENSE in this distribution or at |
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| 9 | * |
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| 10 | * http://www.OARcorp.com/rtems/license.html. |
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| 11 | * |
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| 12 | * @(#) $Id$ |
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| 13 | * |
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| 14 | */ |
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| 15 | |
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| 16 | #ifndef __SH4UART_H__ |
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| 17 | #define __SH4UART_H__ |
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| 18 | |
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| 19 | #include "bsp.h" |
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| 20 | #include "rtems/score/sh7750_regs.h" |
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| 21 | |
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| 22 | |
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| 23 | /* |
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| 24 | * Define this to work from gdb stub |
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| 25 | */ |
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| 26 | #define SH4_WITH_IPL |
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| 27 | |
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| 28 | #define SH4_SCI 1 /* Serial Communication Interface - SCI */ |
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| 29 | #define SH4_SCIF 2 /* Serial Communication Interface with FIFO - SCIF */ |
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| 30 | #define TRANSMIT_TRIGGER_VALUE(ttrg) ((ttrg) == SH7750_SCFCR2_RTRG_1 ? 1 : \ |
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| 31 | (ttrg) == SH7750_SCFCR2_RTRG_4 ? 4 : \ |
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| 32 | (ttrg) == SH7750_SCFCR2_RTRG_8 ? 8 : 14) |
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| 33 | |
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| 34 | /* |
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| 35 | * Macros to call UART registers |
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| 36 | */ |
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| 37 | #define SCRDR(n) (*(volatile rtems_unsigned8 *)SH7750_SCRDR(n)) |
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| 38 | #define SCRDR1 SCRDR(1) |
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| 39 | #define SCRDR2 SCRDR(2) |
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| 40 | #define SCTDR(n) (*(volatile rtems_unsigned8 *)SH7750_SCTDR(n)) |
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| 41 | #define SCTDR1 SCTDR(1) |
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| 42 | #define SCTDR2 SCTDR(2) |
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| 43 | #define SCSMR(n) ((n) == 1 ? *(volatile rtems_unsigned8 *)SH7750_SCSMR1 : \ |
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| 44 | *(volatile rtems_unsigned16 *)SH7750_SCSMR2) |
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| 45 | #define SCSMR1 SCSMR(1) |
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| 46 | #define SCSMR2 SCSMR(2) |
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| 47 | #define SCSCR(n) ((n) == 1 ? *(volatile rtems_unsigned8 *)SH7750_SCSCR1 : \ |
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| 48 | *(volatile rtems_unsigned16 *)SH7750_SCSCR2) |
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| 49 | #define SCSCR1 SCSCR(1) |
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| 50 | #define SCSCR2 SCSCR(2) |
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| 51 | #define SCSSR(n) ((n) == 1 ? *(volatile rtems_unsigned8 *)SH7750_SCSSR1 : \ |
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| 52 | *(volatile rtems_unsigned16 *)SH7750_SCSSR2) |
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| 53 | #define SCSSR1 SCSSR(1) |
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| 54 | #define SCSSR2 SCSSR(2) |
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| 55 | #define SCSPTR1 (*(volatile rtems_unsigned8 *)SH7750_SCSPTR1) |
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| 56 | #define SCSPTR2 (*(volatile rtems_unsigned16 *)SH7750_SCSPTR2) |
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| 57 | #define SCBRR(n) (*(volatile rtems_unsigned8 *)SH7750_SCBRR(n)) |
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| 58 | #define SCBRR1 SCBRR(1) |
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| 59 | #define SCBRR2 SCBRR(2) |
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| 60 | #define SCFCR2 (*(volatile rtems_unsigned16 *)SH7750_SCFCR2) |
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| 61 | #define SCFDR2 (*(volatile rtems_unsigned16 *)SH7750_SCFDR2) |
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| 62 | #define SCLSR2 (*(volatile rtems_unsigned16 *)SH7750_SCLSR2) |
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| 63 | |
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| 64 | #define IPRB (*(volatile rtems_unsigned16 *)SH7750_IPRB) |
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| 65 | #define IPRC (*(volatile rtems_unsigned16 *)SH7750_IPRC) |
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| 66 | |
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| 67 | /* |
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| 68 | * The following structure is a descriptor of single UART channel. |
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| 69 | * It contains the initialization information about channel and |
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| 70 | * current operating values |
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| 71 | */ |
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| 72 | typedef struct sh4uart { |
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| 73 | rtems_unsigned8 chn; /* UART channel number */ |
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| 74 | rtems_unsigned8 int_driven; /* UART interrupt vector number, or |
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| 75 | 0 if polled I/O */ |
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| 76 | void *tty; /* termios channel descriptor */ |
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| 77 | |
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| 78 | volatile const char *tx_buf; /* Transmit buffer from termios */ |
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| 79 | volatile rtems_unsigned32 tx_buf_len; /* Transmit buffer length */ |
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| 80 | volatile rtems_unsigned32 tx_ptr; /* Index of next char to transmit*/ |
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| 81 | |
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| 82 | rtems_isr_entry old_handler_transmit; /* Saved interrupt handlers */ |
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| 83 | rtems_isr_entry old_handler_receive; |
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| 84 | |
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| 85 | tcflag_t c_iflag; /* termios input mode flags */ |
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| 86 | rtems_boolean parerr_mark_flag; /* Parity error processing state */ |
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| 87 | } sh4uart; |
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| 88 | |
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| 89 | /* |
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| 90 | * Functions from sh4uart.c |
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| 91 | */ |
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| 92 | |
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| 93 | /* sh4uart_init -- |
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| 94 | * This function verifies the input parameters and perform initialization |
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| 95 | * of the Motorola Coldfire on-chip UART descriptor structure. |
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| 96 | * |
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| 97 | */ |
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| 98 | rtems_status_code |
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| 99 | sh4uart_init(sh4uart *uart, void *tty, int chn, int int_driven); |
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| 100 | |
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| 101 | /* sh4uart_reset -- |
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| 102 | * This function perform the hardware initialization of Motorola |
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| 103 | * Coldfire processor on-chip UART controller using parameters |
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| 104 | * filled by the sh4uart_init function. |
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| 105 | */ |
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| 106 | rtems_status_code |
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| 107 | sh4uart_reset(sh4uart *uart); |
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| 108 | |
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| 109 | /* sh4uart_disable -- |
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| 110 | * This function disable the operations on Motorola Coldfire UART |
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| 111 | * controller |
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| 112 | */ |
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| 113 | rtems_status_code |
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| 114 | sh4uart_disable(sh4uart *uart); |
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| 115 | |
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| 116 | /* sh4uart_set_attributes -- |
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| 117 | * This function parse the termios attributes structure and perform |
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| 118 | * the appropriate settings in hardware. |
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| 119 | */ |
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| 120 | rtems_status_code |
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| 121 | sh4uart_set_attributes(sh4uart *mcf, const struct termios *t); |
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| 122 | |
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| 123 | /* sh4uart_poll_read -- |
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| 124 | * This function tried to read character from MCF UART and perform |
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| 125 | * error handling. |
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| 126 | */ |
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| 127 | int |
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| 128 | sh4uart_poll_read(sh4uart *uart); |
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| 129 | |
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| 130 | #ifdef SH4_WITH_IPL |
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| 131 | /* ipl_console_poll_read -- |
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| 132 | * This function tried to read character from MCF UART over SH-IPL. |
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| 133 | */ |
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| 134 | int |
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| 135 | ipl_console_poll_read(int minor); |
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| 136 | |
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| 137 | /* sh4uart_interrupt_write -- |
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| 138 | * This function initiate transmitting of the buffer in interrupt mode. |
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| 139 | */ |
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| 140 | rtems_status_code |
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| 141 | sh4uart_interrupt_write(sh4uart *uart, const char *buf, int len); |
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| 142 | |
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| 143 | /* sh4uart_poll_write -- |
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| 144 | * This function transmit buffer byte-by-byte in polling mode. |
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| 145 | */ |
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| 146 | int |
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| 147 | sh4uart_poll_write(sh4uart *uart, const char *buf, int len); |
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| 148 | |
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| 149 | /* ipl_console_poll_write -- |
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| 150 | * This function transmit buffer byte-by-byte in polling mode over SH-IPL. |
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| 151 | */ |
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| 152 | int |
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| 153 | ipl_console_poll_write(int minor, const char *buf, int len); |
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| 154 | |
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| 155 | /* |
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| 156 | * ipl_finish -- |
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| 157 | * Says gdb that program finished to get out from it. |
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| 158 | */ |
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| 159 | extern void ipl_finish(void); |
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| 160 | #endif |
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| 161 | |
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| 162 | /* sh4uart_stop_remote_tx -- |
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| 163 | * This function stop data flow from remote device. |
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| 164 | */ |
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| 165 | rtems_status_code |
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| 166 | sh4uart_stop_remote_tx(sh4uart *uart); |
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| 167 | |
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| 168 | /* sh4uart_start_remote_tx -- |
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| 169 | * This function resume data flow from remote device. |
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| 170 | */ |
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| 171 | rtems_status_code |
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| 172 | sh4uart_start_remote_tx(sh4uart *uart); |
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| 173 | |
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| 174 | /* Descriptor structures for two on-chip UART channels */ |
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| 175 | extern sh4uart sh4_uarts[2]; |
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| 176 | |
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| 177 | #endif |
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| 178 | |
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