1 | /* |
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2 | * Bits on SH-4 registers. |
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3 | * See SH-4 Programming manual for more details. |
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4 | * |
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5 | * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia |
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6 | * Author: Alexandra Kossovsky <sasha@oktet.ru> |
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7 | * |
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8 | * The license and distribution terms for this file may be |
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9 | * found in the file LICENSE in this distribution or at |
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10 | * http://www.OARcorp.com/rtems/license.html. |
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11 | * |
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12 | * @(#) $Id$ |
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13 | */ |
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14 | |
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15 | #ifndef __SH4_REGS_H__ |
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16 | #define __SH4_REGS_H__ |
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17 | |
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18 | /* SR -- Status Register */ |
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19 | #define SH4_SR_MD 0x40000000 /* Priveleged mode */ |
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20 | #define SH4_SR_RB 0x20000000 /* General register bank specifier */ |
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21 | #define SH4_SR_BL 0x10000000 /* Exeption/interrupt masking bit */ |
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22 | #define SH4_SR_FD 0x00008000 /* FPU disable bit */ |
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23 | #define SH4_SR_M 0x00000200 /* For signed division: |
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24 | divisor (module) is negative */ |
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25 | #define SH4_SR_Q 0x00000100 /* For signed division: |
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26 | dividend (and quotient) is negative */ |
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27 | #define SH4_SR_IMASK 0x000000f0 /* Interrupt mask level */ |
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28 | #define SH4_SR_IMASK_S 4 |
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29 | #define SH4_SR_S 0x00000002 /* Saturation for MAC instruction: |
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30 | if set, data in MACH/L register |
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31 | is restricted to 48/32 bits |
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32 | for MAC.W/L instructions */ |
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33 | #define SH4_SR_T 0x00000001 /* 1 if last condiyion was true */ |
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34 | #define SH4_SR_RESERV 0x8fff7d0d /* Reserved bits, read/write as 0 */ |
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35 | |
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36 | /* FPSCR -- FPU Starus/Control Register */ |
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37 | #define SH4_FPSCR_FR 0x00200000 /* FPU register bank specifier */ |
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38 | #define SH4_FPSCR_SZ 0x00100000 /* FMOV 64-bit transfer mode */ |
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39 | #define SH4_FPSCR_PR 0x00080000 /* Double-percision floating-point |
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40 | operations flag */ |
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41 | /* SH4_FPSCR_SZ & SH4_FPSCR_PR != 1 */ |
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42 | #define SH4_FPSCR_DN 0x00040000 /* Treat denormalized number as zero */ |
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43 | #define SH4_FPSCR_CAUSE 0x0003f000 /* FPU exeption cause field */ |
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44 | #define SH4_FPSCR_CAUSE_S 12 |
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45 | #define SH4_FPSCR_ENABLE 0x00000f80 /* FPU exeption enable field */ |
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46 | #define SH4_FPSCR_ENABLE_s 7 |
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47 | #define SH4_FPSCR_FLAG 0x0000007d /* FPU exeption flag field */ |
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48 | #define SH4_FPSCR_FLAG_S 2 |
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49 | #define SH4_FPSCR_RM 0x00000001 /* Rounding mode: |
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50 | 1/0 -- round to zero/nearest */ |
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51 | #define SH4_FPSCR_RESERV 0xffd00000 /* Reserved bits, read/write as 0 */ |
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52 | |
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53 | #endif |
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