source: rtems/c/src/lib/libcpu/sh/sh7750/include/sh4_regs.h @ ba71076

4.104.114.84.95
Last change on this file since ba71076 was ba71076, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 12, 2001 at 1:19:08 PM

2001-10-11 Alexandra Kossovsky <sasha@…>

  • clock/Makefile.am, clock/ckinit.c, clock/.cvsignore, Makefile.am, include/Makefile.am, include/iosh7750.h, include/ipl.h, include/ispsh7750.h, include/sh4_regs.h, include/sh4uart.h, include/sh7750_regs.h, include/.cvsignore, sci/Makefile.am, sci/console.c, sci/sh4uart.c, sci/.cvsignore, score/Makefile.am, score/cpu_asm.c, score/ispsh7750.c, score/.cvsignore, timer/Makefile.am, timer/timer.c, timer/.cvsignore, configure.ac, .cvsignore, ChangeLog?: New files. Reviewed and updated to latest automake and autoconf standards by Ralf Corsepius <corsepiu@…>.
  • Property mode set to 100644
File size: 2.4 KB
Line 
1/*
2 * Bits on SH-4 registers.
3 * See SH-4 Programming manual for more details.
4 *
5 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
6 * Author: Alexandra Kossovsky <sasha@oktet.ru>
7 *
8 * The license and distribution terms for this file may be
9 * found in the file LICENSE in this distribution or at
10 *  http://www.OARcorp.com/rtems/license.html.
11 *
12 * @(#) $Id$
13 */
14
15#ifndef __SH4_REGS_H__
16#define __SH4_REGS_H__
17
18/* SR -- Status Register */
19#define SH4_SR_MD          0x40000000 /* Priveleged mode */
20#define SH4_SR_RB          0x20000000 /* General register bank specifier */
21#define SH4_SR_BL          0x10000000 /* Exeption/interrupt masking bit */
22#define SH4_SR_FD          0x00008000 /* FPU disable bit */
23#define SH4_SR_M           0x00000200 /* For signed division:
24                                         divisor (module) is negative */
25#define SH4_SR_Q           0x00000100 /* For signed division:
26                                         dividend (and quotient) is negative */
27#define SH4_SR_IMASK       0x000000f0 /* Interrupt mask level */
28#define SH4_SR_IMASK_S     4
29#define SH4_SR_S           0x00000002 /* Saturation for MAC instruction:
30                                         if set, data in MACH/L register
31                                         is restricted to 48/32 bits
32                                         for MAC.W/L instructions */
33#define SH4_SR_T           0x00000001 /* 1 if last condiyion was true */
34#define SH4_SR_RESERV      0x8fff7d0d /* Reserved bits, read/write as 0 */
35
36/* FPSCR -- FPU Starus/Control Register */
37#define SH4_FPSCR_FR       0x00200000 /* FPU register bank specifier */
38#define SH4_FPSCR_SZ       0x00100000 /* FMOV 64-bit transfer mode */
39#define SH4_FPSCR_PR       0x00080000 /* Double-percision floating-point
40                                         operations flag */
41                                      /* SH4_FPSCR_SZ & SH4_FPSCR_PR != 1 */
42#define SH4_FPSCR_DN       0x00040000 /* Treat denormalized number as zero */
43#define SH4_FPSCR_CAUSE    0x0003f000 /* FPU exeption cause field */
44#define SH4_FPSCR_CAUSE_S  12
45#define SH4_FPSCR_ENABLE   0x00000f80 /* FPU exeption enable field */
46#define SH4_FPSCR_ENABLE_s 7
47#define SH4_FPSCR_FLAG     0x0000007d /* FPU exeption flag field */
48#define SH4_FPSCR_FLAG_S   2
49#define SH4_FPSCR_RM       0x00000001 /* Rounding mode:
50                                         1/0 -- round to zero/nearest */
51#define SH4_FPSCR_RESERV   0xffd00000 /* Reserved bits, read/write as 0 */
52
53#endif
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