[ba71076] | 1 | /* |
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| 2 | * SH-7750 memory-mapped registers |
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| 3 | * This file based on information provided in the following document: |
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| 4 | * "Hitachi SuperH (tm) RISC engine. SH7750 Series (SH7750, SH7750S) |
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| 5 | * Hardware Manual" |
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| 6 | * Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd. |
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| 7 | * |
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| 8 | * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia |
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| 9 | * Author: Alexandra Kossovsky <sasha@oktet.ru> |
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| 10 | * Victor V. Vengerov <vvv@oktet.ru> |
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| 11 | * |
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| 12 | * The license and distribution terms for this file may be |
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| 13 | * found in the file LICENSE in this distribution or at |
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| 14 | * http://www.OARcorp.com/rtems/license.html. |
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| 15 | * |
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| 16 | * @(#) $Id$ |
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| 17 | */ |
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| 18 | |
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| 19 | #ifndef __SH7750_REGS_H__ |
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| 20 | #define __SH7750_REGS_H__ |
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| 21 | |
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| 22 | /* |
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| 23 | * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and |
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| 24 | * in 0x1f000000 - 0x1fffffff (area 7 address) |
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| 25 | */ |
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| 26 | #define SH7750_P4_BASE 0xff000000 /* Accessable only in |
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| 27 | priveleged mode */ |
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| 28 | #define SH7750_A7_BASE 0x1f000000 /* Accessable only using TLB */ |
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| 29 | |
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| 30 | #define SH7750_P4_REG32(ofs) (SH7750_P4_BASE + (ofs)) |
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| 31 | #define SH7750_A7_REG32(ofs) (SH7750_A7_BASE + (ofs)) |
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| 32 | |
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| 33 | /* |
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| 34 | * MMU Registers |
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| 35 | */ |
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| 36 | |
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| 37 | /* Page Table Entry High register - PTEH */ |
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| 38 | #define SH7750_PTEH_REGOFS 0x000000 /* offset */ |
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| 39 | #define SH7750_PTEH SH7750_P4_REG32(SH7750_PTEH_REGOFS) |
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| 40 | #define SH7750_PTEH_A7 SH7750_A7_REG32(SH7750_PTEH_REGOFS) |
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| 41 | #define SH7750_PTEH_VPN 0xfffffd00 /* Virtual page number */ |
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| 42 | #define SH7750_PTEH_VPN_S 10 |
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| 43 | #define SH7750_PTEH_ASID 0x000000ff /* Address space identifier */ |
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| 44 | #define SH7750_PTEH_ASID_S 0 |
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| 45 | |
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| 46 | /* Page Table Entry Low register - PTEL */ |
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| 47 | #define SH7750_PTEL_REGOFS 0x000004 /* offset */ |
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| 48 | #define SH7750_PTEL SH7750_P4_REG32(SH7750_PTEL_REGOFS) |
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| 49 | #define SH7750_PTEL_A7 SH7750_A7_REG32(SH7750_PTEL_REGOFS) |
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| 50 | #define SH7750_PTEL_PPN 0x1ffffc00 /* Physical page number */ |
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| 51 | #define SH7750_PTEL_PPN_S 10 |
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| 52 | #define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */ |
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| 53 | #define SH7750_PTEL_SZ1 0x00000080 /* Page size bit 1 */ |
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| 54 | #define SH7750_PTEL_SZ0 0x00000010 /* Page size bit 0 */ |
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| 55 | #define SH7750_PTEL_SZ_1KB 0x00000000 /* 1-kbyte page */ |
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| 56 | #define SH7750_PTEL_SZ_4KB 0x00000010 /* 4-kbyte page */ |
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| 57 | #define SH7750_PTEL_SZ_64KB 0x00000080 /* 64-kbyte page */ |
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| 58 | #define SH7750_PTEL_SZ_1MB 0x00000090 /* 1-Mbyte page */ |
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| 59 | #define SH7750_PTEL_PR 0x00000060 /* Protection Key Data */ |
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| 60 | #define SH7750_PTEL_PR_ROPO 0x00000000 /* read-only in priv mode */ |
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| 61 | #define SH7750_PTEL_PR_RWPO 0x00000020 /* read-write in priv mode */ |
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| 62 | #define SH7750_PTEL_PR_ROPU 0x00000040 /* read-only in priv or user mode*/ |
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| 63 | #define SH7750_PTEL_PR_RWPU 0x00000060 /* read-write in priv or user mode*/ |
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| 64 | #define SH7750_PTEL_C 0x00000008 /* Cacheability |
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| 65 | (0 - page not cacheable) */ |
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| 66 | #define SH7750_PTEL_D 0x00000004 /* Dirty bit (1 - write has been |
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| 67 | performed to a page) */ |
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| 68 | #define SH7750_PTEL_SH 0x00000002 /* Share Status bit (1 - page are |
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| 69 | shared by processes) */ |
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| 70 | #define SH7750_PTEL_WT 0x00000001 /* Write-through bit, specifies the |
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| 71 | cache write mode: |
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| 72 | 0 - Copy-back mode |
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| 73 | 1 - Write-through mode */ |
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| 74 | |
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| 75 | /* Page Table Entry Assistance register - PTEA */ |
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| 76 | #define SH7750_PTEA_REGOFS 0x000034 /* offset */ |
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| 77 | #define SH7750_PTEA SH7750_P4_REG32(SH7750_PTEA_REGOFS) |
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| 78 | #define SH7750_PTEA_A7 SH7750_A7_REG32(SH7750_PTEA_REGOFS) |
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| 79 | #define SH7750_PTEA_TC 0x00000008 /* Timing Control bit |
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| 80 | 0 - use area 5 wait states |
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| 81 | 1 - use area 6 wait states */ |
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| 82 | #define SH7750_PTEA_SA 0x00000007 /* Space Attribute bits: */ |
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| 83 | #define SH7750_PTEA_SA_UNDEF 0x00000000 /* 0 - undefined */ |
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| 84 | #define SH7750_PTEA_SA_IOVAR 0x00000001 /* 1 - variable-size I/O space */ |
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| 85 | #define SH7750_PTEA_SA_IO8 0x00000002 /* 2 - 8-bit I/O space */ |
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| 86 | #define SH7750_PTEA_SA_IO16 0x00000003 /* 3 - 16-bit I/O space */ |
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| 87 | #define SH7750_PTEA_SA_CMEM8 0x00000004 /* 4 - 8-bit common memory space*/ |
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| 88 | #define SH7750_PTEA_SA_CMEM16 0x00000005 /* 5 - 16-bit common memory space*/ |
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| 89 | #define SH7750_PTEA_SA_AMEM8 0x00000006 /* 6 - 8-bit attr memory space */ |
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| 90 | #define SH7750_PTEA_SA_AMEM16 0x00000007 /* 7 - 16-bit attr memory space */ |
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| 91 | |
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| 92 | |
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| 93 | /* Translation table base register */ |
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| 94 | #define SH7750_TTB_REGOFS 0x000008 /* offset */ |
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| 95 | #define SH7750_TTB SH7750_P4_REG32(SH7750_TTB_REGOFS) |
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| 96 | #define SH7750_TTB_A7 SH7750_A7_REG32(SH7750_TTB_REGOFS) |
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| 97 | |
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| 98 | /* TLB exeption address register - TEA */ |
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| 99 | #define SH7750_TEA_REGOFS 0x00000c /* offset */ |
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| 100 | #define SH7750_TEA SH7750_P4_REG32(SH7750_TEA_REGOFS) |
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| 101 | #define SH7750_TEA_A7 SH7750_A7_REG32(SH7750_TEA_REGOFS) |
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| 102 | |
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| 103 | /* MMU control register - MMUCR */ |
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| 104 | #define SH7750_MMUCR_REGOFS 0x000010 /* offset */ |
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| 105 | #define SH7750_MMUCR SH7750_P4_REG32(SH7750_MMUCR_REGOFS) |
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| 106 | #define SH7750_MMUCR_A7 SH7750_A7_REG32(SH7750_MMUCR_REGOFS) |
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| 107 | #define SH7750_MMUCR_AT 0x00000001 /* Address translation bit */ |
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| 108 | #define SH7750_MMUCR_TI 0x00000004 /* TLB invalidate */ |
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| 109 | #define SH7750_MMUCR_SV 0x00000100 /* Single Virtual Mode bit */ |
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| 110 | #define SH7750_MMUCR_SQMD 0x00000200 /* Store Queue Mode bit */ |
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| 111 | #define SH7750_MMUCR_URC 0x0000FC00 /* UTLB Replace Counter */ |
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| 112 | #define SH7750_MMUCR_URC_S 10 |
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| 113 | #define SH7750_MMUCR_URB 0x00FC0000 /* UTLB Replace Boundary */ |
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| 114 | #define SH7750_MMUCR_URB_S 18 |
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| 115 | #define SH7750_MMUCR_LRUI 0xFC000000 /* Least Recently Used ITLB */ |
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| 116 | #define SH7750_MMUCR_LRUI_S 26 |
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| 117 | |
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| 118 | |
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| 119 | |
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| 120 | |
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| 121 | /* |
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| 122 | * Cache registers |
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| 123 | * IC -- instructions cache |
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| 124 | * OC -- operand cache |
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| 125 | */ |
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| 126 | |
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| 127 | /* Cache Control Register - CCR */ |
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| 128 | #define SH7750_CCR_REGOFS 0x00001c /* offset */ |
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| 129 | #define SH7750_CCR SH7750_P4_REG32(SH7750_CCR_REGOFS) |
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| 130 | #define SH7750_CCR_A7 SH7750_A7_REG32(SH7750_CCR_REGOFS) |
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| 131 | |
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| 132 | #define SH7750_CCR_IIX 0x00008000 /* IC index enable bit */ |
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| 133 | #define SH7750_CCR_ICI 0x00000800 /* IC invalidation bit: |
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| 134 | set it to clear IC */ |
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| 135 | #define SH7750_CCR_ICE 0x00000100 /* IC enable bit */ |
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| 136 | #define SH7750_CCR_OIX 0x00000080 /* OC index enable bit */ |
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| 137 | #define SH7750_CCR_ORA 0x00000020 /* OC RAM enable bit |
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| 138 | if you set OCE = 0, |
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| 139 | you should set ORA = 0 */ |
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| 140 | #define SH7750_CCR_OCI 0x00000008 /* OC invalidation bit */ |
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| 141 | #define SH7750_CCR_CB 0x00000004 /* Copy-back bit for P1 area */ |
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| 142 | #define SH7750_CCR_WT 0x00000002 /* Write-through bit for P0,U0,P3 area */ |
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| 143 | #define SH7750_CCR_OCE 0x00000001 /* OC enable bit */ |
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| 144 | |
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| 145 | /* Queue address control register 0 - QACR0 */ |
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| 146 | #define SH7750_QACR0_REGOFS 0x000038 /* offset */ |
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| 147 | #define SH7750_QACR0 SH7750_P4_REG32(SH7750_QACR0_REGOFS) |
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| 148 | #define SH7750_QACR0_A7 SH7750_A7_REG32(SH7750_QACR0_REGOFS) |
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| 149 | |
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| 150 | /* Queue address control register 1 - QACR1 */ |
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| 151 | #define SH7750_QACR1_REGOFS 0x00003c /* offset */ |
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| 152 | #define SH7750_QACR1 SH7750_P4_REG32(SH7750_QACR1_REGOFS) |
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| 153 | #define SH7750_QACR1_A7 SH7750_A7_REG32(SH7750_QACR1_REGOFS) |
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| 154 | |
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| 155 | |
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| 156 | /* |
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| 157 | * Exeption-related registers |
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| 158 | */ |
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| 159 | |
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| 160 | /* Immediate data for TRAPA instuction - TRA */ |
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| 161 | #define SH7750_TRA_REGOFS 0x000020 /* offset */ |
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| 162 | #define SH7750_TRA SH7750_P4_REG32(SH7750_TRA_REGOFS) |
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| 163 | #define SH7750_TRA_A7 SH7750_A7_REG32(SH7750_TRA_REGOFS) |
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| 164 | |
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| 165 | #define SH7750_TRA_IMM 0x000003fd /* Immediate data operand */ |
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| 166 | #define SH7750_TRA_IMM_S 2 |
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| 167 | |
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| 168 | /* Exeption event register - EXPEVT */ |
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| 169 | #define SH7750_EXPEVT_REGOFS 0x000024 |
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| 170 | #define SH7750_EXPEVT SH7750_P4_REG32(SH7750_EXPEVT_REGOFS) |
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| 171 | #define SH7750_EXPEVT_A7 SH7750_A7_REG32(SH7750_EXPEVT_REGOFS) |
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| 172 | |
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| 173 | #define SH7750_EXPEVT_EX 0x00000fff /* Exeption code */ |
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| 174 | #define SH7750_EXPEVT_EX_S 0 |
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| 175 | |
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| 176 | /* Interrupt event register */ |
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| 177 | #define SH7750_INTEVT_REGOFS 0x000028 |
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| 178 | #define SH7750_INTEVT SH7750_P4_REG32(SH7750_INTEVT_REGOFS) |
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| 179 | #define SH7750_INTEVT_A7 SH7750_A7_REG32(SH7750_INTEVT_REGOFS) |
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| 180 | #define SH7750_INTEVT_EX 0x00000fff /* Exeption code */ |
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| 181 | #define SH7750_INTEVT_EX_S 0 |
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| 182 | |
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| 183 | /* |
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| 184 | * Exception/interrupt codes |
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| 185 | */ |
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| 186 | #define SH7750_EVT_TO_NUM(evt) ((evt) >> 5) |
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| 187 | |
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| 188 | /* Reset exception category */ |
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| 189 | #define SH7750_EVT_POWER_ON_RST 0x000 /* Power-on reset */ |
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| 190 | #define SH7750_EVT_MANUAL_RST 0x020 /* Manual reset */ |
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| 191 | #define SH7750_EVT_TLB_MULT_HIT 0x140 /* TLB multiple-hit exception */ |
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| 192 | |
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| 193 | /* General exception category */ |
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| 194 | #define SH7750_EVT_USER_BREAK 0x1E0 /* User break */ |
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| 195 | #define SH7750_EVT_IADDR_ERR 0x0E0 /* Instruction address error */ |
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| 196 | #define SH7750_EVT_TLB_READ_MISS 0x040 /* ITLB miss exception / |
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| 197 | DTLB miss exception (read) */ |
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| 198 | #define SH7750_EVT_TLB_READ_PROTV 0x0A0 /* ITLB protection violation / |
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| 199 | DTLB protection violation (read)*/ |
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| 200 | #define SH7750_EVT_ILLEGAL_INSTR 0x180 /* General Illegal Instruction |
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| 201 | exception */ |
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| 202 | #define SH7750_EVT_SLOT_ILLEGAL_INSTR 0x1A0 /* Slot Illegal Instruction |
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| 203 | exception */ |
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| 204 | #define SH7750_EVT_FPU_DISABLE 0x800 /* General FPU disable exception*/ |
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| 205 | #define SH7750_EVT_SLOT_FPU_DISABLE 0x820 /* Slot FPU disable exception */ |
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| 206 | #define SH7750_EVT_DATA_READ_ERR 0x0E0 /* Data address error (read) */ |
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| 207 | #define SH7750_EVT_DATA_WRITE_ERR 0x100 /* Data address error (write) */ |
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| 208 | #define SH7750_EVT_DTLB_WRITE_MISS 0x060 /* DTLB miss exception (write) */ |
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| 209 | #define SH7750_EVT_DTLB_WRITE_PROTV 0x0C0 /* DTLB protection violation |
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| 210 | exception (write) */ |
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| 211 | #define SH7750_EVT_FPU_EXCEPTION 0x120 /* FPU exception */ |
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| 212 | #define SH7750_EVT_INITIAL_PGWRITE 0x080 /* Initial Page Write exception */ |
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| 213 | #define SH7750_EVT_TRAPA 0x160 /* Unconditional trap (TRAPA) */ |
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| 214 | |
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| 215 | /* Interrupt exception category */ |
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| 216 | #define SH7750_EVT_NMI 0x1C0 /* Non-maskable interrupt */ |
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| 217 | #define SH7750_EVT_IRQ0 0x200 /* External Interrupt 0 */ |
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| 218 | #define SH7750_EVT_IRQ1 0x220 /* External Interrupt 1 */ |
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| 219 | #define SH7750_EVT_IRQ2 0x240 /* External Interrupt 2 */ |
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| 220 | #define SH7750_EVT_IRQ3 0x260 /* External Interrupt 3 */ |
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| 221 | #define SH7750_EVT_IRQ4 0x280 /* External Interrupt 4 */ |
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| 222 | #define SH7750_EVT_IRQ5 0x2A0 /* External Interrupt 5 */ |
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| 223 | #define SH7750_EVT_IRQ6 0x2C0 /* External Interrupt 6 */ |
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| 224 | #define SH7750_EVT_IRQ7 0x2E0 /* External Interrupt 7 */ |
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| 225 | #define SH7750_EVT_IRQ8 0x300 /* External Interrupt 8 */ |
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| 226 | #define SH7750_EVT_IRQ9 0x320 /* External Interrupt 9 */ |
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| 227 | #define SH7750_EVT_IRQA 0x340 /* External Interrupt A */ |
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| 228 | #define SH7750_EVT_IRQB 0x360 /* External Interrupt B */ |
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| 229 | #define SH7750_EVT_IRQC 0x380 /* External Interrupt C */ |
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| 230 | #define SH7750_EVT_IRQD 0x3A0 /* External Interrupt D */ |
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| 231 | #define SH7750_EVT_IRQE 0x3C0 /* External Interrupt E */ |
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| 232 | |
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| 233 | /* Peripheral Module Interrupts - Timer Unit (TMU) */ |
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| 234 | #define SH7750_EVT_TUNI0 0x400 /* TMU Underflow Interrupt 0 */ |
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| 235 | #define SH7750_EVT_TUNI1 0x420 /* TMU Underflow Interrupt 1 */ |
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| 236 | #define SH7750_EVT_TUNI2 0x440 /* TMU Underflow Interrupt 2 */ |
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| 237 | #define SH7750_EVT_TICPI2 0x460 /* TMU Input Capture Interrupt 2*/ |
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| 238 | |
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| 239 | /* Peripheral Module Interrupts - Real-Time Clock (RTC) */ |
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| 240 | #define SH7750_EVT_RTC_ATI 0x480 /* Alarm Interrupt Request */ |
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| 241 | #define SH7750_EVT_RTC_PRI 0x4A0 /* Periodic Interrupt Request */ |
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| 242 | #define SH7750_EVT_RTC_CUI 0x4C0 /* Carry Interrupt Request */ |
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| 243 | |
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| 244 | /* Peripheral Module Interrupts - Serial Communication Interface (SCI) */ |
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| 245 | #define SH7750_EVT_SCI_ERI 0x4E0 /* Receive Error */ |
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| 246 | #define SH7750_EVT_SCI_RXI 0x500 /* Receive Data Register Full */ |
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| 247 | #define SH7750_EVT_SCI_TXI 0x520 /* Transmit Data Register Empty */ |
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| 248 | #define SH7750_EVT_SCI_TEI 0x540 /* Transmit End */ |
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| 249 | |
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| 250 | /* Peripheral Module Interrupts - Watchdog Timer (WDT) */ |
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| 251 | #define SH7750_EVT_WDT_ITI 0x560 /* Interval Timer Interrupt |
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| 252 | (used when WDT operates in |
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| 253 | interval timer mode) */ |
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| 254 | |
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| 255 | /* Peripheral Module Interrupts - Memory Refresh Unit (REF) */ |
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| 256 | #define SH7750_EVT_REF_RCMI 0x580 /* Compare-match Interrupt */ |
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| 257 | #define SH7750_EVT_REF_ROVI 0x5A0 /* Refresh Counter Overflow |
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| 258 | interrupt */ |
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| 259 | |
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| 260 | /* Peripheral Module Interrupts - Hitachi User Debug Interface (H-UDI) */ |
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| 261 | #define SH7750_EVT_HUDI 0x600 /* UDI interrupt */ |
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| 262 | |
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| 263 | /* Peripheral Module Interrupts - General-Purpose I/O (GPIO) */ |
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| 264 | #define SH7750_EVT_GPIO 0x620 /* GPIO Interrupt */ |
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| 265 | |
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| 266 | /* Peripheral Module Interrupts - DMA Controller (DMAC) */ |
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| 267 | #define SH7750_EVT_DMAC_DMTE0 0x640 /* DMAC 0 Transfer End Interrupt*/ |
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| 268 | #define SH7750_EVT_DMAC_DMTE1 0x660 /* DMAC 1 Transfer End Interrupt*/ |
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| 269 | #define SH7750_EVT_DMAC_DMTE2 0x680 /* DMAC 2 Transfer End Interrupt*/ |
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| 270 | #define SH7750_EVT_DMAC_DMTE3 0x6A0 /* DMAC 3 Transfer End Interrupt*/ |
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| 271 | #define SH7750_EVT_DMAC_DMAE 0x6C0 /* DMAC Address Error Interrupt */ |
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| 272 | |
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| 273 | /* Peripheral Module Interrupts - Serial Communication Interface with FIFO */ |
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| 274 | /* (SCIF) */ |
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| 275 | #define SH7750_EVT_SCIF_ERI 0x700 /* Receive Error */ |
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| 276 | #define SH7750_EVT_SCIF_RXI 0x720 /* Receive FIFO Data Full or |
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| 277 | Receive Data ready interrupt */ |
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| 278 | #define SH7750_EVT_SCIF_BRI 0x740 /* Break or overrun error */ |
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| 279 | #define SH7750_EVT_SCIF_TXI 0x760 /* Transmit FIFO Data Empty */ |
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| 280 | |
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| 281 | /* |
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| 282 | * Power Management |
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| 283 | */ |
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| 284 | #define SH7750_STBCR_REGOFS 0xC00004 /* offset */ |
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| 285 | #define SH7750_STBCR SH7750_P4_REG32(SH7750_STBCR_REGOFS) |
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| 286 | #define SH7750_STBCR_A7 SH7750_A7_REG32(SH7750_STBCR_REGOFS) |
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| 287 | |
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| 288 | #define SH7750_STBCR_STBY 0x80 /* Specifies a transition to standby mode: |
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| 289 | 0 - Transition to SLEEP mode on SLEEP |
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| 290 | 1 - Transition to STANDBY mode on SLEEP*/ |
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| 291 | #define SH7750_STBCR_PHZ 0x40 /* State of peripheral module pins in |
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| 292 | standby mode: |
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| 293 | 0 - normal state |
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| 294 | 1 - high-impendance state */ |
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| 295 | |
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| 296 | #define SH7750_STBCR_PPU 0x20 /* Peripheral module pins pull-up controls*/ |
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| 297 | #define SH7750_STBCR_MSTP4 0x10 /* Stopping the clock supply to DMAC */ |
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| 298 | #define SH7750_STBCR_DMAC_STP SH7750_STBCR_MSTP4 |
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| 299 | #define SH7750_STBCR_MSTP3 0x08 /* Stopping the clock supply to SCIF */ |
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| 300 | #define SH7750_STBCR_SCIF_STP SH7750_STBCR_MSTP3 |
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| 301 | #define SH7750_STBCR_MSTP2 0x04 /* Stopping the clock supply to TMU */ |
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| 302 | #define SH7750_STBCR_TMU_STP SH7750_STBCR_MSTP2 |
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| 303 | #define SH7750_STBCR_MSTP1 0x02 /* Stopping the clock supply to RTC */ |
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| 304 | #define SH7750_STBCR_RTC_STP SH7750_STBCR_MSTP1 |
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| 305 | #define SH7750_STBCR_MSPT0 0x01 /* Stopping the clock supply to SCI */ |
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| 306 | #define SH7750_STBCR_SCI_STP SH7750_STBCR_MSTP0 |
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| 307 | |
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| 308 | #define SH7750_STBCR_STBY 0x80 |
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| 309 | |
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| 310 | |
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| 311 | #define SH7750_STBCR2_REGOFS 0xC00010 /* offset */ |
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| 312 | #define SH7750_STBCR2 SH7750_P4_REG32(SH7750_STBCR2_REGOFS) |
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| 313 | #define SH7750_STBCR2_A7 SH7750_A7_REG32(SH7750_STBCR2_REGOFS) |
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| 314 | |
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| 315 | #define SH7750_STBCR2_DSLP 0x80 /* Specifies transition to deep sleep mode: |
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| 316 | 0 - transition to sleep or standby mode |
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| 317 | as it is specified in STBY bit |
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| 318 | 1 - transition to deep sleep mode on |
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| 319 | execution of SLEEP instruction */ |
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| 320 | #define SH7750_STBCR2_MSTP6 0x02 /* Stopping the clock supply to Store Queue |
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| 321 | in the cache controller */ |
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| 322 | #define SH7750_STBCR2_SQ_STP SH7750_STBCR2_MSTP6 |
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| 323 | #define SH7750_STBCR2_MSTP5 0x01 /* Stopping the clock supply to the User |
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| 324 | Break Controller (UBC) */ |
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| 325 | #define SH7750_STBCR2_UBC_STP SH7750_STBCR2_MSTP5 |
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| 326 | |
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| 327 | /* |
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| 328 | * Clock Pulse Generator (CPG) |
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| 329 | */ |
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| 330 | #define SH7750_FRQCR_REGOFS 0xC00000 /* offset */ |
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| 331 | #define SH7750_FRQCR SH7750_P4_REG32(SH7750_FRQCR_REGOFS) |
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| 332 | #define SH7750_FRQCR_A7 SH7750_A7_REG32(SH7750_FRQCR_REGOFS) |
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| 333 | |
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| 334 | #define SH7750_FRQCR_CKOEN 0x0800 /* Clock Output Enable |
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| 335 | 0 - CKIO pin goes to HiZ/pullup |
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| 336 | 1 - Clock is output from CKIO */ |
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| 337 | #define SH7750_FRQCR_PLL1EN 0x0400 /* PLL circuit 1 enable */ |
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| 338 | #define SH7750_FRQCR_PLL2EN 0x0200 /* PLL circuit 2 enable */ |
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| 339 | |
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| 340 | #define SH7750_FRQCR_IFC 0x01C0 /* CPU clock frequency division ratio: */ |
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| 341 | #define SH7750_FRQCR_IFCDIV1 0x0000 /* 0 - * 1 */ |
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| 342 | #define SH7750_FRQCR_IFCDIV2 0x0040 /* 1 - * 1/2 */ |
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| 343 | #define SH7750_FRQCR_IFCDIV3 0x0080 /* 2 - * 1/3 */ |
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| 344 | #define SH7750_FRQCR_IFCDIV4 0x00C0 /* 3 - * 1/4 */ |
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| 345 | #define SH7750_FRQCR_IFCDIV6 0x0100 /* 4 - * 1/6 */ |
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| 346 | #define SH7750_FRQCR_IFCDIV8 0x0140 /* 5 - * 1/8 */ |
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| 347 | |
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| 348 | #define SH7750_FRQCR_BFC 0x0038 /* Bus clock frequency division ratio: */ |
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| 349 | #define SH7750_FRQCR_BFCDIV1 0x0000 /* 0 - * 1 */ |
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| 350 | #define SH7750_FRQCR_BFCDIV2 0x0008 /* 1 - * 1/2 */ |
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| 351 | #define SH7750_FRQCR_BFCDIV3 0x0010 /* 2 - * 1/3 */ |
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| 352 | #define SH7750_FRQCR_BFCDIV4 0x0018 /* 3 - * 1/4 */ |
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| 353 | #define SH7750_FRQCR_BFCDIV6 0x0020 /* 4 - * 1/6 */ |
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| 354 | #define SH7750_FRQCR_BFCDIV8 0x0028 /* 5 - * 1/8 */ |
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| 355 | |
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| 356 | #define SH7750_FRQCR_PFC 0x0007 /* Peripheral module clock frequency |
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| 357 | division ratio: */ |
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| 358 | #define SH7750_FRQCR_PFCDIV2 0x0000 /* 0 - * 1/2 */ |
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| 359 | #define SH7750_FRQCR_PFCDIV3 0x0001 /* 1 - * 1/3 */ |
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| 360 | #define SH7750_FRQCR_PFCDIV4 0x0002 /* 2 - * 1/4 */ |
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| 361 | #define SH7750_FRQCR_PFCDIV6 0x0003 /* 3 - * 1/6 */ |
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| 362 | #define SH7750_FRQCR_PFCDIV8 0x0004 /* 4 - * 1/8 */ |
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| 363 | |
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| 364 | /* |
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| 365 | * Watchdog Timer (WDT) |
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| 366 | */ |
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| 367 | |
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| 368 | /* Watchdog Timer Counter register - WTCNT */ |
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| 369 | #define SH7750_WTCNT_REGOFS 0xC00008 /* offset */ |
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| 370 | #define SH7750_WTCNT SH7750_P4_REG32(SH7750_WTCNT_REGOFS) |
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| 371 | #define SH7750_WTCNT_A7 SH7750_A7_REG32(SH7750_WTCNT_REGOFS) |
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| 372 | #define SH7750_WTCNT_KEY 0x5A00 /* When WTCNT byte register written, |
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| 373 | you have to set the upper byte to |
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| 374 | 0x5A */ |
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| 375 | |
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| 376 | /* Watchdog Timer Control/Status register - WTCSR */ |
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| 377 | #define SH7750_WTCSR_REGOFS 0xC0000C /* offset */ |
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| 378 | #define SH7750_WTCSR SH7750_P4_REG32(SH7750_WTCSR_REGOFS) |
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| 379 | #define SH7750_WTCSR_A7 SH7750_A7_REG32(SH7750_WTCSR_REGOFS) |
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| 380 | #define SH7750_WTCSR_KEY 0xA500 /* When WTCSR byte register written, |
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| 381 | you have to set the upper byte to |
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| 382 | 0xA5 */ |
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| 383 | #define SH7750_WTCSR_TME 0x80 /* Timer enable (1-upcount start) */ |
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| 384 | #define SH7750_WTCSR_MODE 0x40 /* Timer Mode Select: */ |
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| 385 | #define SH7750_WTCSR_MODE_WT 0x40 /* Watchdog Timer Mode */ |
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| 386 | #define SH7750_WTCSR_MODE_IT 0x00 /* Interval Timer Mode */ |
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| 387 | #define SH7750_WTCSR_RSTS 0x20 /* Reset Select: */ |
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| 388 | #define SH7750_WTCSR_RST_MAN 0x20 /* Manual Reset */ |
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| 389 | #define SH7750_WTCSR_RST_PWR 0x00 /* Power-on Reset */ |
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| 390 | #define SH7750_WTCSR_WOVF 0x10 /* Watchdog Timer Overflow Flag */ |
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| 391 | #define SH7750_WTCSR_IOVF 0x08 /* Interval Timer Overflow Flag */ |
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| 392 | #define SH7750_WTCSR_CKS 0x07 /* Clock Select: */ |
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| 393 | #define SH7750_WTCSR_CKS_DIV32 0x00 /* 1/32 of frequency divider 2 input */ |
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| 394 | #define SH7750_WTCSR_CKS_DIV64 0x01 /* 1/64 */ |
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| 395 | #define SH7750_WTCSR_CKS_DIV128 0x02 /* 1/128 */ |
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| 396 | #define SH7750_WTCSR_CKS_DIV256 0x03 /* 1/256 */ |
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| 397 | #define SH7750_WTCSR_CKS_DIV512 0x04 /* 1/512 */ |
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| 398 | #define SH7750_WTCSR_CKS_DIV1024 0x05 /* 1/1024 */ |
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| 399 | #define SH7750_WTCSR_CKS_DIV2048 0x06 /* 1/2048 */ |
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| 400 | #define SH7750_WTCSR_CKS_DIV4096 0x07 /* 1/4096 */ |
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| 401 | |
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| 402 | /* |
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| 403 | * Real-Time Clock (RTC) |
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| 404 | */ |
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| 405 | /* 64-Hz Counter Register (byte, read-only) - R64CNT */ |
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| 406 | #define SH7750_R64CNT_REGOFS 0xC80000 /* offset */ |
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| 407 | #define SH7750_R64CNT SH7750_P4_REG32(SH7750_R64CNT_REGOFS) |
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| 408 | #define SH7750_R64CNT_A7 SH7750_A7_REG32(SH7750_R64CNT_REGOFS) |
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| 409 | |
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| 410 | /* Second Counter Register (byte, BCD-coded) - RSECCNT */ |
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| 411 | #define SH7750_RSECCNT_REGOFS 0xC80004 /* offset */ |
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| 412 | #define SH7750_RSECCNT SH7750_P4_REG32(SH7750_RSECCNT_REGOFS) |
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| 413 | #define SH7750_RSECCNT_A7 SH7750_A7_REG32(SH7750_RSECCNT_REGOFS) |
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| 414 | |
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| 415 | /* Minute Counter Register (byte, BCD-coded) - RMINCNT */ |
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| 416 | #define SH7750_RMINCNT_REGOFS 0xC80008 /* offset */ |
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| 417 | #define SH7750_RMINCNT SH7750_P4_REG32(SH7750_RMINCNT_REGOFS) |
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| 418 | #define SH7750_RMINCNT_A7 SH7750_A7_REG32(SH7750_RMINCNT_REGOFS) |
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| 419 | |
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| 420 | /* Hour Counter Register (byte, BCD-coded) - RHRCNT */ |
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| 421 | #define SH7750_RHRCNT_REGOFS 0xC8000C /* offset */ |
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| 422 | #define SH7750_RHRCNT SH7750_P4_REG32(SH7750_RHRCNT_REGOFS) |
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| 423 | #define SH7750_RHRCNT_A7 SH7750_A7_REG32(SH7750_RHRCNT_REGOFS) |
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| 424 | |
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| 425 | /* Day-of-Week Counter Register (byte) - RWKCNT */ |
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| 426 | #define SH7750_RWKCNT_REGOFS 0xC80010 /* offset */ |
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| 427 | #define SH7750_RWKCNT SH7750_P4_REG32(SH7750_RWKCNT_REGOFS) |
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| 428 | #define SH7750_RWKCNT_A7 SH7750_A7_REG32(SH7750_RWKCNT_REGOFS) |
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| 429 | |
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| 430 | #define SH7750_RWKCNT_SUN 0 /* Sunday */ |
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| 431 | #define SH7750_RWKCNT_MON 1 /* Monday */ |
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| 432 | #define SH7750_RWKCNT_TUE 2 /* Tuesday */ |
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| 433 | #define SH7750_RWKCNT_WED 3 /* Wednesday */ |
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| 434 | #define SH7750_RWKCNT_THU 4 /* Thursday */ |
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| 435 | #define SH7750_RWKCNT_FRI 5 /* Friday */ |
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| 436 | #define SH7750_RWKCNT_SAT 6 /* Saturday */ |
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| 437 | |
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| 438 | /* Day Counter Register (byte, BCD-coded) - RDAYCNT */ |
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| 439 | #define SH7750_RDAYCNT_REGOFS 0xC80014 /* offset */ |
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| 440 | #define SH7750_RDAYCNT SH7750_P4_REG32(SH7750_RDAYCNT_REGOFS) |
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| 441 | #define SH7750_RDAYCNT_A7 SH7750_A7_REG32(SH7750_RDAYCNT_REGOFS) |
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| 442 | |
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| 443 | /* Month Counter Register (byte, BCD-coded) - RMONCNT */ |
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| 444 | #define SH7750_RMONCNT_REGOFS 0xC80018 /* offset */ |
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| 445 | #define SH7750_RMONCNT SH7750_P4_REG32(SH7750_RMONCNT_REGOFS) |
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| 446 | #define SH7750_RMONCNT_A7 SH7750_A7_REG32(SH7750_RMONCNT_REGOFS) |
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| 447 | |
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| 448 | /* Year Counter Register (half, BCD-coded) - RYRCNT */ |
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| 449 | #define SH7750_RYRCNT_REGOFS 0xC8001C /* offset */ |
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| 450 | #define SH7750_RYRCNT SH7750_P4_REG32(SH7750_RYRCNT_REGOFS) |
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| 451 | #define SH7750_RYRCNT_A7 SH7750_A7_REG32(SH7750_RYRCNT_REGOFS) |
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| 452 | |
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| 453 | /* Second Alarm Register (byte, BCD-coded) - RSECAR */ |
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| 454 | #define SH7750_RSECAR_REGOFS 0xC80020 /* offset */ |
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| 455 | #define SH7750_RSECAR SH7750_P4_REG32(SH7750_RSECAR_REGOFS) |
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| 456 | #define SH7750_RSECAR_A7 SH7750_A7_REG32(SH7750_RSECAR_REGOFS) |
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| 457 | #define SH7750_RSECAR_ENB 0x80 /* Second Alarm Enable */ |
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| 458 | |
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| 459 | /* Minute Alarm Register (byte, BCD-coded) - RMINAR */ |
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| 460 | #define SH7750_RMINAR_REGOFS 0xC80024 /* offset */ |
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| 461 | #define SH7750_RMINAR SH7750_P4_REG32(SH7750_RMINAR_REGOFS) |
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| 462 | #define SH7750_RMINAR_A7 SH7750_A7_REG32(SH7750_RMINAR_REGOFS) |
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| 463 | #define SH7750_RMINAR_ENB 0x80 /* Minute Alarm Enable */ |
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| 464 | |
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| 465 | /* Hour Alarm Register (byte, BCD-coded) - RHRAR */ |
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| 466 | #define SH7750_RHRAR_REGOFS 0xC80028 /* offset */ |
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| 467 | #define SH7750_RHRAR SH7750_P4_REG32(SH7750_RHRAR_REGOFS) |
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| 468 | #define SH7750_RHRAR_A7 SH7750_A7_REG32(SH7750_RHRAR_REGOFS) |
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| 469 | #define SH7750_RHRAR_ENB 0x80 /* Hour Alarm Enable */ |
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| 470 | |
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| 471 | /* Day-of-Week Alarm Register (byte) - RWKAR */ |
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| 472 | #define SH7750_RWKAR_REGOFS 0xC8002C /* offset */ |
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| 473 | #define SH7750_RWKAR SH7750_P4_REG32(SH7750_RWKAR_REGOFS) |
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| 474 | #define SH7750_RWKAR_A7 SH7750_A7_REG32(SH7750_RWKAR_REGOFS) |
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| 475 | #define SH7750_RWKAR_ENB 0x80 /* Day-of-week Alarm Enable */ |
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| 476 | |
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| 477 | #define SH7750_RWKAR_SUN 0 /* Sunday */ |
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| 478 | #define SH7750_RWKAR_MON 1 /* Monday */ |
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| 479 | #define SH7750_RWKAR_TUE 2 /* Tuesday */ |
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| 480 | #define SH7750_RWKAR_WED 3 /* Wednesday */ |
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| 481 | #define SH7750_RWKAR_THU 4 /* Thursday */ |
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| 482 | #define SH7750_RWKAR_FRI 5 /* Friday */ |
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| 483 | #define SH7750_RWKAR_SAT 6 /* Saturday */ |
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| 484 | |
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| 485 | /* Day Alarm Register (byte, BCD-coded) - RDAYAR */ |
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| 486 | #define SH7750_RDAYAR_REGOFS 0xC80030 /* offset */ |
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| 487 | #define SH7750_RDAYAR SH7750_P4_REG32(SH7750_RDAYAR_REGOFS) |
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| 488 | #define SH7750_RDAYAR_A7 SH7750_A7_REG32(SH7750_RDAYAR_REGOFS) |
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| 489 | #define SH7750_RDAYAR_ENB 0x80 /* Day Alarm Enable */ |
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| 490 | |
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| 491 | /* Month Counter Register (byte, BCD-coded) - RMONAR */ |
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| 492 | #define SH7750_RMONAR_REGOFS 0xC80034 /* offset */ |
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| 493 | #define SH7750_RMONAR SH7750_P4_REG32(SH7750_RMONAR_REGOFS) |
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| 494 | #define SH7750_RMONAR_A7 SH7750_A7_REG32(SH7750_RMONAR_REGOFS) |
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| 495 | #define SH7750_RMONAR_ENB 0x80 /* Month Alarm Enable */ |
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| 496 | |
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| 497 | /* RTC Control Register 1 (byte) - RCR1 */ |
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| 498 | #define SH7750_RCR1_REGOFS 0xC80038 /* offset */ |
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| 499 | #define SH7750_RCR1 SH7750_P4_REG32(SH7750_RCR1_REGOFS) |
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| 500 | #define SH7750_RCR1_A7 SH7750_A7_REG32(SH7750_RCR1_REGOFS) |
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| 501 | #define SH7750_RCR1_CF 0x80 /* Carry Flag */ |
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| 502 | #define SH7750_RCR1_CIE 0x10 /* Carry Interrupt Enable */ |
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| 503 | #define SH7750_RCR1_AIE 0x08 /* Alarm Interrupt Enable */ |
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| 504 | #define SH7750_RCR1_AF 0x01 /* Alarm Flag */ |
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| 505 | |
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| 506 | /* RTC Control Register 2 (byte) - RCR2 */ |
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| 507 | #define SH7750_RCR2_REGOFS 0xC8003C /* offset */ |
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| 508 | #define SH7750_RCR2 SH7750_P4_REG32(SH7750_RCR2_REGOFS) |
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| 509 | #define SH7750_RCR2_A7 SH7750_A7_REG32(SH7750_RCR2_REGOFS) |
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| 510 | #define SH7750_RCR2_PEF 0x80 /* Periodic Interrupt Flag */ |
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| 511 | #define SH7750_RCR2_PES 0x70 /* Periodic Interrupt Enable: */ |
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| 512 | #define SH7750_RCR2_PES_DIS 0x00 /* Periodic Interrupt Disabled */ |
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| 513 | #define SH7750_RCR2_PES_DIV256 0x10 /* Generated at 1/256 sec interval */ |
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| 514 | #define SH7750_RCR2_PES_DIV64 0x20 /* Generated at 1/64 sec interval */ |
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| 515 | #define SH7750_RCR2_PES_DIV16 0x30 /* Generated at 1/16 sec interval */ |
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| 516 | #define SH7750_RCR2_PES_DIV4 0x40 /* Generated at 1/4 sec interval */ |
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| 517 | #define SH7750_RCR2_PES_DIV2 0x50 /* Generated at 1/2 sec interval */ |
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| 518 | #define SH7750_RCR2_PES_x1 0x60 /* Generated at 1 sec interval */ |
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| 519 | #define SH7750_RCR2_PES_x2 0x70 /* Generated at 2 sec interval */ |
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| 520 | #define SH7750_RCR2_RTCEN 0x08 /* RTC Crystal Oscillator is Operated */ |
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| 521 | #define SH7750_RCR2_ADJ 0x04 /* 30-Second Adjastment */ |
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| 522 | #define SH7750_RCR2_RESET 0x02 /* Frequency divider circuits are reset*/ |
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| 523 | #define SH7750_RCR2_START 0x01 /* 0 - sec, min, hr, day-of-week, month, |
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| 524 | year counters are stopped |
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| 525 | 1 - sec, min, hr, day-of-week, month, |
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| 526 | year counters operate normally */ |
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| 527 | |
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| 528 | |
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| 529 | /* |
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| 530 | * Timer Unit (TMU) |
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| 531 | */ |
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| 532 | /* Timer Output Control Register (byte) - TOCR */ |
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| 533 | #define SH7750_TOCR_REGOFS 0xD80000 /* offset */ |
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| 534 | #define SH7750_TOCR SH7750_P4_REG32(SH7750_TOCR_REGOFS) |
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| 535 | #define SH7750_TOCR_A7 SH7750_A7_REG32(SH7750_TOCR_REGOFS) |
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| 536 | #define SH7750_TOCR_TCOE 0x01 /* Timer Clock Pin Control: |
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| 537 | 0 - TCLK is used as external clock |
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| 538 | input or input capture control |
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| 539 | 1 - TCLK is used as on-chip RTC |
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| 540 | output clock pin */ |
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| 541 | |
---|
| 542 | /* Timer Start Register (byte) - TSTR */ |
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| 543 | #define SH7750_TSTR_REGOFS 0xD80004 /* offset */ |
---|
| 544 | #define SH7750_TSTR SH7750_P4_REG32(SH7750_TSTR_REGOFS) |
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| 545 | #define SH7750_TSTR_A7 SH7750_A7_REG32(SH7750_TSTR_REGOFS) |
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| 546 | #define SH7750_TSTR_STR2 0x04 /* TCNT2 performs count operations */ |
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| 547 | #define SH7750_TSTR_STR1 0x02 /* TCNT1 performs count operations */ |
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| 548 | #define SH7750_TSTR_STR0 0x01 /* TCNT0 performs count operations */ |
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| 549 | #define SH7750_TSTR_STR(n) (1 << (n)) |
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| 550 | |
---|
| 551 | /* Timer Constant Register - TCOR0, TCOR1, TCOR2 */ |
---|
| 552 | #define SH7750_TCOR_REGOFS(n) (0xD80008 + ((n)*12)) /* offset */ |
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| 553 | #define SH7750_TCOR(n) SH7750_P4_REG32(SH7750_TCOR_REGOFS(n)) |
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| 554 | #define SH7750_TCOR_A7(n) SH7750_A7_REG32(SH7750_TCOR_REGOFS(n)) |
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| 555 | #define SH7750_TCOR0 SH7750_TCOR(0) |
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| 556 | #define SH7750_TCOR1 SH7750_TCOR(1) |
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| 557 | #define SH7750_TCOR2 SH7750_TCOR(2) |
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| 558 | #define SH7750_TCOR0_A7 SH7750_TCOR_A7(0) |
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| 559 | #define SH7750_TCOR1_A7 SH7750_TCOR_A7(1) |
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| 560 | #define SH7750_TCOR2_A7 SH7750_TCOR_A7(2) |
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| 561 | |
---|
| 562 | /* Timer Counter Register - TCNT0, TCNT1, TCNT2 */ |
---|
| 563 | #define SH7750_TCNT_REGOFS(n) (0xD8000C + ((n)*12)) /* offset */ |
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| 564 | #define SH7750_TCNT(n) SH7750_P4_REG32(SH7750_TCNT_REGOFS(n)) |
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| 565 | #define SH7750_TCNT_A7(n) SH7750_A7_REG32(SH7750_TCNT_REGOFS(n)) |
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| 566 | #define SH7750_TCNT0 SH7750_TCNT(0) |
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| 567 | #define SH7750_TCNT1 SH7750_TCNT(1) |
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| 568 | #define SH7750_TCNT2 SH7750_TCNT(2) |
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| 569 | #define SH7750_TCNT0_A7 SH7750_TCNT_A7(0) |
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| 570 | #define SH7750_TCNT1_A7 SH7750_TCNT_A7(1) |
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| 571 | #define SH7750_TCNT2_A7 SH7750_TCNT_A7(2) |
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| 572 | |
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| 573 | /* Timer Control Register (half) - TCR0, TCR1, TCR2 */ |
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| 574 | #define SH7750_TCR_REGOFS(n) (0xD80010 + ((n)*12)) /* offset */ |
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| 575 | #define SH7750_TCR(n) SH7750_P4_REG32(SH7750_TCR_REGOFS(n)) |
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| 576 | #define SH7750_TCR_A7(n) SH7750_A7_REG32(SH7750_TCR_REGOFS(n)) |
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| 577 | #define SH7750_TCR0 SH7750_TCR(0) |
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| 578 | #define SH7750_TCR1 SH7750_TCR(1) |
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| 579 | #define SH7750_TCR2 SH7750_TCR(2) |
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| 580 | #define SH7750_TCR0_A7 SH7750_TCR_A7(0) |
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| 581 | #define SH7750_TCR1_A7 SH7750_TCR_A7(1) |
---|
| 582 | #define SH7750_TCR2_A7 SH7750_TCR_A7(2) |
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| 583 | |
---|
| 584 | #define SH7750_TCR2_ICPF 0x200 /* Input Capture Interrupt Flag |
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| 585 | (1 - input capture has occured) */ |
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| 586 | #define SH7750_TCR_UNF 0x100 /* Underflow flag */ |
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| 587 | #define SH7750_TCR2_ICPE 0x0C0 /* Input Capture Control: */ |
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| 588 | #define SH7750_TCR2_ICPE_DIS 0x000 /* Input Capture function is not used*/ |
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| 589 | #define SH7750_TCR2_ICPE_NOINT 0x080 /* Input Capture function is used, but |
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| 590 | input capture interrupt is not |
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| 591 | enabled */ |
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| 592 | #define SH7750_TCR2_ICPE_INT 0x0C0 /* Input Capture function is used, |
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| 593 | input capture interrupt enabled */ |
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| 594 | #define SH7750_TCR_UNIE 0x020 /* Underflow Interrupt Control |
---|
| 595 | (1 - underflow interrupt enabled) */ |
---|
| 596 | #define SH7750_TCR_CKEG 0x018 /* Clock Edge selection: */ |
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| 597 | #define SH7750_TCR_CKEG_RAISE 0x000 /* Count/capture on rising edge */ |
---|
| 598 | #define SH7750_TCR_CKEG_FALL 0x008 /* Count/capture on falling edge */ |
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| 599 | #define SH7750_TCR_CKEG_BOTH 0x018 /* Count/capture on both rising and |
---|
| 600 | falling edges */ |
---|
| 601 | #define SH7750_TCR_TPSC 0x007 /* Timer prescaler */ |
---|
| 602 | #define SH7750_TCR_TPSC_DIV4 0x000 /* Counts on peripheral clock/4 */ |
---|
| 603 | #define SH7750_TCR_TPSC_DIV16 0x001 /* Counts on peripheral clock/16 */ |
---|
| 604 | #define SH7750_TCR_TPSC_DIV64 0x002 /* Counts on peripheral clock/64 */ |
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| 605 | #define SH7750_TCR_TPSC_DIV256 0x003 /* Counts on peripheral clock/256 */ |
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| 606 | #define SH7750_TCR_TPSC_DIV1024 0x004 /* Counts on peripheral clock/1024 */ |
---|
| 607 | #define SH7750_TCR_TPSC_RTC 0x006 /* Counts on on-chip RTC output clk*/ |
---|
| 608 | #define SH7750_TCR_TPSC_EXT 0x007 /* Counts on external clock */ |
---|
| 609 | |
---|
| 610 | /* Input Capture Register (read-only) - TCPR2 */ |
---|
| 611 | #define SH7750_TCPR2_REGOFS 0xD8002C /* offset */ |
---|
| 612 | #define SH7750_TCPR2 SH7750_P4_REG32(SH7750_TCPR2_REGOFS) |
---|
| 613 | #define SH7750_TCPR2_A7 SH7750_A7_REG32(SH7750_TCPR2_REGOFS) |
---|
| 614 | |
---|
| 615 | /* |
---|
| 616 | * Bus State Controller - BSC |
---|
| 617 | */ |
---|
| 618 | /* Bus Control Register 1 - BCR1 */ |
---|
| 619 | #define SH7750_BCR1_REGOFS 0x800000 /* offset */ |
---|
| 620 | #define SH7750_BCR1 SH7750_P4_REG32(SH7750_BCR1_REGOFS) |
---|
| 621 | #define SH7750_BCR1_A7 SH7750_A7_REG32(SH7750_BCR1_REGOFS) |
---|
| 622 | #define SH7750_BCR1_ENDIAN 0x80000000 /* Endianness (1 - little endian) */ |
---|
| 623 | #define SH7750_BCR1_MASTER 0x40000000 /* Master/Slave mode (1-master) */ |
---|
| 624 | #define SH7750_BCR1_A0MPX 0x20000000 /* Area 0 Memory Type (0-SRAM,1-MPX)*/ |
---|
| 625 | #define SH7750_BCR1_IPUP 0x02000000 /* Input Pin Pull-up Control: |
---|
| 626 | 0 - pull-up resistor is on for |
---|
| 627 | control input pins |
---|
| 628 | 1 - pull-up resistor is off */ |
---|
| 629 | #define SH7750_BCR1_OPUP 0x01000000 /* Output Pin Pull-up Control: |
---|
| 630 | 0 - pull-up resistor is on for |
---|
| 631 | control output pins |
---|
| 632 | 1 - pull-up resistor is off */ |
---|
| 633 | #define SH7750_BCR1_A1MBC 0x00200000 /* Area 1 SRAM Byte Control Mode: |
---|
| 634 | 0 - Area 1 SRAM is set to |
---|
| 635 | normal mode |
---|
| 636 | 1 - Area 1 SRAM is set to byte |
---|
| 637 | control mode */ |
---|
| 638 | #define SH7750_BCR1_A4MBC 0x00100000 /* Area 4 SRAM Byte Control Mode: |
---|
| 639 | 0 - Area 4 SRAM is set to |
---|
| 640 | normal mode |
---|
| 641 | 1 - Area 4 SRAM is set to byte |
---|
| 642 | control mode */ |
---|
| 643 | #define SH7750_BCR1_BREQEN 0x00080000 /* BREQ Enable: |
---|
| 644 | 0 - External requests are not |
---|
| 645 | accepted |
---|
| 646 | 1 - External requests are |
---|
| 647 | accepted */ |
---|
| 648 | #define SH7750_BCR1_PSHR 0x00040000 /* Partial Sharing Bit: |
---|
| 649 | 0 - Master Mode |
---|
| 650 | 1 - Partial-sharing Mode */ |
---|
| 651 | #define SH7750_BCR1_MEMMPX 0x00020000 /* Area 1 to 6 MPX Interface: |
---|
| 652 | 0 - SRAM/burst ROM interface |
---|
| 653 | 1 - MPX interface */ |
---|
| 654 | #define SH7750_BCR1_HIZMEM 0x00008000 /* High Impendance Control. Specifies |
---|
| 655 | the state of A[25:0], BS\, CSn\, |
---|
| 656 | RD/WR\, CE2A\, CE2B\ in standby |
---|
| 657 | mode and when bus is released: |
---|
| 658 | 0 - signals go to High-Z mode |
---|
| 659 | 1 - signals driven */ |
---|
| 660 | #define SH7750_BCR1_HIZCNT 0x00004000 /* High Impendance Control. Specifies |
---|
| 661 | the state of the RAS\, RAS2\, WEn\, |
---|
| 662 | CASn\, DQMn, RD\, CASS\, FRAME\, |
---|
| 663 | RD2\ signals in standby mode and |
---|
| 664 | when bus is released: |
---|
| 665 | 0 - signals go to High-Z mode |
---|
| 666 | 1 - signals driven */ |
---|
| 667 | #define SH7750_BCR1_A0BST 0x00003800 /* Area 0 Burst ROM Control */ |
---|
| 668 | #define SH7750_BCR1_A0BST_SRAM 0x0000 /* Area 0 accessed as SRAM i/f */ |
---|
| 669 | #define SH7750_BCR1_A0BST_ROM4 0x0800 /* Area 0 accessed as burst ROM |
---|
| 670 | interface, 4 cosequtive access*/ |
---|
| 671 | #define SH7750_BCR1_A0BST_ROM8 0x1000 /* Area 0 accessed as burst ROM |
---|
| 672 | interface, 8 cosequtive access*/ |
---|
| 673 | #define SH7750_BCR1_A0BST_ROM16 0x1800 /* Area 0 accessed as burst ROM |
---|
| 674 | interface, 16 cosequtive access*/ |
---|
| 675 | #define SH7750_BCR1_A0BST_ROM32 0x2000 /* Area 0 accessed as burst ROM |
---|
| 676 | interface, 32 cosequtive access*/ |
---|
| 677 | |
---|
| 678 | #define SH7750_BCR1_A5BST 0x00000700 /* Area 5 Burst ROM Control */ |
---|
| 679 | #define SH7750_BCR1_A5BST_SRAM 0x0000 /* Area 5 accessed as SRAM i/f */ |
---|
| 680 | #define SH7750_BCR1_A5BST_ROM4 0x0100 /* Area 5 accessed as burst ROM |
---|
| 681 | interface, 4 cosequtive access*/ |
---|
| 682 | #define SH7750_BCR1_A5BST_ROM8 0x0200 /* Area 5 accessed as burst ROM |
---|
| 683 | interface, 8 cosequtive access*/ |
---|
| 684 | #define SH7750_BCR1_A5BST_ROM16 0x0300 /* Area 5 accessed as burst ROM |
---|
| 685 | interface, 16 cosequtive access*/ |
---|
| 686 | #define SH7750_BCR1_A5BST_ROM32 0x0400 /* Area 5 accessed as burst ROM |
---|
| 687 | interface, 32 cosequtive access*/ |
---|
| 688 | |
---|
| 689 | #define SH7750_BCR1_A6BST 0x000000E0 /* Area 6 Burst ROM Control */ |
---|
| 690 | #define SH7750_BCR1_A6BST_SRAM 0x0000 /* Area 6 accessed as SRAM i/f */ |
---|
| 691 | #define SH7750_BCR1_A6BST_ROM4 0x0020 /* Area 6 accessed as burst ROM |
---|
| 692 | interface, 4 cosequtive access*/ |
---|
| 693 | #define SH7750_BCR1_A6BST_ROM8 0x0040 /* Area 6 accessed as burst ROM |
---|
| 694 | interface, 8 cosequtive access*/ |
---|
| 695 | #define SH7750_BCR1_A6BST_ROM16 0x0060 /* Area 6 accessed as burst ROM |
---|
| 696 | interface, 16 cosequtive access*/ |
---|
| 697 | #define SH7750_BCR1_A6BST_ROM32 0x0080 /* Area 6 accessed as burst ROM |
---|
| 698 | interface, 32 cosequtive access*/ |
---|
| 699 | |
---|
| 700 | #define SH7750_BCR1_DRAMTP 0x001C /* Area 2 and 3 Memory Type */ |
---|
| 701 | #define SH7750_BCR1_DRAMTP_2SRAM_3SRAM 0x0000 /* Area 2 and 3 are SRAM or MPX |
---|
| 702 | interface. */ |
---|
| 703 | #define SH7750_BCR1_DRAMTP_2SRAM_3SDRAM 0x0008 /* Area 2 - SRAM/MPX, Area 3 - |
---|
| 704 | synchronous DRAM */ |
---|
| 705 | #define SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM 0x000C /* Area 2 and 3 are synchronous |
---|
| 706 | DRAM interface */ |
---|
| 707 | #define SH7750_BCR1_DRAMTP_2SRAM_3DRAM 0x0010 /* Area 2 - SRAM/MPX, Area 3 - |
---|
| 708 | DRAM interface */ |
---|
| 709 | #define SH7750_BCR1_DRAMTP_2DRAM_3DRAM 0x0014 /* Area 2 and 3 are DRAM |
---|
| 710 | interface */ |
---|
| 711 | |
---|
| 712 | #define SH7750_BCR1_A56PCM 0x00000001 /* Area 5 and 6 Bus Type: |
---|
| 713 | 0 - SRAM interface |
---|
| 714 | 1 - PCMCIA interface */ |
---|
| 715 | |
---|
| 716 | /* Bus Control Register 2 (half) - BCR2 */ |
---|
| 717 | #define SH7750_BCR2_REGOFS 0x800004 /* offset */ |
---|
| 718 | #define SH7750_BCR2 SH7750_P4_REG32(SH7750_BCR2_REGOFS) |
---|
| 719 | #define SH7750_BCR2_A7 SH7750_A7_REG32(SH7750_BCR2_REGOFS) |
---|
| 720 | |
---|
| 721 | #define SH7750_BCR2_A0SZ 0xC000 /* Area 0 Bus Width */ |
---|
| 722 | #define SH7750_BCR2_A0SZ_S 14 |
---|
| 723 | #define SH7750_BCR2_A6SZ 0x3000 /* Area 6 Bus Width */ |
---|
| 724 | #define SH7750_BCR2_A6SZ_S 12 |
---|
| 725 | #define SH7750_BCR2_A5SZ 0x0C00 /* Area 5 Bus Width */ |
---|
| 726 | #define SH7750_BCR2_A5SZ_S 10 |
---|
| 727 | #define SH7750_BCR2_A4SZ 0x0300 /* Area 4 Bus Width */ |
---|
| 728 | #define SH7750_BCR2_A4SZ_S 8 |
---|
| 729 | #define SH7750_BCR2_A3SZ 0x00C0 /* Area 3 Bus Width */ |
---|
| 730 | #define SH7750_BCR2_A3SZ_S 6 |
---|
| 731 | #define SH7750_BCR2_A2SZ 0x0030 /* Area 2 Bus Width */ |
---|
| 732 | #define SH7750_BCR2_A2SZ_S 4 |
---|
| 733 | #define SH7750_BCR2_A1SZ 0x000C /* Area 1 Bus Width */ |
---|
| 734 | #define SH7750_BCR2_A1SZ_S 2 |
---|
| 735 | #define SH7750_BCR2_SZ_64 0 /* 64 bits */ |
---|
| 736 | #define SH7750_BCR2_SZ_8 1 /* 8 bits */ |
---|
| 737 | #define SH7750_BCR2_SZ_16 2 /* 16 bits */ |
---|
| 738 | #define SH7750_BCR2_SZ_32 3 /* 32 bits */ |
---|
| 739 | #define SH7750_BCR2_PORTEN 0x0001 /* Port Function Enable : |
---|
| 740 | 0 - D51-D32 are not used as a port |
---|
| 741 | 1 - D51-D32 are used as a port */ |
---|
| 742 | |
---|
| 743 | /* Wait Control Register 1 - WCR1 */ |
---|
| 744 | #define SH7750_WCR1_REGOFS 0x800008 /* offset */ |
---|
| 745 | #define SH7750_WCR1 SH7750_P4_REG32(SH7750_WCR1_REGOFS) |
---|
| 746 | #define SH7750_WCR1_A7 SH7750_A7_REG32(SH7750_WCR1_REGOFS) |
---|
| 747 | #define SH7750_WCR1_DMAIW 0x70000000 /* DACK Device Inter-Cycle Idle |
---|
| 748 | specification */ |
---|
| 749 | #define SH7750_WCR1_DMAIW_S 28 |
---|
| 750 | #define SH7750_WCR1_A6IW 0x07000000 /* Area 6 Inter-Cycle Idle spec. */ |
---|
| 751 | #define SH7750_WCR1_A6IW_S 24 |
---|
| 752 | #define SH7750_WCR1_A5IW 0x00700000 /* Area 5 Inter-Cycle Idle spec. */ |
---|
| 753 | #define SH7750_WCR1_A5IW_S 20 |
---|
| 754 | #define SH7750_WCR1_A4IW 0x00070000 /* Area 4 Inter-Cycle Idle spec. */ |
---|
| 755 | #define SH7750_WCR1_A4IW_S 16 |
---|
| 756 | #define SH7750_WCR1_A3IW 0x00007000 /* Area 3 Inter-Cycle Idle spec. */ |
---|
| 757 | #define SH7750_WCR1_A3IW_S 12 |
---|
| 758 | #define SH7750_WCR1_A2IW 0x00000700 /* Area 2 Inter-Cycle Idle spec. */ |
---|
| 759 | #define SH7750_WCR1_A2IW_S 8 |
---|
| 760 | #define SH7750_WCR1_A1IW 0x00000070 /* Area 1 Inter-Cycle Idle spec. */ |
---|
| 761 | #define SH7750_WCR1_A1IW_S 4 |
---|
| 762 | #define SH7750_WCR1_A0IW 0x00000007 /* Area 0 Inter-Cycle Idle spec. */ |
---|
| 763 | #define SH7750_WCR1_A0IW_S 0 |
---|
| 764 | |
---|
| 765 | /* Wait Control Register 2 - WCR2 */ |
---|
| 766 | #define SH7750_WCR2_REGOFS 0x80000C /* offset */ |
---|
| 767 | #define SH7750_WCR2 SH7750_P4_REG32(SH7750_WCR2_REGOFS) |
---|
| 768 | #define SH7750_WCR2_A7 SH7750_A7_REG32(SH7750_WCR2_REGOFS) |
---|
| 769 | |
---|
| 770 | #define SH7750_WCR2_A6W 0xE0000000 /* Area 6 Wait Control */ |
---|
| 771 | #define SH7750_WCR2_A6W_S 29 |
---|
| 772 | #define SH7750_WCR2_A6B 0x1C000000 /* Area 6 Burst Pitch */ |
---|
| 773 | #define SH7750_WCR2_A6B_S 26 |
---|
| 774 | #define SH7750_WCR2_A5W 0x03800000 /* Area 5 Wait Control */ |
---|
| 775 | #define SH7750_WCR2_A5W_S 23 |
---|
| 776 | #define SH7750_WCR2_A5B 0x00700000 /* Area 5 Burst Pitch */ |
---|
| 777 | #define SH7750_WCR2_A5B_S 20 |
---|
| 778 | #define SH7750_WCR2_A4W 0x000E0000 /* Area 4 Wait Control */ |
---|
| 779 | #define SH7750_WCR2_A4W_S 17 |
---|
| 780 | #define SH7750_WCR2_A3W 0x0000E000 /* Area 3 Wait Control */ |
---|
| 781 | #define SH7750_WCR2_A3W_S 13 |
---|
| 782 | #define SH7750_WCR2_A2W 0x00000E00 /* Area 2 Wait Control */ |
---|
| 783 | #define SH7750_WCR2_A2W_S 9 |
---|
| 784 | #define SH7750_WCR2_A1W 0x000001C0 /* Area 1 Wait Control */ |
---|
| 785 | #define SH7750_WCR2_A1W_S 6 |
---|
| 786 | #define SH7750_WCR2_A0W 0x00000038 /* Area 0 Wait Control */ |
---|
| 787 | #define SH7750_WCR2_A0W_S 3 |
---|
| 788 | #define SH7750_WCR2_A0B 0x00000007 /* Area 0 Burst Pitch */ |
---|
| 789 | #define SH7750_WCR2_A0B_S 0 |
---|
| 790 | |
---|
| 791 | #define SH7750_WCR2_WS0 0 /* 0 wait states inserted */ |
---|
| 792 | #define SH7750_WCR2_WS1 1 /* 1 wait states inserted */ |
---|
| 793 | #define SH7750_WCR2_WS2 2 /* 2 wait states inserted */ |
---|
| 794 | #define SH7750_WCR2_WS3 3 /* 3 wait states inserted */ |
---|
| 795 | #define SH7750_WCR2_WS6 4 /* 6 wait states inserted */ |
---|
| 796 | #define SH7750_WCR2_WS9 5 /* 9 wait states inserted */ |
---|
| 797 | #define SH7750_WCR2_WS12 6 /* 12 wait states inserted */ |
---|
| 798 | #define SH7750_WCR2_WS15 7 /* 15 wait states inserted */ |
---|
| 799 | |
---|
| 800 | #define SH7750_WCR2_BPWS0 0 /* 0 wait states inserted from 2nd access */ |
---|
| 801 | #define SH7750_WCR2_BPWS1 1 /* 1 wait states inserted from 2nd access */ |
---|
| 802 | #define SH7750_WCR2_BPWS2 2 /* 2 wait states inserted from 2nd access */ |
---|
| 803 | #define SH7750_WCR2_BPWS3 3 /* 3 wait states inserted from 2nd access */ |
---|
| 804 | #define SH7750_WCR2_BPWS4 4 /* 4 wait states inserted from 2nd access */ |
---|
| 805 | #define SH7750_WCR2_BPWS5 5 /* 5 wait states inserted from 2nd access */ |
---|
| 806 | #define SH7750_WCR2_BPWS6 6 /* 6 wait states inserted from 2nd access */ |
---|
| 807 | #define SH7750_WCR2_BPWS7 7 /* 7 wait states inserted from 2nd access */ |
---|
| 808 | |
---|
| 809 | /* DRAM CAS\ Assertion Delay (area 3,2) */ |
---|
| 810 | #define SH7750_WCR2_DRAM_CAS_ASW1 0 /* 1 cycle */ |
---|
| 811 | #define SH7750_WCR2_DRAM_CAS_ASW2 1 /* 2 cycles */ |
---|
| 812 | #define SH7750_WCR2_DRAM_CAS_ASW3 2 /* 3 cycles */ |
---|
| 813 | #define SH7750_WCR2_DRAM_CAS_ASW4 3 /* 4 cycles */ |
---|
| 814 | #define SH7750_WCR2_DRAM_CAS_ASW7 4 /* 7 cycles */ |
---|
| 815 | #define SH7750_WCR2_DRAM_CAS_ASW10 5 /* 10 cycles */ |
---|
| 816 | #define SH7750_WCR2_DRAM_CAS_ASW13 6 /* 13 cycles */ |
---|
| 817 | #define SH7750_WCR2_DRAM_CAS_ASW16 7 /* 16 cycles */ |
---|
| 818 | |
---|
| 819 | /* SDRAM CAS\ Latency Cycles */ |
---|
| 820 | #define SH7750_WCR2_SDRAM_CAS_LAT1 1 /* 1 cycle */ |
---|
| 821 | #define SH7750_WCR2_SDRAM_CAS_LAT2 2 /* 2 cycles */ |
---|
| 822 | #define SH7750_WCR2_SDRAM_CAS_LAT3 3 /* 3 cycles */ |
---|
| 823 | #define SH7750_WCR2_SDRAM_CAS_LAT4 4 /* 4 cycles */ |
---|
| 824 | #define SH7750_WCR2_SDRAM_CAS_LAT5 5 /* 5 cycles */ |
---|
| 825 | |
---|
| 826 | /* Wait Control Register 3 - WCR3 */ |
---|
| 827 | #define SH7750_WCR3_REGOFS 0x800010 /* offset */ |
---|
| 828 | #define SH7750_WCR3 SH7750_P4_REG32(SH7750_WCR3_REGOFS) |
---|
| 829 | #define SH7750_WCR3_A7 SH7750_A7_REG32(SH7750_WCR3_REGOFS) |
---|
| 830 | |
---|
| 831 | #define SH7750_WCR3_A6S 0x04000000 /* Area 6 Write Strobe Setup time */ |
---|
| 832 | #define SH7750_WCR3_A6H 0x03000000 /* Area 6 Data Hold Time */ |
---|
| 833 | #define SH7750_WCR3_A6H_S 24 |
---|
| 834 | #define SH7750_WCR3_A5S 0x00400000 /* Area 5 Write Strobe Setup time */ |
---|
| 835 | #define SH7750_WCR3_A5H 0x00300000 /* Area 5 Data Hold Time */ |
---|
| 836 | #define SH7750_WCR3_A5H_S 20 |
---|
| 837 | #define SH7750_WCR3_A4S 0x00040000 /* Area 4 Write Strobe Setup time */ |
---|
| 838 | #define SH7750_WCR3_A4H 0x00030000 /* Area 4 Data Hold Time */ |
---|
| 839 | #define SH7750_WCR3_A4H_S 16 |
---|
| 840 | #define SH7750_WCR3_A3S 0x00004000 /* Area 3 Write Strobe Setup time */ |
---|
| 841 | #define SH7750_WCR3_A3H 0x00003000 /* Area 3 Data Hold Time */ |
---|
| 842 | #define SH7750_WCR3_A3H_S 12 |
---|
| 843 | #define SH7750_WCR3_A2S 0x00000400 /* Area 2 Write Strobe Setup time */ |
---|
| 844 | #define SH7750_WCR3_A2H 0x00000300 /* Area 2 Data Hold Time */ |
---|
| 845 | #define SH7750_WCR3_A2H_S 8 |
---|
| 846 | #define SH7750_WCR3_A1S 0x00000040 /* Area 1 Write Strobe Setup time */ |
---|
| 847 | #define SH7750_WCR3_A1H 0x00000030 /* Area 1 Data Hold Time */ |
---|
| 848 | #define SH7750_WCR3_A1H_S 4 |
---|
| 849 | #define SH7750_WCR3_A0S 0x00000004 /* Area 0 Write Strobe Setup time */ |
---|
| 850 | #define SH7750_WCR3_A0H 0x00000003 /* Area 0 Data Hold Time */ |
---|
| 851 | #define SH7750_WCR3_A0H_S 0 |
---|
| 852 | |
---|
| 853 | #define SH7750_WCR3_DHWS_0 0 /* 0 wait states data hold time */ |
---|
| 854 | #define SH7750_WCR3_DHWS_1 1 /* 1 wait states data hold time */ |
---|
| 855 | #define SH7750_WCR3_DHWS_2 2 /* 2 wait states data hold time */ |
---|
| 856 | #define SH7750_WCR3_DHWS_3 3 /* 3 wait states data hold time */ |
---|
| 857 | |
---|
| 858 | #define SH7750_MCR_REGOFS 0x800014 /* offset */ |
---|
| 859 | #define SH7750_MCR SH7750_P4_REG32(SH7750_MCR_REGOFS) |
---|
| 860 | #define SH7750_MCR_A7 SH7750_A7_REG32(SH7750_MCR_REGOFS) |
---|
| 861 | |
---|
| 862 | #define SH7750_MCR_RASD 0x80000000 /* RAS Down mode */ |
---|
| 863 | #define SH7750_MCR_MRSET 0x40000000 /* SDRAM Mode Register Set */ |
---|
| 864 | #define SH7750_MCR_PALL 0x00000000 /* SDRAM Precharge All cmd. Mode */ |
---|
| 865 | #define SH7750_MCR_TRC 0x38000000 /* RAS Precharge Time at End of |
---|
| 866 | Refresh: */ |
---|
| 867 | #define SH7750_MCR_TRC_0 0x00000000 /* 0 */ |
---|
| 868 | #define SH7750_MCR_TRC_3 0x08000000 /* 3 */ |
---|
| 869 | #define SH7750_MCR_TRC_6 0x10000000 /* 6 */ |
---|
| 870 | #define SH7750_MCR_TRC_9 0x18000000 /* 9 */ |
---|
| 871 | #define SH7750_MCR_TRC_12 0x20000000 /* 12 */ |
---|
| 872 | #define SH7750_MCR_TRC_15 0x28000000 /* 15 */ |
---|
| 873 | #define SH7750_MCR_TRC_18 0x30000000 /* 18 */ |
---|
| 874 | #define SH7750_MCR_TRC_21 0x38000000 /* 21 */ |
---|
| 875 | |
---|
| 876 | #define SH7750_MCR_TCAS 0x00800000 /* CAS Negation Period */ |
---|
| 877 | #define SH7750_MCR_TCAS_1 0x00000000 /* 1 */ |
---|
| 878 | #define SH7750_MCR_TCAS_2 0x00800000 /* 2 */ |
---|
| 879 | |
---|
| 880 | #define SH7750_MCR_TPC 0x00380000 /* DRAM: RAS Precharge Period |
---|
| 881 | SDRAM: minimum number of cycles |
---|
| 882 | until the next bank active cmd |
---|
| 883 | is output after precharging */ |
---|
| 884 | #define SH7750_MCR_TPC_S 19 |
---|
| 885 | #define SH7750_MCR_TPC_SDRAM_1 0x00000000 /* 1 cycle */ |
---|
| 886 | #define SH7750_MCR_TPC_SDRAM_2 0x00080000 /* 2 cycles */ |
---|
| 887 | #define SH7750_MCR_TPC_SDRAM_3 0x00100000 /* 3 cycles */ |
---|
| 888 | #define SH7750_MCR_TPC_SDRAM_4 0x00180000 /* 4 cycles */ |
---|
| 889 | #define SH7750_MCR_TPC_SDRAM_5 0x00200000 /* 5 cycles */ |
---|
| 890 | #define SH7750_MCR_TPC_SDRAM_6 0x00280000 /* 6 cycles */ |
---|
| 891 | #define SH7750_MCR_TPC_SDRAM_7 0x00300000 /* 7 cycles */ |
---|
| 892 | #define SH7750_MCR_TPC_SDRAM_8 0x00380000 /* 8 cycles */ |
---|
| 893 | |
---|
| 894 | #define SH7750_MCR_RCD 0x00030000 /* DRAM: RAS-CAS Assertion Delay time |
---|
| 895 | SDRAM: bank active-read/write cmd |
---|
| 896 | delay time */ |
---|
| 897 | #define SH7750_MCR_RCD_DRAM_2 0x00000000 /* DRAM delay 2 clocks */ |
---|
| 898 | #define SH7750_MCR_RCD_DRAM_3 0x00010000 /* DRAM delay 3 clocks */ |
---|
| 899 | #define SH7750_MCR_RCD_DRAM_4 0x00020000 /* DRAM delay 4 clocks */ |
---|
| 900 | #define SH7750_MCR_RCD_DRAM_5 0x00030000 /* DRAM delay 5 clocks */ |
---|
| 901 | #define SH7750_MCR_RCD_SDRAM_2 0x00010000 /* DRAM delay 2 clocks */ |
---|
| 902 | #define SH7750_MCR_RCD_SDRAM_3 0x00020000 /* DRAM delay 3 clocks */ |
---|
| 903 | #define SH7750_MCR_RCD_SDRAM_4 0x00030000 /* DRAM delay 4 clocks */ |
---|
| 904 | |
---|
| 905 | #define SH7750_MCR_TRWL 0x0000E000 /* SDRAM Write Precharge Delay */ |
---|
| 906 | #define SH7750_MCR_TRWL_1 0x00000000 /* 1 */ |
---|
| 907 | #define SH7750_MCR_TRWL_2 0x00002000 /* 2 */ |
---|
| 908 | #define SH7750_MCR_TRWL_3 0x00004000 /* 3 */ |
---|
| 909 | #define SH7750_MCR_TRWL_4 0x00006000 /* 4 */ |
---|
| 910 | #define SH7750_MCR_TRWL_5 0x00008000 /* 5 */ |
---|
| 911 | |
---|
| 912 | #define SH7750_MCR_TRAS 0x00001C00 /* DRAM: CAS-Before-RAS Refresh RAS |
---|
| 913 | asserting period |
---|
| 914 | SDRAM: Command interval after |
---|
| 915 | synchronous DRAM refresh */ |
---|
| 916 | #define SH7750_MCR_TRAS_DRAM_2 0x00000000 /* 2 */ |
---|
| 917 | #define SH7750_MCR_TRAS_DRAM_3 0x00000400 /* 3 */ |
---|
| 918 | #define SH7750_MCR_TRAS_DRAM_4 0x00000800 /* 4 */ |
---|
| 919 | #define SH7750_MCR_TRAS_DRAM_5 0x00000C00 /* 5 */ |
---|
| 920 | #define SH7750_MCR_TRAS_DRAM_6 0x00001000 /* 6 */ |
---|
| 921 | #define SH7750_MCR_TRAS_DRAM_7 0x00001400 /* 7 */ |
---|
| 922 | #define SH7750_MCR_TRAS_DRAM_8 0x00001800 /* 8 */ |
---|
| 923 | #define SH7750_MCR_TRAS_DRAM_9 0x00001C00 /* 9 */ |
---|
| 924 | |
---|
| 925 | #define SH7750_MCR_TRAS_SDRAM_TRC_4 0x00000000 /* 4 + TRC */ |
---|
| 926 | #define SH7750_MCR_TRAS_SDRAM_TRC_5 0x00000400 /* 5 + TRC */ |
---|
| 927 | #define SH7750_MCR_TRAS_SDRAM_TRC_6 0x00000800 /* 6 + TRC */ |
---|
| 928 | #define SH7750_MCR_TRAS_SDRAM_TRC_7 0x00000C00 /* 7 + TRC */ |
---|
| 929 | #define SH7750_MCR_TRAS_SDRAM_TRC_8 0x00001000 /* 8 + TRC */ |
---|
| 930 | #define SH7750_MCR_TRAS_SDRAM_TRC_9 0x00001400 /* 9 + TRC */ |
---|
| 931 | #define SH7750_MCR_TRAS_SDRAM_TRC_10 0x00001800 /* 10 + TRC */ |
---|
| 932 | #define SH7750_MCR_TRAS_SDRAM_TRC_11 0x00001C00 /* 11 + TRC */ |
---|
| 933 | |
---|
| 934 | #define SH7750_MCR_BE 0x00000200 /* Burst Enable */ |
---|
| 935 | #define SH7750_MCR_SZ 0x00000180 /* Memory Data Size */ |
---|
| 936 | #define SH7750_MCR_SZ_64 0x00000000 /* 64 bits */ |
---|
| 937 | #define SH7750_MCR_SZ_16 0x00000100 /* 16 bits */ |
---|
| 938 | #define SH7750_MCR_SZ_32 0x00000180 /* 32 bits */ |
---|
| 939 | |
---|
| 940 | #define SH7750_MCR_AMX 0x00000078 /* Address Multiplexing */ |
---|
| 941 | #define SH7750_MCR_AMX_S 3 |
---|
| 942 | #define SH7750_MCR_AMX_DRAM_8BIT_COL 0x00000000 /* 8-bit column addr */ |
---|
| 943 | #define SH7750_MCR_AMX_DRAM_9BIT_COL 0x00000008 /* 9-bit column addr */ |
---|
| 944 | #define SH7750_MCR_AMX_DRAM_10BIT_COL 0x00000010 /* 10-bit column addr */ |
---|
| 945 | #define SH7750_MCR_AMX_DRAM_11BIT_COL 0x00000018 /* 11-bit column addr */ |
---|
| 946 | #define SH7750_MCR_AMX_DRAM_12BIT_COL 0x00000020 /* 12-bit column addr */ |
---|
| 947 | /* See SH7750 Hardware Manual for SDRAM address multiplexor selection */ |
---|
| 948 | |
---|
| 949 | #define SH7750_MCR_RFSH 0x00000004 /* Refresh Control */ |
---|
| 950 | #define SH7750_MCR_RMODE 0x00000002 /* Refresh Mode: */ |
---|
| 951 | #define SH7750_MCR_RMODE_NORMAL 0x00000000 /* Normal Refresh Mode */ |
---|
| 952 | #define SH7750_MCR_RMODE_SELF 0x00000002 /* Self-Refresh Mode */ |
---|
| 953 | #define SH7750_MCR_RMODE_EDO 0x00000001 /* EDO Mode */ |
---|
| 954 | |
---|
| 955 | /* SDRAM Mode Set address */ |
---|
| 956 | #define SH7750_SDRAM_MODE_A2_BASE 0xFF900000 |
---|
| 957 | #define SH7750_SDRAM_MODE_A3_BASE 0xFF940000 |
---|
| 958 | #define SH7750_SDRAM_MODE_A2_32BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 2)) |
---|
| 959 | #define SH7750_SDRAM_MODE_A3_32BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 2)) |
---|
| 960 | #define SH7750_SDRAM_MODE_A2_64BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 3)) |
---|
| 961 | #define SH7750_SDRAM_MODE_A3_64BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 3)) |
---|
| 962 | |
---|
| 963 | |
---|
| 964 | /* PCMCIA Control Register (half) - PCR */ |
---|
| 965 | #define SH7750_PCR_REGOFS 0x800018 /* offset */ |
---|
| 966 | #define SH7750_PCR SH7750_P4_REG32(SH7750_PCR_REGOFS) |
---|
| 967 | #define SH7750_PCR_A7 SH7750_A7_REG32(SH7750_PCR_REGOFS) |
---|
| 968 | |
---|
| 969 | #define SH7750_PCR_A5PCW 0xC000 /* Area 5 PCMCIA Wait - Number of wait |
---|
| 970 | states to be added to the number of |
---|
| 971 | waits specified by WCR2 in a low-speed |
---|
| 972 | PCMCIA wait cycle */ |
---|
| 973 | #define SH7750_PCR_A5PCW_0 0x0000 /* 0 waits inserted */ |
---|
| 974 | #define SH7750_PCR_A5PCW_15 0x4000 /* 15 waits inserted */ |
---|
| 975 | #define SH7750_PCR_A5PCW_30 0x8000 /* 30 waits inserted */ |
---|
| 976 | #define SH7750_PCR_A5PCW_50 0xC000 /* 50 waits inserted */ |
---|
| 977 | |
---|
| 978 | #define SH7750_PCR_A6PCW 0x3000 /* Area 6 PCMCIA Wait - Number of wait |
---|
| 979 | states to be added to the number of |
---|
| 980 | waits specified by WCR2 in a low-speed |
---|
| 981 | PCMCIA wait cycle */ |
---|
| 982 | #define SH7750_PCR_A6PCW_0 0x0000 /* 0 waits inserted */ |
---|
| 983 | #define SH7750_PCR_A6PCW_15 0x1000 /* 15 waits inserted */ |
---|
| 984 | #define SH7750_PCR_A6PCW_30 0x2000 /* 30 waits inserted */ |
---|
| 985 | #define SH7750_PCR_A6PCW_50 0x3000 /* 50 waits inserted */ |
---|
| 986 | |
---|
| 987 | #define SH7750_PCR_A5TED 0x0E00 /* Area 5 Address-OE\/WE\ Assertion Delay, |
---|
| 988 | delay time from address output to |
---|
| 989 | OE\/WE\ assertion on the connected |
---|
| 990 | PCMCIA interface */ |
---|
| 991 | #define SH7750_PCR_A5TED_S 9 |
---|
| 992 | #define SH7750_PCR_A6TED 0x01C0 /* Area 6 Address-OE\/WE\ Assertion Delay*/ |
---|
| 993 | #define SH7750_PCR_A6TED_S 6 |
---|
| 994 | |
---|
| 995 | #define SH7750_PCR_TED_0WS 0 /* 0 Waits inserted */ |
---|
| 996 | #define SH7750_PCR_TED_1WS 1 /* 1 Waits inserted */ |
---|
| 997 | #define SH7750_PCR_TED_2WS 2 /* 2 Waits inserted */ |
---|
| 998 | #define SH7750_PCR_TED_3WS 3 /* 3 Waits inserted */ |
---|
| 999 | #define SH7750_PCR_TED_6WS 4 /* 6 Waits inserted */ |
---|
| 1000 | #define SH7750_PCR_TED_9WS 5 /* 9 Waits inserted */ |
---|
| 1001 | #define SH7750_PCR_TED_12WS 6 /* 12 Waits inserted */ |
---|
| 1002 | #define SH7750_PCR_TED_15WS 7 /* 15 Waits inserted */ |
---|
| 1003 | |
---|
| 1004 | #define SH7750_PCR_A5TEH 0x0038 /* Area 5 OE\/WE\ Negation Address delay, |
---|
| 1005 | address hold delay time from OE\/WE\ |
---|
| 1006 | negation in a write on the connected |
---|
| 1007 | PCMCIA interface */ |
---|
| 1008 | #define SH7750_PCR_A5TEH_S 3 |
---|
| 1009 | |
---|
| 1010 | #define SH7750_PCR_A6TEH 0x0007 /* Area 6 OE\/WE\ Negation Address delay*/ |
---|
| 1011 | #define SH7750_PCR_A6TEH_S 0 |
---|
| 1012 | |
---|
| 1013 | #define SH7750_PCR_TEH_0WS 0 /* 0 Waits inserted */ |
---|
| 1014 | #define SH7750_PCR_TEH_1WS 1 /* 1 Waits inserted */ |
---|
| 1015 | #define SH7750_PCR_TEH_2WS 2 /* 2 Waits inserted */ |
---|
| 1016 | #define SH7750_PCR_TEH_3WS 3 /* 3 Waits inserted */ |
---|
| 1017 | #define SH7750_PCR_TEH_6WS 4 /* 6 Waits inserted */ |
---|
| 1018 | #define SH7750_PCR_TEH_9WS 5 /* 9 Waits inserted */ |
---|
| 1019 | #define SH7750_PCR_TEH_12WS 6 /* 12 Waits inserted */ |
---|
| 1020 | #define SH7750_PCR_TEH_15WS 7 /* 15 Waits inserted */ |
---|
| 1021 | |
---|
| 1022 | /* Refresh Timer Control/Status Register (half) - RTSCR */ |
---|
| 1023 | #define SH7750_RTCSR_REGOFS 0x80001C /* offset */ |
---|
| 1024 | #define SH7750_RTCSR SH7750_P4_REG32(SH7750_RTCSR_REGOFS) |
---|
| 1025 | #define SH7750_RTCSR_A7 SH7750_A7_REG32(SH7750_RTCSR_REGOFS) |
---|
| 1026 | |
---|
| 1027 | #define SH7750_RTCSR_KEY 0xA500 /* RTCSR write key */ |
---|
| 1028 | #define SH7750_RTCSR_CMF 0x0080 /* Compare-Match Flag (indicates a |
---|
| 1029 | match between the refresh timer |
---|
| 1030 | counter and refresh time constant) */ |
---|
| 1031 | #define SH7750_RTCSR_CMIE 0x0040 /* Compare-Match Interrupt Enable */ |
---|
| 1032 | #define SH7750_RTCSR_CKS 0x0038 /* Refresh Counter Clock Selects */ |
---|
| 1033 | #define SH7750_RTCSR_CKS_DIS 0x0000 /* Clock Input Disabled */ |
---|
| 1034 | #define SH7750_RTCSR_CKS_CKIO_DIV4 0x0008 /* Bus Clock / 4 */ |
---|
| 1035 | #define SH7750_RTCSR_CKS_CKIO_DIV16 0x0010 /* Bus Clock / 16 */ |
---|
| 1036 | #define SH7750_RTCSR_CKS_CKIO_DIV64 0x0018 /* Bus Clock / 64 */ |
---|
| 1037 | #define SH7750_RTCSR_CKS_CKIO_DIV256 0x0020 /* Bus Clock / 256 */ |
---|
| 1038 | #define SH7750_RTCSR_CKS_CKIO_DIV1024 0x0028 /* Bus Clock / 1024 */ |
---|
| 1039 | #define SH7750_RTCSR_CKS_CKIO_DIV2048 0x0030 /* Bus Clock / 2048 */ |
---|
| 1040 | #define SH7750_RTCSR_CKS_CKIO_DIV4096 0x0038 /* Bus Clock / 4096 */ |
---|
| 1041 | |
---|
| 1042 | #define SH7750_RTCSR_OVF 0x0004 /* Refresh Count Overflow Flag */ |
---|
| 1043 | #define SH7750_RTCSR_OVIE 0x0002 /* Refresh Count Overflow Interrupt |
---|
| 1044 | Enable */ |
---|
| 1045 | #define SH7750_RTCSR_LMTS 0x0001 /* Refresh Count Overflow Limit Select */ |
---|
| 1046 | #define SH7750_RTCSR_LMTS_1024 0x0000 /* Count Limit is 1024 */ |
---|
| 1047 | #define SH7750_RTCSR_LMTS_512 0x0001 /* Count Limit is 512 */ |
---|
| 1048 | |
---|
| 1049 | /* Refresh Timer Counter (half) - RTCNT */ |
---|
| 1050 | #define SH7750_RTCNT_REGOFS 0x800020 /* offset */ |
---|
| 1051 | #define SH7750_RTCNT SH7750_P4_REG32(SH7750_RTCNT_REGOFS) |
---|
| 1052 | #define SH7750_RTCNT_A7 SH7750_A7_REG32(SH7750_RTCNT_REGOFS) |
---|
| 1053 | |
---|
| 1054 | #define SH7750_RTCNT_KEY 0xA500 /* RTCNT write key */ |
---|
| 1055 | |
---|
| 1056 | /* Refresh Time Constant Register (half) - RTCOR */ |
---|
| 1057 | #define SH7750_RTCOR_REGOFS 0x800024 /* offset */ |
---|
| 1058 | #define SH7750_RTCOR SH7750_P4_REG32(SH7750_RTCOR_REGOFS) |
---|
| 1059 | #define SH7750_RTCOR_A7 SH7750_A7_REG32(SH7750_RTCOR_REGOFS) |
---|
| 1060 | |
---|
| 1061 | #define SH7750_RTCOR_KEY 0xA500 /* RTCOR write key */ |
---|
| 1062 | |
---|
| 1063 | /* Refresh Count Register (half) - RFCR */ |
---|
| 1064 | #define SH7750_RFCR_REGOFS 0x800028 /* offset */ |
---|
| 1065 | #define SH7750_RFCR SH7750_P4_REG32(SH7750_RFCR_REGOFS) |
---|
| 1066 | #define SH7750_RFCR_A7 SH7750_A7_REG32(SH7750_RFCR_REGOFS) |
---|
| 1067 | |
---|
| 1068 | #define SH7750_RFCR_KEY 0xA400 /* RFCR write key */ |
---|
| 1069 | |
---|
| 1070 | /* |
---|
| 1071 | * Direct Memory Access Controller (DMAC) |
---|
| 1072 | */ |
---|
| 1073 | |
---|
| 1074 | /* DMA Source Address Register - SAR0, SAR1, SAR2, SAR3 */ |
---|
| 1075 | #define SH7750_SAR_REGOFS(n) (0xA00000 + ((n)*16)) /* offset */ |
---|
| 1076 | #define SH7750_SAR(n) SH7750_P4_REG32(SH7750_SAR_REGOFS(n)) |
---|
| 1077 | #define SH7750_SAR_A7(n) SH7750_A7_REG32(SH7750_SAR_REGOFS(n)) |
---|
| 1078 | #define SH7750_SAR0 SH7750_SAR(0) |
---|
| 1079 | #define SH7750_SAR1 SH7750_SAR(1) |
---|
| 1080 | #define SH7750_SAR2 SH7750_SAR(2) |
---|
| 1081 | #define SH7750_SAR3 SH7750_SAR(3) |
---|
| 1082 | #define SH7750_SAR0_A7 SH7750_SAR_A7(0) |
---|
| 1083 | #define SH7750_SAR1_A7 SH7750_SAR_A7(1) |
---|
| 1084 | #define SH7750_SAR2_A7 SH7750_SAR_A7(2) |
---|
| 1085 | #define SH7750_SAR3_A7 SH7750_SAR_A7(3) |
---|
| 1086 | |
---|
| 1087 | /* DMA Destination Address Register - DAR0, DAR1, DAR2, DAR3 */ |
---|
| 1088 | #define SH7750_DAR_REGOFS(n) (0xA00004 + ((n)*16)) /* offset */ |
---|
| 1089 | #define SH7750_DAR(n) SH7750_P4_REG32(SH7750_DAR_REGOFS(n)) |
---|
| 1090 | #define SH7750_DAR_A7(n) SH7750_A7_REG32(SH7750_DAR_REGOFS(n)) |
---|
| 1091 | #define SH7750_DAR0 SH7750_DAR(0) |
---|
| 1092 | #define SH7750_DAR1 SH7750_DAR(1) |
---|
| 1093 | #define SH7750_DAR2 SH7750_DAR(2) |
---|
| 1094 | #define SH7750_DAR3 SH7750_DAR(3) |
---|
| 1095 | #define SH7750_DAR0_A7 SH7750_DAR_A7(0) |
---|
| 1096 | #define SH7750_DAR1_A7 SH7750_DAR_A7(1) |
---|
| 1097 | #define SH7750_DAR2_A7 SH7750_DAR_A7(2) |
---|
| 1098 | #define SH7750_DAR3_A7 SH7750_DAR_A7(3) |
---|
| 1099 | |
---|
| 1100 | /* DMA Transfer Count Register - DMATCR0, DMATCR1, DMATCR2, DMATCR3 */ |
---|
| 1101 | #define SH7750_DMATCR_REGOFS(n) (0xA00008 + ((n)*16)) /* offset */ |
---|
| 1102 | #define SH7750_DMATCR(n) SH7750_P4_REG32(SH7750_DMATCR_REGOFS(n)) |
---|
| 1103 | #define SH7750_DMATCR_A7(n) SH7750_A7_REG32(SH7750_DMATCR_REGOFS(n)) |
---|
| 1104 | #define SH7750_DMATCR0_P4 SH7750_DMATCR(0) |
---|
| 1105 | #define SH7750_DMATCR1_P4 SH7750_DMATCR(1) |
---|
| 1106 | #define SH7750_DMATCR2_P4 SH7750_DMATCR(2) |
---|
| 1107 | #define SH7750_DMATCR3_P4 SH7750_DMATCR(3) |
---|
| 1108 | #define SH7750_DMATCR0_A7 SH7750_DMATCR_A7(0) |
---|
| 1109 | #define SH7750_DMATCR1_A7 SH7750_DMATCR_A7(1) |
---|
| 1110 | #define SH7750_DMATCR2_A7 SH7750_DMATCR_A7(2) |
---|
| 1111 | #define SH7750_DMATCR3_A7 SH7750_DMATCR_A7(3) |
---|
| 1112 | |
---|
| 1113 | /* DMA Channel Control Register - CHCR0, CHCR1, CHCR2, CHCR3 */ |
---|
| 1114 | #define SH7750_CHCR_REGOFS(n) (0xA0000C + ((n)*16)) /* offset */ |
---|
| 1115 | #define SH7750_CHCR(n) SH7750_P4_REG32(SH7750_CHCR_REGOFS(n)) |
---|
| 1116 | #define SH7750_CHCR_A7(n) SH7750_A7_REG32(SH7750_CHCR_REGOFS(n)) |
---|
| 1117 | #define SH7750_CHCR0 SH7750_CHCR(0) |
---|
| 1118 | #define SH7750_CHCR1 SH7750_CHCR(1) |
---|
| 1119 | #define SH7750_CHCR2 SH7750_CHCR(2) |
---|
| 1120 | #define SH7750_CHCR3 SH7750_CHCR(3) |
---|
| 1121 | #define SH7750_CHCR0_A7 SH7750_CHCR_A7(0) |
---|
| 1122 | #define SH7750_CHCR1_A7 SH7750_CHCR_A7(1) |
---|
| 1123 | #define SH7750_CHCR2_A7 SH7750_CHCR_A7(2) |
---|
| 1124 | #define SH7750_CHCR3_A7 SH7750_CHCR_A7(3) |
---|
| 1125 | |
---|
| 1126 | #define SH7750_CHCR_SSA 0xE0000000 /* Source Address Space Attribute */ |
---|
| 1127 | #define SH7750_CHCR_SSA_PCMCIA 0x00000000 /* Reserved in PCMCIA access */ |
---|
| 1128 | #define SH7750_CHCR_SSA_DYNBSZ 0x20000000 /* Dynamic Bus Sizing I/O space */ |
---|
| 1129 | #define SH7750_CHCR_SSA_IO8 0x40000000 /* 8-bit I/O space */ |
---|
| 1130 | #define SH7750_CHCR_SSA_IO16 0x60000000 /* 16-bit I/O space */ |
---|
| 1131 | #define SH7750_CHCR_SSA_CMEM8 0x80000000 /* 8-bit common memory space */ |
---|
| 1132 | #define SH7750_CHCR_SSA_CMEM16 0xA0000000 /* 16-bit common memory space */ |
---|
| 1133 | #define SH7750_CHCR_SSA_AMEM8 0xC0000000 /* 8-bit attribute memory space */ |
---|
| 1134 | #define SH7750_CHCR_SSA_AMEM16 0xE0000000 /* 16-bit attribute memory space */ |
---|
| 1135 | |
---|
| 1136 | #define SH7750_CHCR_STC 0x10000000 /* Source Address Wait Control Select, |
---|
| 1137 | specifies CS5 or CS6 space wait |
---|
| 1138 | control for PCMCIA access */ |
---|
| 1139 | |
---|
| 1140 | #define SH7750_CHCR_DSA 0x0E000000 /* Source Address Space Attribute */ |
---|
| 1141 | #define SH7750_CHCR_DSA_PCMCIA 0x00000000 /* Reserved in PCMCIA access */ |
---|
| 1142 | #define SH7750_CHCR_DSA_DYNBSZ 0x02000000 /* Dynamic Bus Sizing I/O space */ |
---|
| 1143 | #define SH7750_CHCR_DSA_IO8 0x04000000 /* 8-bit I/O space */ |
---|
| 1144 | #define SH7750_CHCR_DSA_IO16 0x06000000 /* 16-bit I/O space */ |
---|
| 1145 | #define SH7750_CHCR_DSA_CMEM8 0x08000000 /* 8-bit common memory space */ |
---|
| 1146 | #define SH7750_CHCR_DSA_CMEM16 0x0A000000 /* 16-bit common memory space */ |
---|
| 1147 | #define SH7750_CHCR_DSA_AMEM8 0x0C000000 /* 8-bit attribute memory space */ |
---|
| 1148 | #define SH7750_CHCR_DSA_AMEM16 0x0E000000 /* 16-bit attribute memory space */ |
---|
| 1149 | |
---|
| 1150 | #define SH7750_CHCR_DTC 0x01000000 /* Destination Address Wait Control |
---|
| 1151 | Select, specifies CS5 or CS6 |
---|
| 1152 | space wait control for PCMCIA |
---|
| 1153 | access */ |
---|
| 1154 | |
---|
| 1155 | #define SH7750_CHCR_DS 0x00080000 /* DREQ\ Select : */ |
---|
| 1156 | #define SH7750_CHCR_DS_LOWLVL 0x00000000 /* Low Level Detection */ |
---|
| 1157 | #define SH7750_CHCR_DS_FALL 0x00080000 /* Falling Edge Detection */ |
---|
| 1158 | |
---|
| 1159 | #define SH7750_CHCR_RL 0x00040000 /* Request Check Level: */ |
---|
| 1160 | #define SH7750_CHCR_RL_ACTH 0x00000000 /* DRAK is an active high out */ |
---|
| 1161 | #define SH7750_CHCR_RL_ACTL 0x00040000 /* DRAK is an active low out */ |
---|
| 1162 | |
---|
| 1163 | #define SH7750_CHCR_AM 0x00020000 /* Acknowledge Mode: */ |
---|
| 1164 | #define SH7750_CHCR_AM_RD 0x00000000 /* DACK is output in read cycle */ |
---|
| 1165 | #define SH7750_CHCR_AM_WR 0x00020000 /* DACK is output in write cycle*/ |
---|
| 1166 | |
---|
| 1167 | #define SH7750_CHCR_AL 0x00010000 /* Acknowledge Level: */ |
---|
| 1168 | #define SH7750_CHCR_AL_ACTH 0x00000000 /* DACK is an active high out */ |
---|
| 1169 | #define SH7750_CHCR_AL_ACTL 0x00010000 /* DACK is an active low out */ |
---|
| 1170 | |
---|
| 1171 | #define SH7750_CHCR_DM 0x0000C000 /* Destination Address Mode: */ |
---|
| 1172 | #define SH7750_CHCR_DM_FIX 0x00000000 /* Destination Addr Fixed */ |
---|
| 1173 | #define SH7750_CHCR_DM_INC 0x00004000 /* Destination Addr Incremented */ |
---|
| 1174 | #define SH7750_CHCR_DM_DEC 0x00008000 /* Destination Addr Decremented */ |
---|
| 1175 | |
---|
| 1176 | #define SH7750_CHCR_SM 0x00003000 /* Source Address Mode: */ |
---|
| 1177 | #define SH7750_CHCR_SM_FIX 0x00000000 /* Source Addr Fixed */ |
---|
| 1178 | #define SH7750_CHCR_SM_INC 0x00001000 /* Source Addr Incremented */ |
---|
| 1179 | #define SH7750_CHCR_SM_DEC 0x00002000 /* Source Addr Decremented */ |
---|
| 1180 | |
---|
| 1181 | #define SH7750_CHCR_RS 0x00000F00 /* Request Source Select: */ |
---|
| 1182 | #define SH7750_CHCR_RS_ER_DA_EA_TO_EA 0x000 /* External Request, Dual Address |
---|
| 1183 | Mode (External Addr Space-> |
---|
| 1184 | External Addr Space) */ |
---|
| 1185 | #define SH7750_CHCR_RS_ER_SA_EA_TO_ED 0x200 /* External Request, Single |
---|
| 1186 | Address Mode (External Addr |
---|
| 1187 | Space -> External Device) */ |
---|
| 1188 | #define SH7750_CHCR_RS_ER_SA_ED_TO_EA 0x300 /* External Request, Single |
---|
| 1189 | Address Mode, (External |
---|
| 1190 | Device -> External Addr |
---|
| 1191 | Space)*/ |
---|
| 1192 | #define SH7750_CHCR_RS_AR_EA_TO_EA 0x400 /* Auto-Request (External Addr |
---|
| 1193 | Space -> External Addr Space)*/ |
---|
| 1194 | |
---|
| 1195 | #define SH7750_CHCR_RS_AR_EA_TO_OCP 0x500 /* Auto-Request (External Addr |
---|
| 1196 | Space -> On-chip Peripheral |
---|
| 1197 | Module) */ |
---|
| 1198 | #define SH7750_CHCR_RS_AR_OCP_TO_EA 0x600 /* Auto-Request (On-chip |
---|
| 1199 | Peripheral Module -> |
---|
| 1200 | External Addr Space */ |
---|
| 1201 | #define SH7750_CHCR_RS_SCITX_EA_TO_SC 0x800 /* SCI Transmit-Data-Empty intr |
---|
| 1202 | transfer request (external |
---|
| 1203 | address space -> SCTDR1) */ |
---|
| 1204 | #define SH7750_CHCR_RS_SCIRX_SC_TO_EA 0x900 /* SCI Receive-Data-Full intr |
---|
| 1205 | transfer request (SCRDR1 -> |
---|
| 1206 | External Addr Space) */ |
---|
| 1207 | #define SH7750_CHCR_RS_SCIFTX_EA_TO_SC 0xA00 /* SCIF Transmit-Data-Empty intr |
---|
| 1208 | transfer request (external |
---|
| 1209 | address space -> SCFTDR1) */ |
---|
| 1210 | #define SH7750_CHCR_RS_SCIFRX_SC_TO_EA 0xB00 /* SCIF Receive-Data-Full intr |
---|
| 1211 | transfer request (SCFRDR2 -> |
---|
| 1212 | External Addr Space) */ |
---|
| 1213 | #define SH7750_CHCR_RS_TMU2_EA_TO_EA 0xC00 /* TMU Channel 2 (input capture |
---|
| 1214 | interrupt), (external address |
---|
| 1215 | space -> external address |
---|
| 1216 | space) */ |
---|
| 1217 | #define SH7750_CHCR_RS_TMU2_EA_TO_OCP 0xD00 /* TMU Channel 2 (input capture |
---|
| 1218 | interrupt), (external address |
---|
| 1219 | space -> on-chip peripheral |
---|
| 1220 | module) */ |
---|
| 1221 | #define SH7750_CHCR_RS_TMU2_OCP_TO_EA 0xE00 /* TMU Channel 2 (input capture |
---|
| 1222 | interrupt), (on-chip |
---|
| 1223 | peripheral module -> external |
---|
| 1224 | address space) */ |
---|
| 1225 | |
---|
| 1226 | #define SH7750_CHCR_TM 0x00000080 /* Transmit mode: */ |
---|
| 1227 | #define SH7750_CHCR_TM_CSTEAL 0x00000000 /* Cycle Steal Mode */ |
---|
| 1228 | #define SH7750_CHCR_TM_BURST 0x00000080 /* Burst Mode */ |
---|
| 1229 | |
---|
| 1230 | #define SH7750_CHCR_TS 0x00000070 /* Transmit Size: */ |
---|
| 1231 | #define SH7750_CHCR_TS_QUAD 0x00000000 /* Quadword Size (64 bits) */ |
---|
| 1232 | #define SH7750_CHCR_TS_BYTE 0x00000010 /* Byte Size (8 bit) */ |
---|
| 1233 | #define SH7750_CHCR_TS_WORD 0x00000020 /* Word Size (16 bit) */ |
---|
| 1234 | #define SH7750_CHCR_TS_LONG 0x00000030 /* Longword Size (32 bit) */ |
---|
| 1235 | #define SH7750_CHCR_TS_BLOCK 0x00000040 /* 32-byte block transfer */ |
---|
| 1236 | |
---|
| 1237 | #define SH7750_CHCR_IE 0x00000004 /* Interrupt Enable */ |
---|
| 1238 | #define SH7750_CHCR_TE 0x00000002 /* Transfer End */ |
---|
| 1239 | #define SH7750_CHCR_DE 0x00000001 /* DMAC Enable */ |
---|
| 1240 | |
---|
| 1241 | /* DMA Operation Register - DMAOR */ |
---|
| 1242 | #define SH7750_DMAOR_REGOFS 0xA00040 /* offset */ |
---|
| 1243 | #define SH7750_DMAOR SH7750_P4_REG32(SH7750_DMAOR_REGOFS) |
---|
| 1244 | #define SH7750_DMAOR_A7 SH7750_A7_REG32(SH7750_DMAOR_REGOFS) |
---|
| 1245 | |
---|
| 1246 | #define SH7750_DMAOR_DDT 0x00008000 /* On-Demand Data Transfer Mode */ |
---|
| 1247 | |
---|
| 1248 | #define SH7750_DMAOR_PR 0x00000300 /* Priority Mode: */ |
---|
| 1249 | #define SH7750_DMAOR_PR_0123 0x00000000 /* CH0 > CH1 > CH2 > CH3 */ |
---|
| 1250 | #define SH7750_DMAOR_PR_0231 0x00000100 /* CH0 > CH2 > CH3 > CH1 */ |
---|
| 1251 | #define SH7750_DMAOR_PR_2013 0x00000200 /* CH2 > CH0 > CH1 > CH3 */ |
---|
| 1252 | #define SH7750_DMAOR_PR_RR 0x00000300 /* Round-robin mode */ |
---|
| 1253 | |
---|
| 1254 | #define SH7750_DMAOR_COD 0x00000010 /* Check Overrun for DREQ\ */ |
---|
| 1255 | #define SH7750_DMAOR_AE 0x00000004 /* Address Error flag */ |
---|
| 1256 | #define SH7750_DMAOR_NMIF 0x00000002 /* NMI Flag */ |
---|
| 1257 | #define SH7750_DMAOR_DME 0x00000001 /* DMAC Master Enable */ |
---|
| 1258 | |
---|
| 1259 | /* |
---|
| 1260 | * Serial Communication Interface - SCI |
---|
| 1261 | * Serial Communication Interface with FIFO - SCIF |
---|
| 1262 | */ |
---|
| 1263 | /* SCI Receive Data Register (byte, read-only) - SCRDR1, SCFRDR2 */ |
---|
| 1264 | #define SH7750_SCRDR_REGOFS(n) ((n) == 1 ? 0xE00014 : 0xE80014) /* offset */ |
---|
| 1265 | #define SH7750_SCRDR(n) SH7750_P4_REG32(SH7750_SCRDR_REGOFS(n)) |
---|
| 1266 | #define SH7750_SCRDR1 SH7750_SCRDR(1) |
---|
| 1267 | #define SH7750_SCRDR2 SH7750_SCRDR(2) |
---|
| 1268 | #define SH7750_SCRDR_A7(n) SH7750_A7_REG32(SH7750_SCRDR_REGOFS(n)) |
---|
| 1269 | #define SH7750_SCRDR1_A7 SH7750_SCRDR_A7(1) |
---|
| 1270 | #define SH7750_SCRDR2_A7 SH7750_SCRDR_A7(2) |
---|
| 1271 | |
---|
| 1272 | /* SCI Transmit Data Register (byte) - SCTDR1, SCFTDR2 */ |
---|
| 1273 | #define SH7750_SCTDR_REGOFS(n) ((n) == 1 ? 0xE0000C : 0xE8000C) /* offset */ |
---|
| 1274 | #define SH7750_SCTDR(n) SH7750_P4_REG32(SH7750_SCTDR_REGOFS(n)) |
---|
| 1275 | #define SH7750_SCTDR1 SH7750_SCTDR(1) |
---|
| 1276 | #define SH7750_SCTDR2 SH7750_SCTDR(2) |
---|
| 1277 | #define SH7750_SCTDR_A7(n) SH7750_A7_REG32(SH7750_SCTDR_REGOFS(n)) |
---|
| 1278 | #define SH7750_SCTDR1_A7 SH7750_SCTDR_A7(1) |
---|
| 1279 | #define SH7750_SCTDR2_A7 SH7750_SCTDR_A7(2) |
---|
| 1280 | |
---|
| 1281 | /* SCI Serial Mode Register - SCSMR1(byte), SCSMR2(half) */ |
---|
| 1282 | #define SH7750_SCSMR_REGOFS(n) ((n) == 1 ? 0xE00000 : 0xE80000) /* offset */ |
---|
| 1283 | #define SH7750_SCSMR(n) SH7750_P4_REG32(SH7750_SCSMR_REGOFS(n)) |
---|
| 1284 | #define SH7750_SCSMR1 SH7750_SCSMR(1) |
---|
| 1285 | #define SH7750_SCSMR2 SH7750_SCSMR(2) |
---|
| 1286 | #define SH7750_SCSMR_A7(n) SH7750_A7_REG32(SH7750_SCSMR_REGOFS(n)) |
---|
| 1287 | #define SH7750_SCSMR1_A7 SH7750_SCSMR_A7(1) |
---|
| 1288 | #define SH7750_SCSMR2_A7 SH7750_SCSMR_A7(2) |
---|
| 1289 | |
---|
| 1290 | #define SH7750_SCSMR1_CA 0x80 /* Communication Mode (C/A\): */ |
---|
| 1291 | #define SH7750_SCSMR1_CA_ASYNC 0x00 /* Asynchronous Mode */ |
---|
| 1292 | #define SH7750_SCSMR1_CA_SYNC 0x80 /* Synchronous Mode */ |
---|
| 1293 | #define SH7750_SCSMR_CHR 0x40 /* Character Length: */ |
---|
| 1294 | #define SH7750_SCSMR_CHR_8 0x00 /* 8-bit data */ |
---|
| 1295 | #define SH7750_SCSMR_CHR_7 0x40 /* 7-bit data */ |
---|
| 1296 | #define SH7750_SCSMR_PE 0x20 /* Parity Enable */ |
---|
| 1297 | #define SH7750_SCSMR_PM 0x10 /* Parity Mode: */ |
---|
| 1298 | #define SH7750_SCSMR_PM_EVEN 0x00 /* Even Parity */ |
---|
| 1299 | #define SH7750_SCSMR_PM_ODD 0x10 /* Odd Parity */ |
---|
| 1300 | #define SH7750_SCSMR_STOP 0x08 /* Stop Bit Length: */ |
---|
| 1301 | #define SH7750_SCSMR_STOP_1 0x00 /* 1 stop bit */ |
---|
| 1302 | #define SH7750_SCSMR_STOP_2 0x08 /* 2 stop bit */ |
---|
| 1303 | #define SH7750_SCSMR1_MP 0x04 /* Multiprocessor Mode */ |
---|
| 1304 | #define SH7750_SCSMR_CKS 0x03 /* Clock Select */ |
---|
| 1305 | #define SH7750_SCSMR_CKS_DIV1 0x00 /* Periph clock */ |
---|
| 1306 | #define SH7750_SCSMR_CKS_DIV4 0x01 /* Periph clock / 4 */ |
---|
| 1307 | #define SH7750_SCSMR_CKS_DIV16 0x02 /* Periph clock / 16 */ |
---|
| 1308 | #define SH7750_SCSMR_CKS_DIV64 0x03 /* Periph clock / 64 */ |
---|
| 1309 | |
---|
| 1310 | /* SCI Serial Control Register - SCSCR1(byte), SCSCR2(half) */ |
---|
| 1311 | #define SH7750_SCSCR_REGOFS(n) ((n) == 1 ? 0xE00008 : 0xE80008) /* offset */ |
---|
| 1312 | #define SH7750_SCSCR(n) SH7750_P4_REG32(SH7750_SCSCR_REGOFS(n)) |
---|
| 1313 | #define SH7750_SCSCR1 SH7750_SCSCR(1) |
---|
| 1314 | #define SH7750_SCSCR2 SH7750_SCSCR(2) |
---|
| 1315 | #define SH7750_SCSCR_A7(n) SH7750_A7_REG32(SH7750_SCSCR_REGOFS(n)) |
---|
| 1316 | #define SH7750_SCSCR1_A7 SH7750_SCSCR_A7(1) |
---|
| 1317 | #define SH7750_SCSCR2_A7 SH7750_SCSCR_A7(2) |
---|
| 1318 | |
---|
| 1319 | #define SH7750_SCSCR_TIE 0x80 /* Transmit Interrupt Enable */ |
---|
| 1320 | #define SH7750_SCSCR_RIE 0x40 /* Receive Interrupt Enable */ |
---|
| 1321 | #define SH7750_SCSCR_TE 0x20 /* Transmit Enable */ |
---|
| 1322 | #define SH7750_SCSCR_RE 0x10 /* Receive Enable */ |
---|
| 1323 | #define SH7750_SCSCR1_MPIE 0x08 /* Multiprocessor Interrupt Enable */ |
---|
| 1324 | #define SH7750_SCSCR2_REIE 0x08 /* Receive Error Interrupt Enable */ |
---|
| 1325 | #define SH7750_SCSCR1_TEIE 0x04 /* Transmit End Interrupt Enable */ |
---|
| 1326 | #define SH7750_SCSCR1_CKE 0x03 /* Clock Enable: */ |
---|
| 1327 | #define SH7750_SCSCR_CKE_INTCLK 0x00 /* Use Internal Clock */ |
---|
| 1328 | #define SH7750_SCSCR_CKE_EXTCLK 0x02 /* Use External Clock from SCK*/ |
---|
| 1329 | #define SH7750_SCSCR1_CKE_ASYNC_SCK_CLKOUT 0x01 /* Use SCK as a clock output |
---|
| 1330 | in asynchronous mode */ |
---|
| 1331 | |
---|
| 1332 | /* SCI Serial Status Register - SCSSR1(byte), SCSSR2(half) */ |
---|
| 1333 | #define SH7750_SCSSR_REGOFS(n) ((n) == 1 ? 0xE00010 : 0xE80010) /* offset */ |
---|
| 1334 | #define SH7750_SCSSR(n) SH7750_P4_REG32(SH7750_SCSSR_REGOFS(n)) |
---|
| 1335 | #define SH7750_SCSSR1 SH7750_SCSSR(1) |
---|
| 1336 | #define SH7750_SCSSR2 SH7750_SCSSR(2) |
---|
| 1337 | #define SH7750_SCSSR_A7(n) SH7750_A7_REG32(SH7750_SCSSR_REGOFS(n)) |
---|
| 1338 | #define SH7750_SCSSR1_A7 SH7750_SCSSR_A7(1) |
---|
| 1339 | #define SH7750_SCSSR2_A7 SH7750_SCSSR_A7(2) |
---|
| 1340 | |
---|
| 1341 | #define SH7750_SCSSR1_TDRE 0x80 /* Transmit Data Register Empty */ |
---|
| 1342 | #define SH7750_SCSSR1_RDRF 0x40 /* Receive Data Register Full */ |
---|
| 1343 | #define SH7750_SCSSR1_ORER 0x20 /* Overrun Error */ |
---|
| 1344 | #define SH7750_SCSSR1_FER 0x10 /* Framing Error */ |
---|
| 1345 | #define SH7750_SCSSR1_PER 0x08 /* Parity Error */ |
---|
| 1346 | #define SH7750_SCSSR1_TEND 0x04 /* Transmit End */ |
---|
| 1347 | #define SH7750_SCSSR1_MPB 0x02 /* Multiprocessor Bit */ |
---|
| 1348 | #define SH7750_SCSSR1_MPBT 0x01 /* Multiprocessor Bit Transfer */ |
---|
| 1349 | |
---|
| 1350 | #define SH7750_SCSSR2_PERN 0xF000 /* Number of Parity Errors */ |
---|
| 1351 | #define SH7750_SCSSR2_PERN_S 12 |
---|
| 1352 | #define SH7750_SCSSR2_FERN 0x0F00 /* Number of Framing Errors */ |
---|
| 1353 | #define SH7750_SCSSR2_FERN_S 8 |
---|
| 1354 | #define SH7750_SCSSR2_ER 0x0080 /* Receive Error */ |
---|
| 1355 | #define SH7750_SCSSR2_TEND 0x0040 /* Transmit End */ |
---|
| 1356 | #define SH7750_SCSSR2_TDFE 0x0020 /* Transmit FIFO Data Empty */ |
---|
| 1357 | #define SH7750_SCSSR2_BRK 0x0010 /* Break Detect */ |
---|
| 1358 | #define SH7750_SCSSR2_FER 0x0008 /* Framing Error */ |
---|
| 1359 | #define SH7750_SCSSR2_PER 0x0004 /* Parity Error */ |
---|
| 1360 | #define SH7750_SCSSR2_RDF 0x0002 /* Receive FIFO Data Full */ |
---|
| 1361 | #define SH7750_SCSSR2_DR 0x0001 /* Receive Data Ready */ |
---|
| 1362 | |
---|
| 1363 | /* SCI Serial Port Register - SCSPTR1(byte) */ |
---|
| 1364 | #define SH7750_SCSPTR1_REGOFS 0xE0001C /* offset */ |
---|
| 1365 | #define SH7750_SCSPTR1 SH7750_P4_REG32(SH7750_SCSPTR1_REGOFS) |
---|
| 1366 | #define SH7750_SCSPTR1_A7 SH7750_A7_REG32(SH7750_SCSPTR1_REGOFS) |
---|
| 1367 | |
---|
| 1368 | #define SH7750_SCSPTR1_EIO 0x80 /* Error Interrupt Only */ |
---|
| 1369 | #define SH7750_SCSPTR1_SPB1IO 0x08 /* 1: Output SPB1DT bit to SCK pin */ |
---|
| 1370 | #define SH7750_SCSPTR1_SPB1DT 0x04 /* Serial Port Clock Port Data */ |
---|
| 1371 | #define SH7750_SCSPTR1_SPB0IO 0x02 /* 1: Output SPB0DT bit to TxD pin */ |
---|
| 1372 | #define SH7750_SCSPTR1_SPB0DT 0x01 /* Serial Port Break Data */ |
---|
| 1373 | |
---|
| 1374 | /* SCIF Serial Port Register - SCSPTR2(half) */ |
---|
| 1375 | #define SH7750_SCSPTR2_REGOFS 0xE80020 /* offset */ |
---|
| 1376 | #define SH7750_SCSPTR2 SH7750_P4_REG32(SH7750_SCSPTR2_REGOFS) |
---|
| 1377 | #define SH7750_SCSPTR2_A7 SH7750_A7_REG32(SH7750_SCSPTR2_REGOFS) |
---|
| 1378 | |
---|
| 1379 | #define SH7750_SCSPTR2_RTSIO 0x80 /* 1: Output RTSDT bit to RTS2\ pin */ |
---|
| 1380 | #define SH7750_SCSPTR2_RTSDT 0x40 /* RTS Port Data */ |
---|
| 1381 | #define SH7750_SCSPTR2_CTSIO 0x20 /* 1: Output CTSDT bit to CTS2\ pin */ |
---|
| 1382 | #define SH7750_SCSPTR2_CTSDT 0x10 /* CTS Port Data */ |
---|
| 1383 | #define SH7750_SCSPTR2_SPB2IO 0x02 /* 1: Output SPBDT bit to TxD2 pin */ |
---|
| 1384 | #define SH7750_SCSPTR2_SPB2DT 0x01 /* Serial Port Break Data */ |
---|
| 1385 | |
---|
| 1386 | /* SCI Bit Rate Register - SCBRR1(byte), SCBRR2(byte) */ |
---|
| 1387 | #define SH7750_SCBRR_REGOFS(n) ((n) == 1 ? 0xE00004 : 0xE80004) /* offset */ |
---|
| 1388 | #define SH7750_SCBRR(n) SH7750_P4_REG32(SH7750_SCBRR_REGOFS(n)) |
---|
| 1389 | #define SH7750_SCBRR1 SH7750_SCBRR(1) |
---|
| 1390 | #define SH7750_SCBRR2 SH7750_SCBRR(2) |
---|
| 1391 | #define SH7750_SCBRR_A7(n) SH7750_A7_REG32(SH7750_SCBRR_REGOFS(n)) |
---|
| 1392 | #define SH7750_SCBRR1_A7 SH7750_SCBRR(1) |
---|
| 1393 | #define SH7750_SCBRR2_A7 SH7750_SCBRR(2) |
---|
| 1394 | |
---|
| 1395 | /* SCIF FIFO Control Register - SCFCR2(half) */ |
---|
| 1396 | #define SH7750_SCFCR2_REGOFS 0xE80018 /* offset */ |
---|
| 1397 | #define SH7750_SCFCR2 SH7750_P4_REG32(SH7750_SCFCR2_REGOFS) |
---|
| 1398 | #define SH7750_SCFCR2_A7 SH7750_A7_REG32(SH7750_SCFCR2_REGOFS) |
---|
| 1399 | |
---|
| 1400 | #define SH7750_SCFCR2_RSTRG 0x700 /* RTS2\ Output Active Trigger; RTS2\ |
---|
| 1401 | signal goes to high level when the |
---|
| 1402 | number of received data stored in |
---|
| 1403 | FIFO exceeds the trigger number */ |
---|
| 1404 | #define SH7750_SCFCR2_RSTRG_15 0x000 /* 15 bytes */ |
---|
| 1405 | #define SH7750_SCFCR2_RSTRG_1 0x000 /* 1 byte */ |
---|
| 1406 | #define SH7750_SCFCR2_RSTRG_4 0x000 /* 4 bytes */ |
---|
| 1407 | #define SH7750_SCFCR2_RSTRG_6 0x000 /* 6 bytes */ |
---|
| 1408 | #define SH7750_SCFCR2_RSTRG_8 0x000 /* 8 bytes */ |
---|
| 1409 | #define SH7750_SCFCR2_RSTRG_10 0x000 /* 10 bytes */ |
---|
| 1410 | #define SH7750_SCFCR2_RSTRG_14 0x000 /* 14 bytes */ |
---|
| 1411 | |
---|
| 1412 | #define SH7750_SCFCR2_RTRG 0x0C0 /* Receive FIFO Data Number Trigger, |
---|
| 1413 | Receive Data Full (RDF) Flag sets |
---|
| 1414 | when number of receive data bytes is |
---|
| 1415 | equal or greater than the trigger |
---|
| 1416 | number */ |
---|
| 1417 | #define SH7750_SCFCR2_RTRG_1 0x000 /* 1 byte */ |
---|
| 1418 | #define SH7750_SCFCR2_RTRG_4 0x040 /* 4 bytes */ |
---|
| 1419 | #define SH7750_SCFCR2_RTRG_8 0x080 /* 8 bytes */ |
---|
| 1420 | #define SH7750_SCFCR2_RTRG_14 0x0C0 /* 14 bytes */ |
---|
| 1421 | |
---|
| 1422 | #define SH7750_SCFCR2_TTRG 0x030 /* Transmit FIFO Data Number Trigger, |
---|
| 1423 | Transmit FIFO Data Register Empty (TDFE) |
---|
| 1424 | flag sets when the number of remaining |
---|
| 1425 | transmit data bytes is equal or less |
---|
| 1426 | than the trigger number */ |
---|
| 1427 | #define SH7750_SCFCR2_TTRG_8 0x000 /* 8 bytes */ |
---|
| 1428 | #define SH7750_SCFCR2_TTRG_4 0x010 /* 4 bytes */ |
---|
| 1429 | #define SH7750_SCFCR2_TTRG_2 0x020 /* 2 bytes */ |
---|
| 1430 | #define SH7750_SCFCR2_TTRG_1 0x030 /* 1 byte */ |
---|
| 1431 | |
---|
| 1432 | #define SH7750_SCFCR2_MCE 0x008 /* Modem Control Enable */ |
---|
| 1433 | #define SH7750_SCFCR2_TFRST 0x004 /* Transmit FIFO Data Register Reset, |
---|
| 1434 | invalidates the transmit data in the |
---|
| 1435 | transmit FIFO */ |
---|
| 1436 | #define SH7750_SCFCR2_RFRST 0x002 /* Receive FIFO Data Register Reset, |
---|
| 1437 | invalidates the receive data in the |
---|
| 1438 | receive FIFO data register and resets |
---|
| 1439 | it to the empty state */ |
---|
| 1440 | #define SH7750_SCFCR2_LOOP 0x001 /* Loopback Test */ |
---|
| 1441 | |
---|
| 1442 | /* SCIF FIFO Data Count Register - SCFDR2(half, read-only) */ |
---|
| 1443 | #define SH7750_SCFDR2_REGOFS 0xE8001C /* offset */ |
---|
| 1444 | #define SH7750_SCFDR2 SH7750_P4_REG32(SH7750_SCFDR2_REGOFS) |
---|
| 1445 | #define SH7750_SCFDR2_A7 SH7750_A7_REG32(SH7750_SCFDR2_REGOFS) |
---|
| 1446 | |
---|
| 1447 | #define SH7750_SCFDR2_T 0x1F00 /* Number of untransmitted data bytes |
---|
| 1448 | in transmit FIFO */ |
---|
| 1449 | #define SH7750_SCFDR2_T_S 8 |
---|
| 1450 | #define SH7750_SCFDR2_R 0x001F /* Number of received data bytes in |
---|
| 1451 | receive FIFO */ |
---|
| 1452 | #define SH7750_SCFDR2_R_S 0 |
---|
| 1453 | |
---|
| 1454 | /* SCIF Line Status Register - SCLSR2(half, read-only) */ |
---|
| 1455 | #define SH7750_SCLSR2_REGOFS 0xE80024 /* offset */ |
---|
| 1456 | #define SH7750_SCLSR2 SH7750_P4_REG32(SH7750_SCLSR2_REGOFS) |
---|
| 1457 | #define SH7750_SCLSR2_A7 SH7750_A7_REG32(SH7750_SCLSR2_REGOFS) |
---|
| 1458 | |
---|
| 1459 | #define SH7750_SCLSR2_ORER 0x0001 /* Overrun Error */ |
---|
| 1460 | |
---|
| 1461 | /* |
---|
| 1462 | * SCI-based Smart Card Interface |
---|
| 1463 | */ |
---|
| 1464 | /* Smart Card Mode Register - SCSCMR1(byte) */ |
---|
| 1465 | #define SH7750_SCSCMR1_REGOFS 0xE00018 /* offset */ |
---|
| 1466 | #define SH7750_SCSCMR1 SH7750_P4_REG32(SH7750_SCSCMR1_REGOFS) |
---|
| 1467 | #define SH7750_SCSCMR1_A7 SH7750_A7_REG32(SH7750_SCSCMR1_REGOFS) |
---|
| 1468 | |
---|
| 1469 | #define SH7750_SCSCMR1_SDIR 0x08 /* Smart Card Data Transfer Direction: */ |
---|
| 1470 | #define SH7750_SCSCMR1_SDIR_LSBF 0x00 /* LSB-first */ |
---|
| 1471 | #define SH7750_SCSCMR1_SDIR_MSBF 0x08 /* MSB-first */ |
---|
| 1472 | |
---|
| 1473 | #define SH7750_SCSCMR1_SINV 0x04 /* Smart Card Data Inversion */ |
---|
| 1474 | #define SH7750_SCSCMR1_SMIF 0x01 /* Smart Card Interface Mode Select */ |
---|
| 1475 | |
---|
| 1476 | /* Smart-card specific bits in other registers */ |
---|
| 1477 | /* SCSMR1: */ |
---|
| 1478 | #define SH7750_SCSMR1_GSM 0x80 /* GSM mode select */ |
---|
| 1479 | |
---|
| 1480 | /* SCSSR1: */ |
---|
| 1481 | #define SH7750_SCSSR1_ERS 0x10 /* Error Signal Status */ |
---|
| 1482 | |
---|
| 1483 | /* |
---|
| 1484 | * I/O Ports |
---|
| 1485 | */ |
---|
| 1486 | /* Port Control Register A - PCTRA */ |
---|
| 1487 | #define SH7750_PCTRA_REGOFS 0x80002C /* offset */ |
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| 1488 | #define SH7750_PCTRA SH7750_P4_REG32(SH7750_PCTRA_REGOFS) |
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| 1489 | #define SH7750_PCTRA_A7 SH7750_A7_REG32(SH7750_PCTRA_REGOFS) |
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| 1490 | |
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| 1491 | #define SH7750_PCTRA_PBPUP(n) 0 /* Bit n is pulled up */ |
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| 1492 | #define SH7750_PCTRA_PBNPUP(n) (1 << ((n)*2+1)) /* Bit n is not pulled up */ |
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| 1493 | #define SH7750_PCTRA_PBINP(n) 0 /* Bit n is an input */ |
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| 1494 | #define SH7750_PCTRA_PBOUT(n) (1 << ((n)*2)) /* Bit n is an output */ |
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| 1495 | |
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| 1496 | /* Port Data Register A - PDTRA(half) */ |
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| 1497 | #define SH7750_PDTRA_REGOFS 0x800030 /* offset */ |
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| 1498 | #define SH7750_PDTRA SH7750_P4_REG32(SH7750_PDTRA_REGOFS) |
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| 1499 | #define SH7750_PDTRA_A7 SH7750_A7_REG32(SH7750_PDTRA_REGOFS) |
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| 1500 | |
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| 1501 | #define SH7750_PDTRA_BIT(n) (1 << (n)) |
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| 1502 | |
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| 1503 | /* Port Control Register B - PCTRB */ |
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| 1504 | #define SH7750_PCTRB_REGOFS 0x800040 /* offset */ |
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| 1505 | #define SH7750_PCTRB SH7750_P4_REG32(SH7750_PCTRB_REGOFS) |
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| 1506 | #define SH7750_PCTRB_A7 SH7750_A7_REG32(SH7750_PCTRB_REGOFS) |
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| 1507 | |
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| 1508 | #define SH7750_PCTRB_PBPUP(n) 0 /* Bit n is pulled up */ |
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| 1509 | #define SH7750_PCTRB_PBNPUP(n) (1 << ((n-16)*2+1)) /* Bit n is not pulled up */ |
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| 1510 | #define SH7750_PCTRB_PBINP(n) 0 /* Bit n is an input */ |
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| 1511 | #define SH7750_PCTRB_PBOUT(n) (1 << ((n-16)*2)) /* Bit n is an output */ |
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| 1512 | |
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| 1513 | /* Port Data Register B - PDTRB(half) */ |
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| 1514 | #define SH7750_PDTRB_REGOFS 0x800044 /* offset */ |
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| 1515 | #define SH7750_PDTRB SH7750_P4_REG32(SH7750_PDTRB_REGOFS) |
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| 1516 | #define SH7750_PDTRB_A7 SH7750_A7_REG32(SH7750_PDTRB_REGOFS) |
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| 1517 | |
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| 1518 | #define SH7750_PDTRB_BIT(n) (1 << ((n)-16)) |
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| 1519 | |
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| 1520 | /* GPIO Interrupt Control Register - GPIOIC(half) */ |
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| 1521 | #define SH7750_GPIOIC_REGOFS 0x800048 /* offset */ |
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| 1522 | #define SH7750_GPIOIC SH7750_P4_REG32(SH7750_GPIOIC_REGOFS) |
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| 1523 | #define SH7750_GPIOIC_A7 SH7750_A7_REG32(SH7750_GPIOIC_REGOFS) |
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| 1524 | |
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| 1525 | #define SH7750_GPIOIC_PTIREN(n) (1 << (n)) /* Port n is used as a GPIO int */ |
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| 1526 | |
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| 1527 | /* |
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| 1528 | * Interrupt Controller - INTC |
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| 1529 | */ |
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| 1530 | /* Interrupt Control Register - ICR (half) */ |
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| 1531 | #define SH7750_ICR_REGOFS 0xD00000 /* offset */ |
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| 1532 | #define SH7750_ICR SH7750_P4_REG32(SH7750_ICR_REGOFS) |
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| 1533 | #define SH7750_ICR_A7 SH7750_A7_REG32(SH7750_ICR_REGOFS) |
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| 1534 | |
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| 1535 | #define SH7750_ICR_NMIL 0x8000 /* NMI Input Level */ |
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| 1536 | #define SH7750_ICR_MAI 0x4000 /* NMI Interrupt Mask */ |
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| 1537 | |
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| 1538 | #define SH7750_ICR_NMIB 0x0200 /* NMI Block Mode: */ |
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| 1539 | #define SH7750_ICR_NMIB_BLK 0x0000 /* NMI requests held pending while |
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| 1540 | SR.BL bit is set to 1 */ |
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| 1541 | #define SH7750_ICR_NMIB_NBLK 0x0200 /* NMI requests detected when SR.BL bit |
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| 1542 | set to 1 */ |
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| 1543 | |
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| 1544 | #define SH7750_ICR_NMIE 0x0100 /* NMI Edge Select: */ |
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| 1545 | #define SH7750_ICR_NMIE_FALL 0x0000 /* Interrupt request detected on falling |
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| 1546 | edge of NMI input */ |
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| 1547 | #define SH7750_ICR_NMIE_RISE 0x0100 /* Interrupt request detected on rising |
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| 1548 | edge of NMI input */ |
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| 1549 | |
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| 1550 | #define SH7750_ICR_IRLM 0x0080 /* IRL Pin Mode: */ |
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| 1551 | #define SH7750_ICR_IRLM_ENC 0x0000 /* IRL\ pins used as a level-encoded |
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| 1552 | interrupt requests */ |
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| 1553 | #define SH7750_ICR_IRLM_RAW 0x0080 /* IRL\ pins used as a four independent |
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| 1554 | interrupt requests */ |
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| 1555 | |
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| 1556 | /* Interrupt Priority Register A - IPRA (half) */ |
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| 1557 | #define SH7750_IPRA_REGOFS 0xD00004 /* offset */ |
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| 1558 | #define SH7750_IPRA SH7750_P4_REG32(SH7750_IPRA_REGOFS) |
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| 1559 | #define SH7750_IPRA_A7 SH7750_A7_REG32(SH7750_IPRA_REGOFS) |
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| 1560 | |
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| 1561 | #define SH7750_IPRA_TMU0 0xF000 /* TMU0 interrupt priority */ |
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| 1562 | #define SH7750_IPRA_TMU0_S 12 |
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| 1563 | #define SH7750_IPRA_TMU1 0x0F00 /* TMU1 interrupt priority */ |
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| 1564 | #define SH7750_IPRA_TMU1_S 8 |
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| 1565 | #define SH7750_IPRA_TMU2 0x00F0 /* TMU2 interrupt priority */ |
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| 1566 | #define SH7750_IPRA_TMU2_S 4 |
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| 1567 | #define SH7750_IPRA_RTC 0x000F /* RTC interrupt priority */ |
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| 1568 | #define SH7750_IPRA_RTC_S 0 |
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| 1569 | |
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| 1570 | /* Interrupt Priority Register B - IPRB (half) */ |
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| 1571 | #define SH7750_IPRB_REGOFS 0xD00008 /* offset */ |
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| 1572 | #define SH7750_IPRB SH7750_P4_REG32(SH7750_IPRB_REGOFS) |
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| 1573 | #define SH7750_IPRB_A7 SH7750_A7_REG32(SH7750_IPRB_REGOFS) |
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| 1574 | |
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| 1575 | #define SH7750_IPRB_WDT 0xF000 /* WDT interrupt priority */ |
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| 1576 | #define SH7750_IPRB_WDT_S 12 |
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| 1577 | #define SH7750_IPRB_REF 0x0F00 /* Memory Refresh unit interrupt |
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| 1578 | priority */ |
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| 1579 | #define SH7750_IPRB_REF_S 8 |
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| 1580 | #define SH7750_IPRB_SCI1 0x00F0 /* SCI1 interrupt priority */ |
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| 1581 | #define SH7750_IPRB_SCI1_S 4 |
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| 1582 | |
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| 1583 | /* Interrupt Priority Register ó - IPRó (half) */ |
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| 1584 | #define SH7750_IPRC_REGOFS 0xD00004 /* offset */ |
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| 1585 | #define SH7750_IPRC SH7750_P4_REG32(SH7750_IPRC_REGOFS) |
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| 1586 | #define SH7750_IPRC_A7 SH7750_A7_REG32(SH7750_IPRC_REGOFS) |
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| 1587 | |
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| 1588 | #define SH7750_IPRC_GPIO 0xF000 /* GPIO interrupt priority */ |
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| 1589 | #define SH7750_IPRC_GPIO_S 12 |
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| 1590 | #define SH7750_IPRC_DMAC 0x0F00 /* DMAC interrupt priority */ |
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| 1591 | #define SH7750_IPRC_DMAC_S 8 |
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| 1592 | #define SH7750_IPRC_SCIF 0x00F0 /* SCIF interrupt priority */ |
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| 1593 | #define SH7750_IPRC_SCIF_S 4 |
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| 1594 | #define SH7750_IPRC_HUDI 0x000F /* H-UDI interrupt priority */ |
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| 1595 | #define SH7750_IPRC_HUDI_S 0 |
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| 1596 | |
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| 1597 | |
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| 1598 | /* |
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| 1599 | * User Break Controller registers |
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| 1600 | */ |
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| 1601 | #define SH7750_BARA 0x200000 /* Break address regiser A */ |
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| 1602 | #define SH7750_BAMRA 0x200004 /* Break address mask regiser A */ |
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| 1603 | #define SH7750_BBRA 0x200008 /* Break bus cycle regiser A */ |
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| 1604 | #define SH7750_BARB 0x20000c /* Break address regiser B */ |
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| 1605 | #define SH7750_BAMRB 0x200010 /* Break address mask regiser B */ |
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| 1606 | #define SH7750_BBRB 0x200014 /* Break bus cycle regiser B */ |
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| 1607 | #define SH7750_BASRB 0x000018 /* Break ASID regiser B */ |
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| 1608 | #define SH7750_BDRB 0x200018 /* Break data regiser B */ |
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| 1609 | #define SH7750_BDMRB 0x20001c /* Break data mask regiser B */ |
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| 1610 | #define SH7750_BRCR 0x200020 /* Break control register */ |
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| 1611 | |
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| 1612 | #define SH7750_BRCR_UDBE 0x0001 /* User break debug enable bit */ |
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| 1613 | |
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| 1614 | #endif |
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