1 | /* |
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2 | * This file contains the generic RTEMS clock driver the Hitachi SH 7750 |
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3 | * |
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4 | * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia |
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5 | * Author: Victor V. Vengerov <vvv@oktet.ru> |
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6 | * |
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7 | * COPYRIGHT (c) 2001 |
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8 | * On-Line Applications Research Corporation (OAR). |
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9 | * Copyright assigned to U.S. Government, 1994. |
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10 | * |
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11 | * The license and distribution terms for this file may be |
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12 | * found in the file LICENSE in this distribution or at |
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13 | * http://www.OARcorp.com/rtems/license.html. |
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14 | * |
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15 | * $Id$ |
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16 | */ |
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17 | |
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18 | #include <rtems.h> |
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19 | |
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20 | #include <stdlib.h> |
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21 | |
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22 | #include <rtems/libio.h> |
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23 | #include <rtems/score/sh_io.h> |
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24 | #include <rtems/score/sh.h> |
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25 | #include <rtems/score/ispsh7750.h> |
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26 | #include <rtems/score/iosh7750.h> |
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27 | |
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28 | #ifndef CLOCKPRIO |
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29 | #define CLOCKPRIO 10 |
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30 | #endif |
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31 | |
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32 | /* Clock timer prescaler division ratio */ |
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33 | #define CLOCK_PRESCALER 4 |
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34 | #define TCR0_TPSC SH7750_TCR_TPSC_DIV4 |
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35 | |
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36 | /* |
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37 | * The interrupt vector number associated with the clock tick device |
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38 | * driver. |
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39 | */ |
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40 | |
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41 | #define CLOCK_VECTOR SH7750_EVT_TO_NUM(SH7750_EVT_TUNI0) |
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42 | |
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43 | /* |
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44 | * Clock_driver_ticks is a monotonically increasing counter of the |
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45 | * number of clock ticks since the driver was initialized. |
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46 | */ |
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47 | |
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48 | volatile rtems_unsigned32 Clock_driver_ticks; |
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49 | |
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50 | static void Clock_exit( void ); |
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51 | static rtems_isr Clock_isr( rtems_vector_number vector ); |
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52 | |
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53 | /* |
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54 | * These are set by clock driver during its init |
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55 | */ |
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56 | rtems_device_major_number rtems_clock_major = ~0; |
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57 | rtems_device_minor_number rtems_clock_minor; |
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58 | |
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59 | /* |
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60 | * The previous ISR on this clock tick interrupt vector. |
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61 | */ |
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62 | |
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63 | rtems_isr_entry Old_ticker; |
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64 | |
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65 | /* |
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66 | * Isr Handler |
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67 | */ |
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68 | |
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69 | /* Clock_isr -- |
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70 | * Clock interrupt handling routine. |
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71 | * |
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72 | * PARAMETERS: |
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73 | * vector - interrupt vector number |
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74 | * |
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75 | * RETURNS: |
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76 | * none |
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77 | */ |
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78 | rtems_isr |
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79 | Clock_isr(rtems_vector_number vector) |
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80 | { |
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81 | unsigned16 tcr; |
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82 | |
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83 | /* reset the timer underflow flag */ |
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84 | tcr = read16(SH7750_TCR0); |
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85 | write16(tcr & ~SH7750_TCR_UNF, SH7750_TCR0); |
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86 | |
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87 | /* Increment the clock interrupt counter */ |
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88 | Clock_driver_ticks++ ; |
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89 | |
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90 | /* Invoke rtems clock service routine */ |
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91 | rtems_clock_tick(); |
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92 | } |
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93 | |
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94 | /* Install_clock -- |
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95 | * Install a clock tick handler and reprograms the chip. This |
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96 | * is used to initially establish the clock tick. |
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97 | * |
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98 | * PARAMETERS: |
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99 | * clock_isr - Clock interrupt stay routine |
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100 | * |
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101 | * RETURNS: |
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102 | * none |
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103 | * |
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104 | * SIDE EFFECTS: |
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105 | * Establish clock interrupt handler, configure Timer 0 hardware |
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106 | */ |
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107 | void |
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108 | Install_clock(rtems_isr_entry clock_isr) |
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109 | { |
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110 | int cpudiv = 1; /* CPU frequency divider */ |
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111 | int tidiv = 1; /* Timer input frequency divider */ |
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112 | unsigned32 timer_divider; /* Calculated Timer Divider value */ |
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113 | unsigned8 temp8; |
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114 | unsigned16 temp16; |
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115 | |
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116 | /* |
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117 | * Initialize the clock tick device driver variables |
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118 | */ |
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119 | |
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120 | Clock_driver_ticks = 0; |
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121 | |
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122 | /* Get CPU frequency divider from clock unit */ |
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123 | switch (read16(SH7750_FRQCR) & SH7750_FRQCR_IFC) |
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124 | { |
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125 | case SH7750_FRQCR_IFCDIV1: |
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126 | cpudiv = 1; |
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127 | break; |
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128 | |
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129 | case SH7750_FRQCR_IFCDIV2: |
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130 | cpudiv = 2; |
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131 | break; |
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132 | |
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133 | case SH7750_FRQCR_IFCDIV3: |
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134 | cpudiv = 3; |
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135 | break; |
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136 | |
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137 | case SH7750_FRQCR_IFCDIV4: |
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138 | cpudiv = 4; |
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139 | break; |
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140 | |
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141 | case SH7750_FRQCR_IFCDIV6: |
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142 | cpudiv = 6; |
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143 | break; |
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144 | |
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145 | case SH7750_FRQCR_IFCDIV8: |
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146 | cpudiv = 8; |
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147 | break; |
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148 | |
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149 | default: |
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150 | rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); |
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151 | } |
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152 | |
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153 | /* Get peripheral module frequency divider from clock unit */ |
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154 | switch (read16(SH7750_FRQCR) & SH7750_FRQCR_PFC) |
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155 | { |
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156 | case SH7750_FRQCR_PFCDIV2: |
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157 | tidiv = 2 * CLOCK_PRESCALER; |
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158 | break; |
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159 | |
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160 | case SH7750_FRQCR_PFCDIV3: |
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161 | tidiv = 3 * CLOCK_PRESCALER; |
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162 | break; |
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163 | |
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164 | case SH7750_FRQCR_PFCDIV4: |
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165 | tidiv = 4 * CLOCK_PRESCALER; |
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166 | break; |
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167 | |
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168 | case SH7750_FRQCR_PFCDIV6: |
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169 | tidiv = 6 * CLOCK_PRESCALER; |
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170 | break; |
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171 | |
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172 | case SH7750_FRQCR_PFCDIV8: |
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173 | tidiv = 8 * CLOCK_PRESCALER; |
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174 | break; |
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175 | |
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176 | default: |
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177 | rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); |
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178 | } |
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179 | timer_divider = |
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180 | (rtems_cpu_configuration_get_clicks_per_second() * |
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181 | cpudiv / (tidiv*1000000)) * |
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182 | rtems_configuration_get_microseconds_per_tick(); |
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183 | |
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184 | /* |
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185 | * Hardware specific initialization |
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186 | */ |
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187 | |
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188 | /* Stop the Timer 0 */ |
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189 | temp8 = read8(SH7750_TSTR); |
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190 | temp8 &= ~SH7750_TSTR_STR0; |
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191 | write8(temp8, SH7750_TSTR); |
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192 | |
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193 | /* Establish interrupt handler */ |
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194 | rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker ); |
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195 | |
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196 | /* Reset counter */ |
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197 | write32(timer_divider, SH7750_TCNT0); |
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198 | |
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199 | /* Load divider */ |
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200 | write32(timer_divider, SH7750_TCOR0); |
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201 | |
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202 | write16( |
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203 | SH7750_TCR_UNIE | /* Enable Underflow Interrupt */ |
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204 | SH7750_TCR_CKEG_RAISE | /* Count on rising edge */ |
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205 | TCR0_TPSC, /* Timer prescaler ratio */ |
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206 | SH7750_TCR0); |
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207 | |
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208 | /* Set clock interrupt priority */ |
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209 | temp16 = read16(SH7750_IPRA); |
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210 | temp16 = (temp16 & ~SH7750_IPRA_TMU0) | (CLOCKPRIO << SH7750_IPRA_TMU0_S); |
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211 | write16(temp16, SH7750_IPRA); |
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212 | |
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213 | /* Start the Timer 0 */ |
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214 | temp8 = read8(SH7750_TSTR); |
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215 | temp8 |= SH7750_TSTR_STR0; |
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216 | write8(temp8, SH7750_TSTR); |
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217 | |
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218 | /* |
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219 | * Schedule the clock cleanup routine to execute if the application exits. |
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220 | */ |
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221 | |
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222 | atexit( Clock_exit ); |
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223 | } |
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224 | |
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225 | /* Clock_exit -- |
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226 | * Clean up before the application exits |
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227 | * |
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228 | * PARAMETERS: |
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229 | * none |
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230 | * |
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231 | * RETURNS: |
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232 | * none |
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233 | * |
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234 | * SIDE EFFECTS: |
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235 | * Stop Timer 0 counting, set timer 0 interrupt priority level to 0. |
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236 | */ |
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237 | void |
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238 | Clock_exit(void) |
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239 | { |
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240 | unsigned8 temp8 = 0; |
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241 | unsigned16 temp16 = 0; |
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242 | |
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243 | /* turn off the timer interrupts */ |
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244 | /* Stop the Timer 0 */ |
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245 | temp8 = read8(SH7750_TSTR); |
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246 | temp8 &= ~SH7750_TSTR_STR0; |
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247 | write8(temp8, SH7750_TSTR); |
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248 | |
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249 | /* Lower timer interrupt priority to 0 */ |
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250 | temp16 = read16(SH7750_IPRA); |
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251 | temp16 = (temp16 & ~SH7750_IPRA_TMU0) | (0 << SH7750_IPRA_TMU0_S); |
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252 | write16(temp16, SH7750_IPRA); |
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253 | |
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254 | /* old vector shall not be installed */ |
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255 | } |
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256 | |
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257 | /* Clock_initialize -- |
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258 | * Device driver entry point for clock tick driver initialization. |
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259 | * |
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260 | * PARAMETERS: |
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261 | * major - clock major device number |
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262 | * minor - clock minor device number |
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263 | * pargp - driver initialize primitive argument, not used |
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264 | * |
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265 | * RETURNS: |
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266 | * RTEMS_SUCCESSFUL |
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267 | */ |
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268 | rtems_device_driver |
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269 | Clock_initialize(rtems_device_major_number major, |
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270 | rtems_device_minor_number minor, |
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271 | void *pargp) |
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272 | { |
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273 | Install_clock( Clock_isr ); |
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274 | |
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275 | /* |
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276 | * make major/minor avail to others such as shared memory driver |
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277 | */ |
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278 | rtems_clock_major = major; |
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279 | rtems_clock_minor = minor; |
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280 | |
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281 | return RTEMS_SUCCESSFUL; |
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282 | } |
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283 | |
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284 | /* Clock_control -- |
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285 | * Device driver entry point for clock driver IOCTL functions. |
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286 | * |
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287 | * PARAMETERS: |
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288 | * major - clock major device number |
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289 | * minor - clock minor device number |
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290 | * pargp - driver ioctl primitive argument, not used |
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291 | * |
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292 | * RETURNS: |
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293 | * RTEMS_SUCCESSFUL |
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294 | */ |
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295 | rtems_device_driver |
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296 | Clock_control(rtems_device_major_number major, |
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297 | rtems_device_minor_number minor, |
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298 | void *pargp) |
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299 | { |
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300 | rtems_unsigned32 isrlevel; |
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301 | rtems_libio_ioctl_args_t *args = pargp; |
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302 | |
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303 | if (args != 0) |
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304 | { |
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305 | /* |
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306 | * This is hokey, but until we get a defined interface |
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307 | * to do this, it will just be this simple... |
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308 | */ |
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309 | |
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310 | if (args->command == rtems_build_name('I', 'S', 'R', ' ')) |
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311 | { |
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312 | Clock_isr(CLOCK_VECTOR); |
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313 | } |
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314 | else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) |
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315 | { |
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316 | rtems_isr_entry ignored ; |
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317 | rtems_interrupt_disable( isrlevel ); |
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318 | rtems_interrupt_catch( args->buffer, CLOCK_VECTOR, &ignored ); |
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319 | |
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320 | rtems_interrupt_enable( isrlevel ); |
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321 | } |
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322 | } |
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323 | return RTEMS_SUCCESSFUL; |
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324 | } |
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