[ba71076] | 1 | /* |
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| 2 | * This file contains the generic RTEMS clock driver the Hitachi SH 7750 |
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| 3 | * |
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| 4 | * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia |
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| 5 | * Author: Victor V. Vengerov <vvv@oktet.ru> |
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| 6 | * |
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| 7 | * COPYRIGHT (c) 2001 |
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| 8 | * On-Line Applications Research Corporation (OAR). |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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| 12 | * http://www.OARcorp.com/rtems/license.html. |
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| 13 | * |
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| 14 | * $Id$ |
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| 15 | */ |
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| 16 | |
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| 17 | #include <rtems.h> |
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| 18 | |
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| 19 | #include <stdlib.h> |
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| 20 | |
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| 21 | #include <rtems/libio.h> |
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| 22 | #include <rtems/score/sh_io.h> |
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| 23 | #include <rtems/score/sh.h> |
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| 24 | #include <rtems/score/ispsh7750.h> |
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| 25 | #include <rtems/score/iosh7750.h> |
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| 26 | |
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| 27 | #ifndef CLOCKPRIO |
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| 28 | #define CLOCKPRIO 10 |
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| 29 | #endif |
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| 30 | |
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| 31 | /* Clock timer prescaler division ratio */ |
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| 32 | #define CLOCK_PRESCALER 4 |
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| 33 | #define TCR0_TPSC SH7750_TCR_TPSC_DIV4 |
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| 34 | |
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| 35 | /* |
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| 36 | * The interrupt vector number associated with the clock tick device |
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| 37 | * driver. |
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| 38 | */ |
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| 39 | |
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| 40 | #define CLOCK_VECTOR SH7750_EVT_TO_NUM(SH7750_EVT_TUNI0) |
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| 41 | |
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| 42 | /* |
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| 43 | * Clock_driver_ticks is a monotonically increasing counter of the |
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| 44 | * number of clock ticks since the driver was initialized. |
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| 45 | */ |
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| 46 | |
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| 47 | volatile rtems_unsigned32 Clock_driver_ticks; |
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| 48 | |
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| 49 | static void Clock_exit( void ); |
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| 50 | static rtems_isr Clock_isr( rtems_vector_number vector ); |
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| 51 | |
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| 52 | /* |
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| 53 | * These are set by clock driver during its init |
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| 54 | */ |
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| 55 | rtems_device_major_number rtems_clock_major = ~0; |
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| 56 | rtems_device_minor_number rtems_clock_minor; |
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| 57 | |
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| 58 | /* |
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| 59 | * The previous ISR on this clock tick interrupt vector. |
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| 60 | */ |
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| 61 | |
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| 62 | rtems_isr_entry Old_ticker; |
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| 63 | |
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| 64 | /* |
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| 65 | * Isr Handler |
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| 66 | */ |
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| 67 | |
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| 68 | /* Clock_isr -- |
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| 69 | * Clock interrupt handling routine. |
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| 70 | * |
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| 71 | * PARAMETERS: |
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| 72 | * vector - interrupt vector number |
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| 73 | * |
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| 74 | * RETURNS: |
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| 75 | * none |
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| 76 | */ |
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| 77 | rtems_isr |
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| 78 | Clock_isr(rtems_vector_number vector) |
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| 79 | { |
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| 80 | unsigned16 tcr; |
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| 81 | |
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| 82 | /* reset the timer underflow flag */ |
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| 83 | tcr = read16(SH7750_TCR0); |
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| 84 | write16(tcr & ~SH7750_TCR_UNF, SH7750_TCR0); |
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| 85 | |
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| 86 | /* Increment the clock interrupt counter */ |
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| 87 | Clock_driver_ticks++ ; |
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| 88 | |
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| 89 | /* Invoke rtems clock service routine */ |
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| 90 | rtems_clock_tick(); |
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| 91 | } |
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| 92 | |
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| 93 | /* Install_clock -- |
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| 94 | * Install a clock tick handler and reprograms the chip. This |
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| 95 | * is used to initially establish the clock tick. |
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| 96 | * |
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| 97 | * PARAMETERS: |
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| 98 | * clock_isr - Clock interrupt stay routine |
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| 99 | * |
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| 100 | * RETURNS: |
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| 101 | * none |
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| 102 | * |
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| 103 | * SIDE EFFECTS: |
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| 104 | * Establish clock interrupt handler, configure Timer 0 hardware |
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| 105 | */ |
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| 106 | void |
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| 107 | Install_clock(rtems_isr_entry clock_isr) |
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| 108 | { |
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| 109 | int cpudiv = 1; /* CPU frequency divider */ |
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| 110 | int tidiv = 1; /* Timer input frequency divider */ |
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| 111 | unsigned32 timer_divider; /* Calculated Timer Divider value */ |
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| 112 | unsigned8 temp8; |
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| 113 | unsigned16 temp16; |
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| 114 | |
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| 115 | /* |
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| 116 | * Initialize the clock tick device driver variables |
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| 117 | */ |
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| 118 | |
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| 119 | Clock_driver_ticks = 0; |
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| 120 | |
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| 121 | /* Get CPU frequency divider from clock unit */ |
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| 122 | switch (read16(SH7750_FRQCR) & SH7750_FRQCR_IFC) |
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| 123 | { |
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| 124 | case SH7750_FRQCR_IFCDIV1: |
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| 125 | cpudiv = 1; |
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| 126 | break; |
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| 127 | |
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| 128 | case SH7750_FRQCR_IFCDIV2: |
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| 129 | cpudiv = 2; |
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| 130 | break; |
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| 131 | |
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| 132 | case SH7750_FRQCR_IFCDIV3: |
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| 133 | cpudiv = 3; |
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| 134 | break; |
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| 135 | |
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| 136 | case SH7750_FRQCR_IFCDIV4: |
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| 137 | cpudiv = 4; |
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| 138 | break; |
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| 139 | |
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| 140 | case SH7750_FRQCR_IFCDIV6: |
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| 141 | cpudiv = 6; |
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| 142 | break; |
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| 143 | |
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| 144 | case SH7750_FRQCR_IFCDIV8: |
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| 145 | cpudiv = 8; |
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| 146 | break; |
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| 147 | |
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| 148 | default: |
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| 149 | rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); |
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| 150 | } |
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| 151 | |
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| 152 | /* Get peripheral module frequency divider from clock unit */ |
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| 153 | switch (read16(SH7750_FRQCR) & SH7750_FRQCR_PFC) |
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| 154 | { |
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| 155 | case SH7750_FRQCR_PFCDIV2: |
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| 156 | tidiv = 2 * CLOCK_PRESCALER; |
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| 157 | break; |
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| 158 | |
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| 159 | case SH7750_FRQCR_PFCDIV3: |
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| 160 | tidiv = 3 * CLOCK_PRESCALER; |
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| 161 | break; |
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| 162 | |
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| 163 | case SH7750_FRQCR_PFCDIV4: |
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| 164 | tidiv = 4 * CLOCK_PRESCALER; |
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| 165 | break; |
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| 166 | |
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| 167 | case SH7750_FRQCR_PFCDIV6: |
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| 168 | tidiv = 6 * CLOCK_PRESCALER; |
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| 169 | break; |
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| 170 | |
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| 171 | case SH7750_FRQCR_PFCDIV8: |
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| 172 | tidiv = 8 * CLOCK_PRESCALER; |
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| 173 | break; |
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| 174 | |
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| 175 | default: |
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| 176 | rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); |
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| 177 | } |
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| 178 | timer_divider = |
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| 179 | (rtems_cpu_configuration_get_clicks_per_second() * |
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| 180 | cpudiv / (tidiv*1000000)) * |
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| 181 | rtems_configuration_get_microseconds_per_tick(); |
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| 182 | |
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| 183 | /* |
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| 184 | * Hardware specific initialization |
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| 185 | */ |
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| 186 | |
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| 187 | /* Stop the Timer 0 */ |
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| 188 | temp8 = read8(SH7750_TSTR); |
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| 189 | temp8 &= ~SH7750_TSTR_STR0; |
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| 190 | write8(temp8, SH7750_TSTR); |
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| 191 | |
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| 192 | /* Establish interrupt handler */ |
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| 193 | rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker ); |
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| 194 | |
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| 195 | /* Reset counter */ |
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| 196 | write32(timer_divider, SH7750_TCNT0); |
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| 197 | |
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| 198 | /* Load divider */ |
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| 199 | write32(timer_divider, SH7750_TCOR0); |
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| 200 | |
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| 201 | write16( |
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| 202 | SH7750_TCR_UNIE | /* Enable Underflow Interrupt */ |
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| 203 | SH7750_TCR_CKEG_RAISE | /* Count on rising edge */ |
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| 204 | TCR0_TPSC, /* Timer prescaler ratio */ |
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| 205 | SH7750_TCR0); |
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| 206 | |
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| 207 | /* Set clock interrupt priority */ |
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| 208 | temp16 = read16(SH7750_IPRA); |
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| 209 | temp16 = (temp16 & ~SH7750_IPRA_TMU0) | (CLOCKPRIO << SH7750_IPRA_TMU0_S); |
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| 210 | write16(temp16, SH7750_IPRA); |
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| 211 | |
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| 212 | /* Start the Timer 0 */ |
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| 213 | temp8 = read8(SH7750_TSTR); |
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| 214 | temp8 |= SH7750_TSTR_STR0; |
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| 215 | write8(temp8, SH7750_TSTR); |
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| 216 | |
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| 217 | /* |
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| 218 | * Schedule the clock cleanup routine to execute if the application exits. |
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| 219 | */ |
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| 220 | |
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| 221 | atexit( Clock_exit ); |
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| 222 | } |
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| 223 | |
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| 224 | /* Clock_exit -- |
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| 225 | * Clean up before the application exits |
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| 226 | * |
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| 227 | * PARAMETERS: |
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| 228 | * none |
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| 229 | * |
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| 230 | * RETURNS: |
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| 231 | * none |
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| 232 | * |
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| 233 | * SIDE EFFECTS: |
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| 234 | * Stop Timer 0 counting, set timer 0 interrupt priority level to 0. |
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| 235 | */ |
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| 236 | void |
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| 237 | Clock_exit(void) |
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| 238 | { |
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| 239 | unsigned8 temp8 = 0; |
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| 240 | unsigned16 temp16 = 0; |
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| 241 | |
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| 242 | /* turn off the timer interrupts */ |
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| 243 | /* Stop the Timer 0 */ |
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| 244 | temp8 = read8(SH7750_TSTR); |
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| 245 | temp8 &= ~SH7750_TSTR_STR0; |
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| 246 | write8(temp8, SH7750_TSTR); |
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| 247 | |
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| 248 | /* Lower timer interrupt priority to 0 */ |
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| 249 | temp16 = read16(SH7750_IPRA); |
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| 250 | temp16 = (temp16 & ~SH7750_IPRA_TMU0) | (0 << SH7750_IPRA_TMU0_S); |
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| 251 | write16(temp16, SH7750_IPRA); |
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| 252 | |
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| 253 | /* old vector shall not be installed */ |
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| 254 | } |
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| 255 | |
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| 256 | /* Clock_initialize -- |
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| 257 | * Device driver entry point for clock tick driver initialization. |
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| 258 | * |
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| 259 | * PARAMETERS: |
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| 260 | * major - clock major device number |
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| 261 | * minor - clock minor device number |
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| 262 | * pargp - driver initialize primitive argument, not used |
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| 263 | * |
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| 264 | * RETURNS: |
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| 265 | * RTEMS_SUCCESSFUL |
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| 266 | */ |
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| 267 | rtems_device_driver |
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| 268 | Clock_initialize(rtems_device_major_number major, |
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| 269 | rtems_device_minor_number minor, |
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| 270 | void *pargp) |
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| 271 | { |
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| 272 | Install_clock( Clock_isr ); |
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| 273 | |
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| 274 | /* |
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| 275 | * make major/minor avail to others such as shared memory driver |
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| 276 | */ |
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| 277 | rtems_clock_major = major; |
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| 278 | rtems_clock_minor = minor; |
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| 279 | |
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| 280 | return RTEMS_SUCCESSFUL; |
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| 281 | } |
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| 282 | |
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| 283 | /* Clock_control -- |
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| 284 | * Device driver entry point for clock driver IOCTL functions. |
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| 285 | * |
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| 286 | * PARAMETERS: |
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| 287 | * major - clock major device number |
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| 288 | * minor - clock minor device number |
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| 289 | * pargp - driver ioctl primitive argument, not used |
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| 290 | * |
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| 291 | * RETURNS: |
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| 292 | * RTEMS_SUCCESSFUL |
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| 293 | */ |
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| 294 | rtems_device_driver |
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| 295 | Clock_control(rtems_device_major_number major, |
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| 296 | rtems_device_minor_number minor, |
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| 297 | void *pargp) |
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| 298 | { |
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| 299 | rtems_unsigned32 isrlevel; |
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| 300 | rtems_libio_ioctl_args_t *args = pargp; |
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| 301 | |
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| 302 | if (args != 0) |
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| 303 | { |
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| 304 | /* |
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| 305 | * This is hokey, but until we get a defined interface |
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| 306 | * to do this, it will just be this simple... |
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| 307 | */ |
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| 308 | |
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| 309 | if (args->command == rtems_build_name('I', 'S', 'R', ' ')) |
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| 310 | { |
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| 311 | Clock_isr(CLOCK_VECTOR); |
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| 312 | } |
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| 313 | else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) |
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| 314 | { |
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| 315 | rtems_isr_entry ignored ; |
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| 316 | rtems_interrupt_disable( isrlevel ); |
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| 317 | rtems_interrupt_catch( args->buffer, CLOCK_VECTOR, &ignored ); |
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| 318 | |
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| 319 | rtems_interrupt_enable( isrlevel ); |
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| 320 | } |
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| 321 | } |
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| 322 | return RTEMS_SUCCESSFUL; |
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| 323 | } |
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