source: rtems/c/src/lib/libcpu/sh/sh7045/timer/timer.c @ 8fbe2e6

4.11
Last change on this file since 8fbe2e6 was 8fbe2e6, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 4, 2014 at 1:59:49 PM

Use correct prototype of benchmark_timer_read()

This change starts with removing the effectively empty file
timerdrv.h. The prototypes for benchmark_timer_XXX() were in
btimer.h which was not universally used. Thus every use of
timerdrv.h had to be changed to btimer.h. Then the prototypes
for benchmark_timer_read() had to be adjusted to return
benchmark_timer_t rather than int or uint32_t.

I took this opportunity to also correct the file headers to
separate the copyright from the file description comments which
is needed to ensure the copyright isn't propagated into Doxygen
output.

  • Property mode set to 100644
File size: 4.6 KB
Line 
1/**
2 *  @file
3 *  @brief Timer for the Hitachi SH 704X
4 */
5
6/*
7 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
8 *           Bernd Becker (becker@faw.uni-ulm.de)
9 *
10 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
11 *
12 *  This program is distributed in the hope that it will be useful,
13 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
14 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
15 *
16 *  COPYRIGHT (c) 1998.
17 *  On-Line Applications Research Corporation (OAR).
18 *
19 *  The license and distribution terms for this file may be
20 *  found in the file LICENSE in this distribution or at
21 *  http://www.rtems.org/license/LICENSE.
22 */
23
24#include <rtems.h>
25#include <rtems/btimer.h>
26
27#include <rtems/score/sh_io.h>
28#include <rtems/score/iosh7045.h>
29
30extern uint32_t bsp_clicks_per_second;
31
32/*
33 *  We use a Phi/4 timer
34 */
35#define SCALE (Timer_MHZ/4)
36
37#define MTU1_STARTMASK  0xfd
38#define MTU1_SYNCMASK   0xfd
39#define MTU1_MODEMASK   0xc0
40#define MTU1_TCRMASK    0x01
41#define MTU1_TIORMASK   0x88
42#define MTU1_STAT_MASK  0xf8
43#define MTU1_TIERMASK   0xfc
44#define IPRC_MTU1_MASK  0xfff0
45
46#ifndef MTU1_PRIO
47#define MTU1_PRIO 15
48#endif
49
50#define MTU1_VECTOR 86
51
52extern rtems_isr timerisr(void);
53
54static uint32_t   Timer_interrupts;
55
56bool benchmark_timer_find_average_overhead;
57
58static uint32_t   Timer_MHZ ;
59
60void benchmark_timer_initialize( void )
61{
62  uint8_t                temp8;
63  uint16_t               temp16;
64  rtems_interrupt_level  level;
65  rtems_isr             *ignored;
66
67  Timer_MHZ = bsp_clicks_per_second / 1000000 ;
68
69  /*
70   *  Timer has never overflowed.  This may not be necessary on some
71   *  implemenations of timer but ....
72   */
73
74  Timer_interrupts /* .i */ = 0;
75  rtems_interrupt_disable( level );
76
77  /*
78   *  Somehow start the timer
79   */
80  /* stop Timer 1  */
81  temp8 = read8(MTU_TSTR) & MTU1_STARTMASK;
82  write8( temp8, MTU_TSTR );
83
84  /* initialize counter 1 */
85  write16( 0, MTU_TCNT1);
86
87  /* Timer 1 is independent of other timers */
88  temp8 = read8(MTU_TSYR) & MTU1_SYNCMASK;
89  write8( temp8, MTU_TSYR );
90
91  /* Timer 1, normal mode */
92  temp8 = read8(MTU_TMDR1) & MTU1_MODEMASK;
93  write8( temp8, MTU_TMDR1 );
94
95  /* x0000000
96   * |||||+++--- Internal Clock
97   * |||++------ Count on rising edge
98   * |++-------- disable TCNT clear
99   * +---------- don`t care
100   */
101  write8( MTU1_TCRMASK, MTU_TCR1 );
102
103  /* gra and grb are not used */
104  write8( MTU1_TIORMASK, MTU_TIOR1 );
105
106  /* reset all status flags */
107  temp8 = read8(MTU_TSR1) & MTU1_STAT_MASK;
108  write8( temp8, MTU_TSR1 );
109
110  /* enable overflow interrupt */
111  write8( MTU1_TIERMASK, MTU_TIER1 );
112
113  /* set interrupt priority */
114  temp16 = read16(INTC_IPRC) & IPRC_MTU1_MASK;
115  temp16 |= MTU1_PRIO;
116  write16( temp16, INTC_IPRC);
117
118  /* initialize ISR */
119  _CPU_ISR_install_raw_handler( MTU1_VECTOR, timerisr, &ignored );
120  rtems_interrupt_enable( level );
121
122  /* start timer 1 */
123  temp8 = read8(MTU_TSTR) | ~MTU1_STARTMASK;
124  write8( temp8, MTU_TSTR );
125}
126
127/*
128 *  The following controls the behavior of benchmark_timer_read().
129 *
130 *  AVG_OVERHEAD is the overhead for starting and stopping the timer.  It
131 *  is usually deducted from the number returned.
132 *
133 *  LEAST_VALID is the lowest number this routine should trust.  Numbers
134 *  below this are "noise" and zero is returned.
135 */
136
137#define AVG_OVERHEAD      1  /* It typically takes X.X microseconds */
138                             /* (Y countdowns) to start/stop the timer. */
139                             /* This value is in microseconds. */
140#define LEAST_VALID       0 /* 20 */ /* Don't trust a clicks value lower than this */
141
142benchmark_timer_t benchmark_timer_read( void )
143{
144  uint32_t   clicks;
145  uint32_t   total ;
146  /*
147   *  Read the timer and see how many clicks it has been since we started.
148   */
149
150
151  clicks = read16( MTU_TCNT1 );   /* XXX: read some HW here */
152
153  /*
154   *  Total is calculated by taking into account the number of timer overflow
155   *  interrupts since the timer was initialized and clicks since the last
156   *  interrupts.
157   */
158
159  total = clicks + Timer_interrupts * 65536;
160
161  if ( benchmark_timer_find_average_overhead )
162    return total / SCALE;          /* in XXX microsecond units */
163  else
164  {
165    if ( total < LEAST_VALID )
166      return 0;            /* below timer resolution */
167  /*
168   *  Somehow convert total into microseconds
169   */
170    return (total / SCALE - AVG_OVERHEAD) ;
171  }
172}
173
174void benchmark_timer_disable_subtracting_average_overhead(bool find_flag)
175{
176  benchmark_timer_find_average_overhead = find_flag;
177}
178
179/* Timer 1 is used */
180
181#pragma interrupt
182void timerisr( void )
183{
184  uint8_t   temp8;
185
186  /* reset the flags of the status register */
187  temp8 = read8(MTU_TSR1) & MTU1_STAT_MASK;
188  write8( temp8, MTU_TSR1 );
189
190  Timer_interrupts += 1;
191}
Note: See TracBrowser for help on using the repository browser.