1 | /* |
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2 | * timer for the Hitachi SH 704X |
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3 | * |
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4 | * This file manages the benchmark timer used by the RTEMS Timing Test |
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5 | * Suite. Each measured time period is demarcated by calls to |
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6 | * Timer_initialize() and Read_timer(). Read_timer() usually returns |
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7 | * the number of microseconds since Timer_initialize() exitted. |
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8 | * |
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9 | * NOTE: It is important that the timer start/stop overhead be |
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10 | * determined when porting or modifying this code. |
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11 | * |
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12 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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13 | * Bernd Becker (becker@faw.uni-ulm.de) |
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14 | * |
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15 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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16 | * |
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17 | * This program is distributed in the hope that it will be useful, |
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18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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20 | * |
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21 | * COPYRIGHT (c) 1998. |
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22 | * On-Line Applications Research Corporation (OAR). |
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23 | * Copyright assigned to U.S. Government, 1994. |
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24 | * |
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25 | * The license and distribution terms for this file may be |
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26 | * found in the file LICENSE in this distribution or at |
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27 | * http://www.OARcorp.com/rtems/license.html. |
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28 | * |
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29 | * $Id$ |
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30 | */ |
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31 | |
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32 | #include <rtems.h> |
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33 | |
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34 | #include <rtems/score/sh_io.h> |
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35 | #include <rtems/score/iosh7045.h> |
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36 | |
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37 | /* |
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38 | * We use a Phi/4 timer |
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39 | */ |
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40 | #define SCALE (Timer_MHZ/4) |
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41 | |
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42 | #define MTU1_STARTMASK 0xfd |
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43 | #define MTU1_SYNCMASK 0xfd |
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44 | #define MTU1_MODEMASK 0xc0 |
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45 | #define MTU1_TCRMASK 0x01 |
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46 | #define MTU1_TIORMASK 0x88 |
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47 | #define MTU1_STAT_MASK 0xf8 |
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48 | #define MTU1_TIERMASK 0xfc |
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49 | #define IPRC_MTU1_MASK 0xfff0 |
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50 | |
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51 | #ifndef MTU1_PRIO |
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52 | #define MTU1_PRIO 15 |
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53 | #endif |
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54 | |
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55 | #define MTU1_VECTOR 86 |
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56 | |
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57 | rtems_isr timerisr(); |
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58 | |
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59 | static rtems_unsigned32 Timer_interrupts; |
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60 | |
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61 | rtems_boolean Timer_driver_Find_average_overhead; |
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62 | |
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63 | static rtems_unsigned32 Timer_MHZ ; |
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64 | |
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65 | void Timer_initialize( void ) |
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66 | { |
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67 | rtems_unsigned8 temp8; |
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68 | rtems_unsigned16 temp16; |
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69 | rtems_unsigned32 level; |
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70 | rtems_isr *ignored; |
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71 | |
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72 | Timer_MHZ = rtems_cpu_configuration_get_clicks_per_second() / 1000000 ; |
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73 | |
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74 | /* |
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75 | * Timer has never overflowed. This may not be necessary on some |
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76 | * implemenations of timer but .... |
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77 | */ |
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78 | |
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79 | Timer_interrupts /* .i */ = 0; |
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80 | _CPU_ISR_Disable( level); |
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81 | |
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82 | /* |
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83 | * Somehow start the timer |
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84 | */ |
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85 | /* stop Timer 1 */ |
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86 | temp8 = read8( MTU_TSTR) & MTU1_STARTMASK; |
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87 | write8( temp8, MTU_TSTR); |
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88 | |
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89 | /* initialize counter 1 */ |
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90 | write16( 0, MTU_TCNT1); |
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91 | |
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92 | /* Timer 1 is independent of other timers */ |
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93 | temp8 = read8( MTU_TSYR) & MTU1_SYNCMASK; |
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94 | write8( temp8, MTU_TSYR); |
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95 | |
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96 | /* Timer 1, normal mode */ |
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97 | temp8 = read8( MTU_TMDR1) & MTU1_MODEMASK; |
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98 | write8( temp8, MTU_TMDR1); |
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99 | |
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100 | /* x0000000 |
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101 | * |||||+++--- Internal Clock |
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102 | * |||++------ Count on rising edge |
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103 | * |++-------- disable TCNT clear |
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104 | * +---------- don`t care |
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105 | */ |
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106 | write8( MTU1_TCRMASK, MTU_TCR1); |
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107 | |
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108 | /* gra and grb are not used */ |
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109 | write8( MTU1_TIORMASK, MTU_TIOR1); |
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110 | |
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111 | /* reset all status flags */ |
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112 | temp8 = read8( MTU_TSR1) & MTU1_STAT_MASK; |
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113 | write8( temp8, MTU_TSR1); |
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114 | |
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115 | /* enable overflow interrupt */ |
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116 | write8( MTU1_TIERMASK, MTU_TIER1); |
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117 | |
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118 | /* set interrupt priority */ |
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119 | temp16 = read16( INTC_IPRC) & IPRC_MTU1_MASK; |
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120 | temp16 |= MTU1_PRIO; |
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121 | write16( temp16, INTC_IPRC); |
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122 | |
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123 | /* initialize ISR */ |
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124 | _CPU_ISR_install_raw_handler( MTU1_VECTOR, timerisr, &ignored ); |
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125 | _CPU_ISR_Enable( level); |
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126 | |
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127 | /* start timer 1 */ |
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128 | temp8 = read8( MTU_TSTR) | ~MTU1_STARTMASK; |
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129 | write8( temp8, MTU_TSTR); |
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130 | } |
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131 | |
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132 | /* |
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133 | * The following controls the behavior of Read_timer(). |
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134 | * |
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135 | * AVG_OVERHEAD is the overhead for starting and stopping the timer. It |
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136 | * is usually deducted from the number returned. |
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137 | * |
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138 | * LEAST_VALID is the lowest number this routine should trust. Numbers |
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139 | * below this are "noise" and zero is returned. |
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140 | */ |
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141 | |
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142 | #define AVG_OVERHEAD 1 /* It typically takes X.X microseconds */ |
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143 | /* (Y countdowns) to start/stop the timer. */ |
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144 | /* This value is in microseconds. */ |
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145 | #define LEAST_VALID 0 /* 20 */ /* Don't trust a clicks value lower than this */ |
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146 | |
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147 | int Read_timer( void ) |
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148 | { |
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149 | rtems_unsigned32 clicks; |
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150 | rtems_unsigned32 total ; |
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151 | /* |
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152 | * Read the timer and see how many clicks it has been since we started. |
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153 | */ |
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154 | |
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155 | |
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156 | clicks = read16( MTU_TCNT1); /* XXX: read some HW here */ |
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157 | |
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158 | /* |
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159 | * Total is calculated by taking into account the number of timer overflow |
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160 | * interrupts since the timer was initialized and clicks since the last |
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161 | * interrupts. |
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162 | */ |
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163 | |
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164 | total = clicks + Timer_interrupts * 65536 ; |
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165 | |
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166 | if ( Timer_driver_Find_average_overhead ) |
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167 | return total / SCALE; /* in XXX microsecond units */ |
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168 | else |
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169 | { |
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170 | if ( total < LEAST_VALID ) |
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171 | return 0; /* below timer resolution */ |
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172 | /* |
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173 | * Somehow convert total into microseconds |
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174 | */ |
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175 | return (total / SCALE - AVG_OVERHEAD) ; |
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176 | } |
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177 | } |
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178 | |
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179 | /* |
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180 | * Empty function call used in loops to measure basic cost of looping |
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181 | * in Timing Test Suite. |
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182 | */ |
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183 | |
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184 | rtems_status_code Empty_function( void ) |
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185 | { |
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186 | return RTEMS_SUCCESSFUL; |
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187 | } |
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188 | |
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189 | void Set_find_average_overhead( |
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190 | rtems_boolean find_flag |
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191 | ) |
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192 | { |
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193 | Timer_driver_Find_average_overhead = find_flag; |
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194 | } |
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195 | |
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196 | /* Timer 1 is used */ |
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197 | |
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198 | #pragma interrupt |
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199 | void timerisr( void ) |
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200 | { |
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201 | unsigned8 temp8; |
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202 | |
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203 | /* reset the flags of the status register */ |
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204 | temp8 = read8( MTU_TSR1) & MTU1_STAT_MASK; |
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205 | write8( temp8, MTU_TSR1); |
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206 | |
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207 | Timer_interrupts += 1; |
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208 | } |
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