source: rtems/c/src/lib/libcpu/sh/sh7045/score/ispsh7045.c @ b22a19e

4.104.114.84.95
Last change on this file since b22a19e was b22a19e, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 22, 1999 at 1:46:50 PM

Adding files not added as part of merger of SH2 port.

  • Property mode set to 100644
File size: 10.5 KB
Line 
1/*
2 * This file contains the isp frames for the user interrupts.
3 * From these procedures __ISR_Handler is called with the vector number
4 * as argument.
5 *
6 * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
7 * some releases of gcc doesn't properly handle #pragma interrupt, if a
8 * file contains both isrs and normal functions.
9 *
10 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
11 *           Bernd Becker (becker@faw.uni-ulm.de)
12 *
13 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
14 *
15 *  This program is distributed in the hope that it will be useful,
16 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
17 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
18 *
19 *
20 *  COPYRIGHT (c) 1998.
21 *  On-Line Applications Research Corporation (OAR).
22 *  Copyright assigned to U.S. Government, 1994.
23 *
24 *  The license and distribution terms for this file may be
25 *  found in the file LICENSE in this distribution or at
26 *  http://www.OARcorp.com/rtems/license.html.
27 *
28 *      Modified to reflect isp entries for sh7045 processor:
29 *      John M. Mills (jmills@tga.com)
30 *      TGA Technologies, Inc.
31 *      100 Pinnacle Way, Suite 140
32 *      Norcross, GA 30071 U.S.A.
33 *      August, 1999
34 *
35 *      This modified file may be copied and distributed in accordance
36 *      the above-referenced license. It is provided for critique and
37 *      developmental purposes without any warranty nor representation
38 *      by the authors or by TGA Technologies.
39 *
40 *  $Id$
41 */
42
43/**************************************************************************
44 *     Note this file contains two pair of independent sections which are
45 *     used conditionally, depending on whether the module is being built
46 *     for the SH703x or SH704x families of processor
47 **************************************************************************/
48
49#include <rtems/system.h>
50#include <rtems/score/shtypes.h>
51
52#if !defined (sh7045)
53#error Wrong CPU MODEL
54#endif
55
56/*
57 * This is a exception vector table
58 *
59 * It has the same structure as the actual vector table (vectab)
60 */
61
62
63/* SH-2 ISR Table */
64#include <rtems/score/ispsh7045.h>
65
66proc_ptr _Hardware_isr_Table[256]={
67_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,         /* PWRon Reset, Maual Reset,...*/
68_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
69_dummy_isp, _dummy_isp, _dummy_isp,
70_nmi_isp, _usb_isp,                               /* irq 11, 12*/
71_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
72_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
73_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
74_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
75_dummy_isp, _dummy_isp, _dummy_isp, 
76/* trapa 0 -31 */
77_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
78_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
79_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
80_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
81_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
82_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
83_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
84_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
85_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp,   /* external H/W: irq 64-71 */
86_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
87_dma0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DMAC: irq 72-87*/
88_dma1_isp, _dummy_isp, _dummy_isp, _dummy_isp,
89_dma2_isp, _dummy_isp, _dummy_isp, _dummy_isp,
90_dma3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
91_mtua0_isp, _mtub0_isp, _mtuc0_isp, _mtud0_isp, /* MTUs: irq 88-127 */
92_mtuv0_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
93_mtua1_isp, _mtub1_isp, _dummy_isp, _dummy_isp,
94_mtuv1_isp, _mtuu1_isp, _dummy_isp, _dummy_isp, 
95_mtua2_isp, _mtub2_isp, _dummy_isp, _dummy_isp,
96_mtuv2_isp, _mtuu2_isp, _dummy_isp, _dummy_isp, 
97_mtua3_isp, _mtub3_isp, _mtuc3_isp, _mtud3_isp,
98_mtuv3_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
99_mtua4_isp, _mtub4_isp, _mtuc4_isp, _mtud4_isp,
100_mtuv4_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
101_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp, /* SCI0-1: irq 128-135*/
102_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
103_adi0_isp, _adi1_isp, _dummy_isp, _dummy_isp, /* ADC0-1: irq 136-139*/
104_dtci_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DTU: irq 140-143 */
105_cmt0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* CMT0-1: irq 144-151 */
106_cmt1_isp, _dummy_isp, _dummy_isp, _dummy_isp,
107_wdt_isp, /* WDT: irq 152*/
108_bsc_isp, _dummy_isp, _dummy_isp, /* BSC: irq 153-155*/
109_oei_isp, /* I/O Port: irq 156*/
110};
111
112#define Str(a)#a
113
114/*
115 * Some versions of gcc and all version of egcs at least until egcs-1.1b
116 * are not able to handle #pragma interrupt correctly if more than 1 isr is
117 * contained in a file and when optimizing.
118 * We try to work around this problem by using the macro below.
119 */
120#define isp( name, number, func)\
121asm (".global _"Str(name)"\n\t" \
122     "_"Str(name)":       \n\t" \
123     "    mov.l r0,@-r15   \n\t" \
124     "    mov.l r1,@-r15   \n\t" \
125     "    mov.l r2,@-r15   \n\t" \
126     "    mov.l r3,@-r15   \n\t" \
127     "    mov.l r4,@-r15   \n\t" \
128     "    mov.l r5,@-r15   \n\t" \
129     "    mov.l r6,@-r15   \n\t" \
130     "    mov.l r7,@-r15   \n\t" \
131     "    mov.l r14,@-r15  \n\t" \
132     "    sts.l pr,@-r15   \n\t" \
133     "    sts.l mach,@-r15 \n\t" \
134     "    sts.l macl,@-r15 \n\t" \
135     "    mov r15,r14      \n\t" \
136     "    mov.l "Str(name)"_k, r1\n\t" \
137     "    jsr @r1           \n\t" \
138     "    mov #"Str(number)", r4\n\t" \
139     "    mov   r14,r15    \n\t" \
140     "    lds.l @r15+,macl \n\t" \
141     "    lds.l @r15+,mach \n\t" \
142     "    lds.l @r15+,pr   \n\t" \
143     "    mov.l @r15+,r14  \n\t" \
144     "    mov.l @r15+,r7   \n\t" \
145     "    mov.l @r15+,r6   \n\t" \
146     "    mov.l @r15+,r5   \n\t" \
147     "    mov.l @r15+,r4   \n\t" \
148     "    mov.l @r15+,r3   \n\t" \
149     "    mov.l @r15+,r2   \n\t" \
150     "    mov.l @r15+,r1   \n\t" \
151     "    mov.l @r15+,r0   \n\t" \
152     "    rte              \n\t" \
153     "    nop              \n\t" \
154     "    .align 2         \n\t" \
155     #name"_k: \n\t" \
156     ".long "Str(func));
157
158/************************************************
159 * Dummy interrupt service procedure for
160 * interrupts being not allowed --> Trap 34
161 ************************************************/
162asm(" .section .text
163.global __dummy_isp
164__dummy_isp:
165      mov.l r14,@-r15
166      mov   r15, r14
167      trapa #34
168      mov.l @r15+,r14
169      rte
170      nop");
171
172/*******************************************************************
173 *     ISP Vector Table for sh7045 family of processors            *
174 *******************************************************************/
175
176
177/*****************************
178 * Non maskable interrupt
179 *****************************/
180isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
181
182/*****************************
183 * User break controller
184 *****************************/
185isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
186
187/*****************************
188 *  External interrupts 0-7
189 *****************************/
190isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
191isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler);
192isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler);
193isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler);
194isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler);
195isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler);
196isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler);
197isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler);
198
199/*****************************
200 * DMA - controller
201 *****************************/
202isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
203isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler);
204isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler);
205isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler);
206
207
208/*****************************
209 * Match timer unit
210 *****************************/
211
212/*****************************
213 * Timer 0
214 *****************************/
215isp( _mtua0_isp, MTUA0_ISP_V, ___ISR_Handler);
216isp( _mtub0_isp, MTUB0_ISP_V, ___ISR_Handler);
217isp( _mtuc0_isp, MTUC0_ISP_V, ___ISR_Handler);
218isp( _mtud0_isp, MTUD0_ISP_V, ___ISR_Handler);
219isp( _mtuv0_isp, MTUV0_ISP_V, ___ISR_Handler);
220
221/*****************************
222 * Timer 1
223 *****************************/
224isp( _mtua1_isp, MTUA1_ISP_V, ___ISR_Handler);
225isp( _mtub1_isp, MTUB1_ISP_V, ___ISR_Handler);
226isp( _mtuv1_isp, MTUV1_ISP_V, ___ISR_Handler);
227isp( _mtuu1_isp, MTUU1_ISP_V, ___ISR_Handler);
228
229/*****************************
230 * Timer 2
231 *****************************/
232isp( _mtua2_isp, MTUA2_ISP_V, ___ISR_Handler);
233isp( _mtub2_isp, MTUB2_ISP_V, ___ISR_Handler);
234isp( _mtuv2_isp, MTUV2_ISP_V, ___ISR_Handler);
235isp( _mtuu2_isp, MTUU2_ISP_V, ___ISR_Handler);
236
237/*****************************
238 * Timer 3
239 *****************************/
240isp( _mtua3_isp, MTUA3_ISP_V, ___ISR_Handler);
241isp( _mtub3_isp, MTUB3_ISP_V, ___ISR_Handler);
242isp( _mtuc3_isp, MTUC3_ISP_V, ___ISR_Handler);
243isp( _mtud3_isp, MTUD3_ISP_V, ___ISR_Handler);
244isp( _mtuv3_isp, MTUV3_ISP_V, ___ISR_Handler);
245
246/*****************************
247 * Timer 4
248 *****************************/
249isp( _mtua4_isp, MTUA4_ISP_V, ___ISR_Handler);
250isp( _mtub4_isp, MTUB4_ISP_V, ___ISR_Handler);
251isp( _mtuc4_isp, MTUC4_ISP_V, ___ISR_Handler);
252isp( _mtud4_isp, MTUD4_ISP_V, ___ISR_Handler);
253isp( _mtuv4_isp, MTUV4_ISP_V, ___ISR_Handler);
254
255
256/*****************************
257 * Serial interfaces
258 *****************************/
259
260/*****************************
261 * Serial interface 0
262 *****************************/
263isp( _eri0_isp,  ERI0_ISP_V, ___ISR_Handler);
264isp( _rxi0_isp,  RXI0_ISP_V, ___ISR_Handler);
265isp( _txi0_isp,  TXI0_ISP_V, ___ISR_Handler);
266isp( _tei0_isp,  TEI0_ISP_V, ___ISR_Handler);
267
268/*****************************
269 * Serial interface 1
270 *****************************/
271isp( _eri1_isp,  ERI1_ISP_V, ___ISR_Handler);
272isp( _rxi1_isp,  RXI1_ISP_V, ___ISR_Handler);
273isp( _txi1_isp,  TXI1_ISP_V, ___ISR_Handler);
274isp( _tei1_isp,  TEI1_ISP_V, ___ISR_Handler);
275
276
277/******************************
278 * A/D converters
279 * ADC0-1
280 ******************************/
281isp( _adi0_isp,  ADI0_ISP_V, ___ISR_Handler);
282isp( _adi1_isp,  ADI1_ISP_V, ___ISR_Handler);
283
284
285/******************************
286 *  Data transfer controller
287 ******************************/
288isp( _dtci_isp,  DTC_ISP_V, ___ISR_Handler);
289
290
291/******************************
292 *  Counter match timer
293 ******************************/
294isp( _cmt0_isp,  CMT0_ISP_V, ___ISR_Handler);
295isp( _cmt1_isp,  CMT1_ISP_V, ___ISR_Handler);
296
297
298/******************************
299 *  Watchdog timer
300 ******************************/
301isp( _wdt_isp,  WDT_ISP_V, ___ISR_Handler);
302
303
304/******************************
305 * DRAM refresh control unit
306 * of bus state controller
307 ******************************/
308isp( _bsc_isp,  CMI_ISP_V, ___ISR_Handler);
309
310/******************************
311 *  I/O port
312 ******************************/
313isp( _oei_isp,  OEI_ISP_V, ___ISR_Handler);
314
315
316/*****************************
317 * Parity control unit of
318 * the bus state controller
319 * NOT PROVIDED IN SH-2
320 *****************************/
321/* isp( _prt_isp,  PRT_ISP_V, ___ISR_Handler); */
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