1 | /* |
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2 | * This file contains the isp frames for the user interrupts. |
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3 | * From these procedures __ISR_Handler is called with the vector number |
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4 | * as argument. |
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5 | * |
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6 | * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in |
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7 | * some releases of gcc doesn't properly handle #pragma interrupt, if a |
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8 | * file contains both isrs and normal functions. |
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9 | * |
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10 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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11 | * Bernd Becker (becker@faw.uni-ulm.de) |
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12 | * |
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13 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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14 | * |
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15 | * This program is distributed in the hope that it will be useful, |
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16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE |
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18 | * |
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19 | * |
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20 | * COPYRIGHT (c) 1998. |
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21 | * On-Line Applications Research Corporation (OAR). |
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22 | * |
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23 | * The license and distribution terms for this file may be |
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24 | * found in the file LICENSE in this distribution or at |
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25 | * http://www.rtems.com/license/LICENSE. |
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26 | * |
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27 | * Modified to reflect isp entries for sh7045 processor: |
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28 | * John M. Mills (jmills@tga.com) |
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29 | * TGA Technologies, Inc. |
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30 | * 100 Pinnacle Way, Suite 140 |
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31 | * Norcross, GA 30071 U.S.A. |
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32 | * August, 1999 |
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33 | * |
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34 | * This modified file may be copied and distributed in accordance |
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35 | * the above-referenced license. It is provided for critique and |
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36 | * developmental purposes without any warranty nor representation |
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37 | * by the authors or by TGA Technologies. |
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38 | * |
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39 | * $Id$ |
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40 | */ |
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41 | |
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42 | #include <rtems/system.h> |
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43 | #include <rtems/score/types.h> |
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44 | |
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45 | /* |
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46 | * This is a exception vector table |
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47 | * |
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48 | * It has the same structure as the actual vector table (vectab) |
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49 | */ |
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50 | |
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51 | |
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52 | /* SH-2 ISR Table */ |
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53 | #include <rtems/score/ispsh7045.h> |
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54 | |
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55 | proc_ptr _Hardware_isr_Table[256]={ |
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56 | _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* PWRon Reset, Maual Reset,...*/ |
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57 | _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, |
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58 | _dummy_isp, _dummy_isp, _dummy_isp, |
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59 | _nmi_isp, _usb_isp, /* irq 11, 12*/ |
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60 | _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, |
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61 | _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, |
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62 | _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, |
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63 | _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, |
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64 | _dummy_isp, _dummy_isp, _dummy_isp, |
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65 | /* trapa 0 -31 */ |
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66 | _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, |
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67 | _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, |
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68 | _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, |
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69 | _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, |
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70 | _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, |
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71 | _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, |
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72 | _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, |
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73 | _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, |
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74 | _irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp, /* external H/W: irq 64-71 */ |
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75 | _irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp, |
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76 | _dma0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DMAC: irq 72-87*/ |
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77 | _dma1_isp, _dummy_isp, _dummy_isp, _dummy_isp, |
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78 | _dma2_isp, _dummy_isp, _dummy_isp, _dummy_isp, |
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79 | _dma3_isp, _dummy_isp, _dummy_isp, _dummy_isp, |
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80 | _mtua0_isp, _mtub0_isp, _mtuc0_isp, _mtud0_isp, /* MTUs: irq 88-127 */ |
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81 | _mtuv0_isp, _dummy_isp, _dummy_isp, _dummy_isp, |
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82 | _mtua1_isp, _mtub1_isp, _dummy_isp, _dummy_isp, |
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83 | _mtuv1_isp, _mtuu1_isp, _dummy_isp, _dummy_isp, |
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84 | _mtua2_isp, _mtub2_isp, _dummy_isp, _dummy_isp, |
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85 | _mtuv2_isp, _mtuu2_isp, _dummy_isp, _dummy_isp, |
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86 | _mtua3_isp, _mtub3_isp, _mtuc3_isp, _mtud3_isp, |
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87 | _mtuv3_isp, _dummy_isp, _dummy_isp, _dummy_isp, |
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88 | _mtua4_isp, _mtub4_isp, _mtuc4_isp, _mtud4_isp, |
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89 | _mtuv4_isp, _dummy_isp, _dummy_isp, _dummy_isp, |
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90 | _eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp, /* SCI0-1: irq 128-135*/ |
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91 | _eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp, |
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92 | _adi0_isp, _adi1_isp, _dummy_isp, _dummy_isp, /* ADC0-1: irq 136-139*/ |
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93 | _dtci_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DTU: irq 140-143 */ |
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94 | _cmt0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* CMT0-1: irq 144-151 */ |
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95 | _cmt1_isp, _dummy_isp, _dummy_isp, _dummy_isp, |
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96 | _wdt_isp, /* WDT: irq 152*/ |
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97 | _bsc_isp, _dummy_isp, _dummy_isp, /* BSC: irq 153-155*/ |
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98 | _oei_isp, /* I/O Port: irq 156*/ |
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99 | }; |
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100 | |
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101 | #define Str(a)#a |
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102 | |
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103 | /* |
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104 | * Some versions of gcc and all version of egcs at least until egcs-1.1b |
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105 | * are not able to handle #pragma interrupt correctly if more than 1 isr is |
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106 | * contained in a file and when optimizing. |
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107 | * We try to work around this problem by using the macro below. |
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108 | */ |
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109 | #define isp( name, number, func)\ |
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110 | asm (".global _"Str(name)"\n\t"\ |
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111 | "_"Str(name)": \n\t"\ |
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112 | " mov.l r0,@-r15 \n\t"\ |
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113 | " mov.l r1,@-r15 \n\t"\ |
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114 | " mov.l r2,@-r15 \n\t"\ |
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115 | " mov.l r3,@-r15 \n\t"\ |
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116 | " mov.l r4,@-r15 \n\t"\ |
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117 | " mov.l r5,@-r15 \n\t"\ |
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118 | " mov.l r6,@-r15 \n\t"\ |
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119 | " mov.l r7,@-r15 \n\t"\ |
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120 | " mov.l r14,@-r15 \n\t"\ |
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121 | " sts.l pr,@-r15 \n\t"\ |
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122 | " sts.l mach,@-r15 \n\t"\ |
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123 | " sts.l macl,@-r15 \n\t"\ |
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124 | " mov r15,r14 \n\t"\ |
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125 | " mov.l "Str(name)"_v, r2 \n\t"\ |
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126 | " mov.l "Str(name)"_k, r1\n\t"\ |
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127 | " jsr @r1 \n\t"\ |
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128 | " mov r2,r4 \n\t"\ |
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129 | " mov r14,r15 \n\t"\ |
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130 | " lds.l @r15+,macl \n\t"\ |
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131 | " lds.l @r15+,mach \n\t"\ |
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132 | " lds.l @r15+,pr \n\t"\ |
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133 | " mov.l @r15+,r14 \n\t"\ |
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134 | " mov.l @r15+,r7 \n\t"\ |
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135 | " mov.l @r15+,r6 \n\t"\ |
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136 | " mov.l @r15+,r5 \n\t"\ |
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137 | " mov.l @r15+,r4 \n\t"\ |
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138 | " mov.l @r15+,r3 \n\t"\ |
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139 | " mov.l @r15+,r2 \n\t"\ |
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140 | " mov.l @r15+,r1 \n\t"\ |
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141 | " mov.l @r15+,r0 \n\t"\ |
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142 | " rte \n\t"\ |
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143 | " nop \n\t"\ |
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144 | " .align 2 \n\t"\ |
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145 | #name"_k: \n\t"\ |
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146 | ".long "Str(func)"\n\t"\ |
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147 | #name"_v: \n\t"\ |
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148 | ".long "Str(number)); |
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149 | |
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150 | /************************************************ |
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151 | * Dummy interrupt service procedure for |
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152 | * interrupts being not allowed --> Trap 34 |
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153 | ************************************************/ |
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154 | asm(" .section .text\n\ |
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155 | .global __dummy_isp\n\ |
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156 | __dummy_isp:\n\ |
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157 | mov.l r14,@-r15\n\ |
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158 | mov r15, r14\n\ |
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159 | trapa #34\n\ |
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160 | mov.l @r15+,r14\n\ |
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161 | rte\n\ |
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162 | nop"); |
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163 | |
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164 | /******************************************************************* |
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165 | * ISP Vector Table for sh7045 family of processors * |
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166 | *******************************************************************/ |
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167 | |
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168 | |
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169 | /***************************** |
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170 | * Non maskable interrupt |
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171 | *****************************/ |
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172 | isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler); |
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173 | |
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174 | /***************************** |
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175 | * User break controller |
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176 | *****************************/ |
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177 | isp( _usb_isp, USB_ISP_V, ___ISR_Handler); |
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178 | |
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179 | /***************************** |
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180 | * External interrupts 0-7 |
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181 | *****************************/ |
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182 | isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler); |
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183 | isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler); |
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184 | isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler); |
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185 | isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler); |
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186 | isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler); |
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187 | isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler); |
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188 | isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler); |
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189 | isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler); |
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190 | |
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191 | /***************************** |
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192 | * DMA - controller |
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193 | *****************************/ |
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194 | isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler); |
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195 | isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler); |
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196 | isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler); |
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197 | isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler); |
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198 | |
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199 | |
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200 | /***************************** |
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201 | * Match timer unit |
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202 | *****************************/ |
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203 | |
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204 | /***************************** |
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205 | * Timer 0 |
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206 | *****************************/ |
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207 | isp( _mtua0_isp, MTUA0_ISP_V, ___ISR_Handler); |
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208 | isp( _mtub0_isp, MTUB0_ISP_V, ___ISR_Handler); |
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209 | isp( _mtuc0_isp, MTUC0_ISP_V, ___ISR_Handler); |
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210 | isp( _mtud0_isp, MTUD0_ISP_V, ___ISR_Handler); |
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211 | isp( _mtuv0_isp, MTUV0_ISP_V, ___ISR_Handler); |
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212 | |
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213 | /***************************** |
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214 | * Timer 1 |
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215 | *****************************/ |
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216 | isp( _mtua1_isp, MTUA1_ISP_V, ___ISR_Handler); |
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217 | isp( _mtub1_isp, MTUB1_ISP_V, ___ISR_Handler); |
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218 | isp( _mtuv1_isp, MTUV1_ISP_V, ___ISR_Handler); |
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219 | isp( _mtuu1_isp, MTUU1_ISP_V, ___ISR_Handler); |
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220 | |
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221 | /***************************** |
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222 | * Timer 2 |
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223 | *****************************/ |
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224 | isp( _mtua2_isp, MTUA2_ISP_V, ___ISR_Handler); |
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225 | isp( _mtub2_isp, MTUB2_ISP_V, ___ISR_Handler); |
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226 | isp( _mtuv2_isp, MTUV2_ISP_V, ___ISR_Handler); |
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227 | isp( _mtuu2_isp, MTUU2_ISP_V, ___ISR_Handler); |
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228 | |
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229 | /***************************** |
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230 | * Timer 3 |
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231 | *****************************/ |
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232 | isp( _mtua3_isp, MTUA3_ISP_V, ___ISR_Handler); |
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233 | isp( _mtub3_isp, MTUB3_ISP_V, ___ISR_Handler); |
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234 | isp( _mtuc3_isp, MTUC3_ISP_V, ___ISR_Handler); |
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235 | isp( _mtud3_isp, MTUD3_ISP_V, ___ISR_Handler); |
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236 | isp( _mtuv3_isp, MTUV3_ISP_V, ___ISR_Handler); |
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237 | |
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238 | /***************************** |
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239 | * Timer 4 |
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240 | *****************************/ |
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241 | isp( _mtua4_isp, MTUA4_ISP_V, ___ISR_Handler); |
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242 | isp( _mtub4_isp, MTUB4_ISP_V, ___ISR_Handler); |
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243 | isp( _mtuc4_isp, MTUC4_ISP_V, ___ISR_Handler); |
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244 | isp( _mtud4_isp, MTUD4_ISP_V, ___ISR_Handler); |
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245 | isp( _mtuv4_isp, MTUV4_ISP_V, ___ISR_Handler); |
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246 | |
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247 | |
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248 | /***************************** |
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249 | * Serial interfaces |
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250 | *****************************/ |
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251 | |
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252 | /***************************** |
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253 | * Serial interface 0 |
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254 | *****************************/ |
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255 | isp( _eri0_isp, ERI0_ISP_V, ___ISR_Handler); |
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256 | isp( _rxi0_isp, RXI0_ISP_V, ___ISR_Handler); |
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257 | isp( _txi0_isp, TXI0_ISP_V, ___ISR_Handler); |
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258 | isp( _tei0_isp, TEI0_ISP_V, ___ISR_Handler); |
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259 | |
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260 | /***************************** |
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261 | * Serial interface 1 |
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262 | *****************************/ |
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263 | isp( _eri1_isp, ERI1_ISP_V, ___ISR_Handler); |
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264 | isp( _rxi1_isp, RXI1_ISP_V, ___ISR_Handler); |
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265 | isp( _txi1_isp, TXI1_ISP_V, ___ISR_Handler); |
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266 | isp( _tei1_isp, TEI1_ISP_V, ___ISR_Handler); |
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267 | |
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268 | |
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269 | /****************************** |
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270 | * A/D converters |
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271 | * ADC0-1 |
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272 | ******************************/ |
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273 | isp( _adi0_isp, ADI0_ISP_V, ___ISR_Handler); |
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274 | isp( _adi1_isp, ADI1_ISP_V, ___ISR_Handler); |
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275 | |
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276 | |
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277 | /****************************** |
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278 | * Data transfer controller |
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279 | ******************************/ |
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280 | isp( _dtci_isp, DTC_ISP_V, ___ISR_Handler); |
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281 | |
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282 | |
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283 | /****************************** |
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284 | * Counter match timer |
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285 | ******************************/ |
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286 | isp( _cmt0_isp, CMT0_ISP_V, ___ISR_Handler); |
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287 | isp( _cmt1_isp, CMT1_ISP_V, ___ISR_Handler); |
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288 | |
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289 | |
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290 | /****************************** |
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291 | * Watchdog timer |
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292 | ******************************/ |
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293 | isp( _wdt_isp, WDT_ISP_V, ___ISR_Handler); |
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294 | |
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295 | |
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296 | /****************************** |
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297 | * DRAM refresh control unit |
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298 | * of bus state controller |
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299 | ******************************/ |
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300 | isp( _bsc_isp, CMI_ISP_V, ___ISR_Handler); |
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301 | |
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302 | /****************************** |
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303 | * I/O port |
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304 | ******************************/ |
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305 | isp( _oei_isp, OEI_ISP_V, ___ISR_Handler); |
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306 | |
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307 | |
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308 | /***************************** |
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309 | * Parity control unit of |
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310 | * the bus state controller |
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311 | * NOT PROVIDED IN SH-2 |
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312 | *****************************/ |
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313 | /* isp( _prt_isp, PRT_ISP_V, ___ISR_Handler); */ |
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