source: rtems/c/src/lib/libcpu/sh/sh7045/score/ispsh7045.c @ 7ae5125

4.104.114.84.95
Last change on this file since 7ae5125 was 7ae5125, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 16, 2001 at 9:08:28 PM

2001-08-10 Radzislaw Galler <rgaller@…>

  • score/cpu_asm.c (sh_set_irq_priority): Changed interrupt vector number range check and handling of interrupt priority regs to conform SH2 specs.
  • sci/sci_termios.c: New file.
  • include/sci_termios.h: New file.
  • include/Makefile.am (EXTRA_DIST): Added sci_termios.h. (include_sh_HEADERS): Added sci_termios.h.
  • score/ispsh7045.c (isp): Calling an ISR with immediate argument casued negative sign extension for vector numbers of 128 and above. This was fixed.
  • sci/sci.c: Cleaned initialization of SCI registers; added necessary setup for new TERMIOS console cooperation
  • Property mode set to 100644
File size: 10.2 KB
Line 
1/*
2 * This file contains the isp frames for the user interrupts.
3 * From these procedures __ISR_Handler is called with the vector number
4 * as argument.
5 *
6 * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
7 * some releases of gcc doesn't properly handle #pragma interrupt, if a
8 * file contains both isrs and normal functions.
9 *
10 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
11 *           Bernd Becker (becker@faw.uni-ulm.de)
12 *
13 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
14 *
15 *  This program is distributed in the hope that it will be useful,
16 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
17 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
18 *
19 *
20 *  COPYRIGHT (c) 1998.
21 *  On-Line Applications Research Corporation (OAR).
22 *  Copyright assigned to U.S. Government, 1994.
23 *
24 *  The license and distribution terms for this file may be
25 *  found in the file LICENSE in this distribution or at
26 *  http://www.OARcorp.com/rtems/license.html.
27 *
28 *      Modified to reflect isp entries for sh7045 processor:
29 *      John M. Mills (jmills@tga.com)
30 *      TGA Technologies, Inc.
31 *      100 Pinnacle Way, Suite 140
32 *      Norcross, GA 30071 U.S.A.
33 *      August, 1999
34 *
35 *      This modified file may be copied and distributed in accordance
36 *      the above-referenced license. It is provided for critique and
37 *      developmental purposes without any warranty nor representation
38 *      by the authors or by TGA Technologies.
39 *
40 *  $Id$
41 */
42
43#include <rtems/system.h>
44#include <rtems/score/shtypes.h>
45
46/*
47 * This is a exception vector table
48 *
49 * It has the same structure as the actual vector table (vectab)
50 */
51
52
53/* SH-2 ISR Table */
54#include <rtems/score/ispsh7045.h>
55
56proc_ptr _Hardware_isr_Table[256]={
57_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,         /* PWRon Reset, Maual Reset,...*/
58_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
59_dummy_isp, _dummy_isp, _dummy_isp,
60_nmi_isp, _usb_isp,                               /* irq 11, 12*/
61_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
62_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
63_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
64_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
65_dummy_isp, _dummy_isp, _dummy_isp, 
66/* trapa 0 -31 */
67_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
68_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
69_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
70_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
71_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
72_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
73_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
74_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
75_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp,   /* external H/W: irq 64-71 */
76_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
77_dma0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DMAC: irq 72-87*/
78_dma1_isp, _dummy_isp, _dummy_isp, _dummy_isp,
79_dma2_isp, _dummy_isp, _dummy_isp, _dummy_isp,
80_dma3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
81_mtua0_isp, _mtub0_isp, _mtuc0_isp, _mtud0_isp, /* MTUs: irq 88-127 */
82_mtuv0_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
83_mtua1_isp, _mtub1_isp, _dummy_isp, _dummy_isp,
84_mtuv1_isp, _mtuu1_isp, _dummy_isp, _dummy_isp, 
85_mtua2_isp, _mtub2_isp, _dummy_isp, _dummy_isp,
86_mtuv2_isp, _mtuu2_isp, _dummy_isp, _dummy_isp, 
87_mtua3_isp, _mtub3_isp, _mtuc3_isp, _mtud3_isp,
88_mtuv3_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
89_mtua4_isp, _mtub4_isp, _mtuc4_isp, _mtud4_isp,
90_mtuv4_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
91_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp, /* SCI0-1: irq 128-135*/
92_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
93_adi0_isp, _adi1_isp, _dummy_isp, _dummy_isp, /* ADC0-1: irq 136-139*/
94_dtci_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DTU: irq 140-143 */
95_cmt0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* CMT0-1: irq 144-151 */
96_cmt1_isp, _dummy_isp, _dummy_isp, _dummy_isp,
97_wdt_isp, /* WDT: irq 152*/
98_bsc_isp, _dummy_isp, _dummy_isp, /* BSC: irq 153-155*/
99_oei_isp, /* I/O Port: irq 156*/
100};
101
102#define Str(a)#a
103
104/*
105 * Some versions of gcc and all version of egcs at least until egcs-1.1b
106 * are not able to handle #pragma interrupt correctly if more than 1 isr is
107 * contained in a file and when optimizing.
108 * We try to work around this problem by using the macro below.
109 */
110#define isp( name, number, func)\
111asm (".global _"Str(name)"\n\t" \
112     "_"Str(name)":       \n\t" \
113     "    mov.l r0,@-r15   \n\t" \
114     "    mov.l r1,@-r15   \n\t" \
115     "    mov.l r2,@-r15   \n\t" \
116     "    mov.l r3,@-r15   \n\t" \
117     "    mov.l r4,@-r15   \n\t" \
118     "    mov.l r5,@-r15   \n\t" \
119     "    mov.l r6,@-r15   \n\t" \
120     "    mov.l r7,@-r15   \n\t" \
121     "    mov.l r14,@-r15  \n\t" \
122     "    sts.l pr,@-r15   \n\t" \
123     "    sts.l mach,@-r15 \n\t" \
124     "    sts.l macl,@-r15 \n\t" \
125     "    mov r15,r14      \n\t" \
126     "    mov.l "Str(name)"_v, r2 \n\t" \
127     "    mov.l "Str(name)"_k, r1\n\t" \
128     "    jsr @r1           \n\t" \
129     "    mov   r2,r4      \n\t" \
130     "    mov   r14,r15    \n\t" \
131     "    lds.l @r15+,macl \n\t" \
132     "    lds.l @r15+,mach \n\t" \
133     "    lds.l @r15+,pr   \n\t" \
134     "    mov.l @r15+,r14  \n\t" \
135     "    mov.l @r15+,r7   \n\t" \
136     "    mov.l @r15+,r6   \n\t" \
137     "    mov.l @r15+,r5   \n\t" \
138     "    mov.l @r15+,r4   \n\t" \
139     "    mov.l @r15+,r3   \n\t" \
140     "    mov.l @r15+,r2   \n\t" \
141     "    mov.l @r15+,r1   \n\t" \
142     "    mov.l @r15+,r0   \n\t" \
143     "    rte              \n\t" \
144     "    nop              \n\t" \
145     "    .align 2         \n\t" \
146     #name"_k: \n\t" \
147     ".long "Str(func)"\n\t" \
148     #name"_v: \n\t" \
149     ".long "Str(number));
150
151/************************************************
152 * Dummy interrupt service procedure for
153 * interrupts being not allowed --> Trap 34
154 ************************************************/
155asm(" .section .text
156.global __dummy_isp
157__dummy_isp:
158      mov.l r14,@-r15
159      mov   r15, r14
160      trapa #34
161      mov.l @r15+,r14
162      rte
163      nop");
164
165/*******************************************************************
166 *     ISP Vector Table for sh7045 family of processors            *
167 *******************************************************************/
168
169
170/*****************************
171 * Non maskable interrupt
172 *****************************/
173isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
174
175/*****************************
176 * User break controller
177 *****************************/
178isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
179
180/*****************************
181 *  External interrupts 0-7
182 *****************************/
183isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
184isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler);
185isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler);
186isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler);
187isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler);
188isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler);
189isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler);
190isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler);
191
192/*****************************
193 * DMA - controller
194 *****************************/
195isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
196isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler);
197isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler);
198isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler);
199
200
201/*****************************
202 * Match timer unit
203 *****************************/
204
205/*****************************
206 * Timer 0
207 *****************************/
208isp( _mtua0_isp, MTUA0_ISP_V, ___ISR_Handler);
209isp( _mtub0_isp, MTUB0_ISP_V, ___ISR_Handler);
210isp( _mtuc0_isp, MTUC0_ISP_V, ___ISR_Handler);
211isp( _mtud0_isp, MTUD0_ISP_V, ___ISR_Handler);
212isp( _mtuv0_isp, MTUV0_ISP_V, ___ISR_Handler);
213
214/*****************************
215 * Timer 1
216 *****************************/
217isp( _mtua1_isp, MTUA1_ISP_V, ___ISR_Handler);
218isp( _mtub1_isp, MTUB1_ISP_V, ___ISR_Handler);
219isp( _mtuv1_isp, MTUV1_ISP_V, ___ISR_Handler);
220isp( _mtuu1_isp, MTUU1_ISP_V, ___ISR_Handler);
221
222/*****************************
223 * Timer 2
224 *****************************/
225isp( _mtua2_isp, MTUA2_ISP_V, ___ISR_Handler);
226isp( _mtub2_isp, MTUB2_ISP_V, ___ISR_Handler);
227isp( _mtuv2_isp, MTUV2_ISP_V, ___ISR_Handler);
228isp( _mtuu2_isp, MTUU2_ISP_V, ___ISR_Handler);
229
230/*****************************
231 * Timer 3
232 *****************************/
233isp( _mtua3_isp, MTUA3_ISP_V, ___ISR_Handler);
234isp( _mtub3_isp, MTUB3_ISP_V, ___ISR_Handler);
235isp( _mtuc3_isp, MTUC3_ISP_V, ___ISR_Handler);
236isp( _mtud3_isp, MTUD3_ISP_V, ___ISR_Handler);
237isp( _mtuv3_isp, MTUV3_ISP_V, ___ISR_Handler);
238
239/*****************************
240 * Timer 4
241 *****************************/
242isp( _mtua4_isp, MTUA4_ISP_V, ___ISR_Handler);
243isp( _mtub4_isp, MTUB4_ISP_V, ___ISR_Handler);
244isp( _mtuc4_isp, MTUC4_ISP_V, ___ISR_Handler);
245isp( _mtud4_isp, MTUD4_ISP_V, ___ISR_Handler);
246isp( _mtuv4_isp, MTUV4_ISP_V, ___ISR_Handler);
247
248
249/*****************************
250 * Serial interfaces
251 *****************************/
252
253/*****************************
254 * Serial interface 0
255 *****************************/
256isp( _eri0_isp,  ERI0_ISP_V, ___ISR_Handler);
257isp( _rxi0_isp,  RXI0_ISP_V, ___ISR_Handler);
258isp( _txi0_isp,  TXI0_ISP_V, ___ISR_Handler);
259isp( _tei0_isp,  TEI0_ISP_V, ___ISR_Handler);
260
261/*****************************
262 * Serial interface 1
263 *****************************/
264isp( _eri1_isp,  ERI1_ISP_V, ___ISR_Handler);
265isp( _rxi1_isp,  RXI1_ISP_V, ___ISR_Handler);
266isp( _txi1_isp,  TXI1_ISP_V, ___ISR_Handler);
267isp( _tei1_isp,  TEI1_ISP_V, ___ISR_Handler);
268
269
270/******************************
271 * A/D converters
272 * ADC0-1
273 ******************************/
274isp( _adi0_isp,  ADI0_ISP_V, ___ISR_Handler);
275isp( _adi1_isp,  ADI1_ISP_V, ___ISR_Handler);
276
277
278/******************************
279 *  Data transfer controller
280 ******************************/
281isp( _dtci_isp,  DTC_ISP_V, ___ISR_Handler);
282
283
284/******************************
285 *  Counter match timer
286 ******************************/
287isp( _cmt0_isp,  CMT0_ISP_V, ___ISR_Handler);
288isp( _cmt1_isp,  CMT1_ISP_V, ___ISR_Handler);
289
290
291/******************************
292 *  Watchdog timer
293 ******************************/
294isp( _wdt_isp,  WDT_ISP_V, ___ISR_Handler);
295
296
297/******************************
298 * DRAM refresh control unit
299 * of bus state controller
300 ******************************/
301isp( _bsc_isp,  CMI_ISP_V, ___ISR_Handler);
302
303/******************************
304 *  I/O port
305 ******************************/
306isp( _oei_isp,  OEI_ISP_V, ___ISR_Handler);
307
308
309/*****************************
310 * Parity control unit of
311 * the bus state controller
312 * NOT PROVIDED IN SH-2
313 *****************************/
314/* isp( _prt_isp,  PRT_ISP_V, ___ISR_Handler); */
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