source: rtems/c/src/lib/libcpu/sh/sh7045/score/ispsh7045.c @ 0312d81f

4.104.114.84.95
Last change on this file since 0312d81f was 0312d81f, checked in by Joel Sherrill <joel.sherrill@…>, on Jan 5, 2000 at 11:01:05 PM

Fixed comment thanks to John M. Mills <jmills@…>.

  • Property mode set to 100644
File size: 10.2 KB
Line 
1/*
2 * This file contains the isp frames for the user interrupts.
3 * From these procedures __ISR_Handler is called with the vector number
4 * as argument.
5 *
6 * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
7 * some releases of gcc doesn't properly handle #pragma interrupt, if a
8 * file contains both isrs and normal functions.
9 *
10 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
11 *           Bernd Becker (becker@faw.uni-ulm.de)
12 *
13 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
14 *
15 *  This program is distributed in the hope that it will be useful,
16 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
17 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
18 *
19 *
20 *  COPYRIGHT (c) 1998.
21 *  On-Line Applications Research Corporation (OAR).
22 *  Copyright assigned to U.S. Government, 1994.
23 *
24 *  The license and distribution terms for this file may be
25 *  found in the file LICENSE in this distribution or at
26 *  http://www.OARcorp.com/rtems/license.html.
27 *
28 *      Modified to reflect isp entries for sh7045 processor:
29 *      John M. Mills (jmills@tga.com)
30 *      TGA Technologies, Inc.
31 *      100 Pinnacle Way, Suite 140
32 *      Norcross, GA 30071 U.S.A.
33 *      August, 1999
34 *
35 *      This modified file may be copied and distributed in accordance
36 *      the above-referenced license. It is provided for critique and
37 *      developmental purposes without any warranty nor representation
38 *      by the authors or by TGA Technologies.
39 *
40 *  $Id$
41 */
42
43#include <rtems/system.h>
44#include <rtems/score/shtypes.h>
45
46#if !defined (sh7045)
47#error Wrong CPU MODEL
48#endif
49
50/*
51 * This is a exception vector table
52 *
53 * It has the same structure as the actual vector table (vectab)
54 */
55
56
57/* SH-2 ISR Table */
58#include <rtems/score/ispsh7045.h>
59
60proc_ptr _Hardware_isr_Table[256]={
61_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,         /* PWRon Reset, Maual Reset,...*/
62_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
63_dummy_isp, _dummy_isp, _dummy_isp,
64_nmi_isp, _usb_isp,                               /* irq 11, 12*/
65_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
66_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
67_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
68_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
69_dummy_isp, _dummy_isp, _dummy_isp, 
70/* trapa 0 -31 */
71_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
72_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
73_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
74_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
75_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
76_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
77_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
78_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
79_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp,   /* external H/W: irq 64-71 */
80_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
81_dma0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DMAC: irq 72-87*/
82_dma1_isp, _dummy_isp, _dummy_isp, _dummy_isp,
83_dma2_isp, _dummy_isp, _dummy_isp, _dummy_isp,
84_dma3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
85_mtua0_isp, _mtub0_isp, _mtuc0_isp, _mtud0_isp, /* MTUs: irq 88-127 */
86_mtuv0_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
87_mtua1_isp, _mtub1_isp, _dummy_isp, _dummy_isp,
88_mtuv1_isp, _mtuu1_isp, _dummy_isp, _dummy_isp, 
89_mtua2_isp, _mtub2_isp, _dummy_isp, _dummy_isp,
90_mtuv2_isp, _mtuu2_isp, _dummy_isp, _dummy_isp, 
91_mtua3_isp, _mtub3_isp, _mtuc3_isp, _mtud3_isp,
92_mtuv3_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
93_mtua4_isp, _mtub4_isp, _mtuc4_isp, _mtud4_isp,
94_mtuv4_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
95_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp, /* SCI0-1: irq 128-135*/
96_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
97_adi0_isp, _adi1_isp, _dummy_isp, _dummy_isp, /* ADC0-1: irq 136-139*/
98_dtci_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DTU: irq 140-143 */
99_cmt0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* CMT0-1: irq 144-151 */
100_cmt1_isp, _dummy_isp, _dummy_isp, _dummy_isp,
101_wdt_isp, /* WDT: irq 152*/
102_bsc_isp, _dummy_isp, _dummy_isp, /* BSC: irq 153-155*/
103_oei_isp, /* I/O Port: irq 156*/
104};
105
106#define Str(a)#a
107
108/*
109 * Some versions of gcc and all version of egcs at least until egcs-1.1b
110 * are not able to handle #pragma interrupt correctly if more than 1 isr is
111 * contained in a file and when optimizing.
112 * We try to work around this problem by using the macro below.
113 */
114#define isp( name, number, func)\
115asm (".global _"Str(name)"\n\t" \
116     "_"Str(name)":       \n\t" \
117     "    mov.l r0,@-r15   \n\t" \
118     "    mov.l r1,@-r15   \n\t" \
119     "    mov.l r2,@-r15   \n\t" \
120     "    mov.l r3,@-r15   \n\t" \
121     "    mov.l r4,@-r15   \n\t" \
122     "    mov.l r5,@-r15   \n\t" \
123     "    mov.l r6,@-r15   \n\t" \
124     "    mov.l r7,@-r15   \n\t" \
125     "    mov.l r14,@-r15  \n\t" \
126     "    sts.l pr,@-r15   \n\t" \
127     "    sts.l mach,@-r15 \n\t" \
128     "    sts.l macl,@-r15 \n\t" \
129     "    mov r15,r14      \n\t" \
130     "    mov.l "Str(name)"_k, r1\n\t" \
131     "    jsr @r1           \n\t" \
132     "    mov #"Str(number)", r4\n\t" \
133     "    mov   r14,r15    \n\t" \
134     "    lds.l @r15+,macl \n\t" \
135     "    lds.l @r15+,mach \n\t" \
136     "    lds.l @r15+,pr   \n\t" \
137     "    mov.l @r15+,r14  \n\t" \
138     "    mov.l @r15+,r7   \n\t" \
139     "    mov.l @r15+,r6   \n\t" \
140     "    mov.l @r15+,r5   \n\t" \
141     "    mov.l @r15+,r4   \n\t" \
142     "    mov.l @r15+,r3   \n\t" \
143     "    mov.l @r15+,r2   \n\t" \
144     "    mov.l @r15+,r1   \n\t" \
145     "    mov.l @r15+,r0   \n\t" \
146     "    rte              \n\t" \
147     "    nop              \n\t" \
148     "    .align 2         \n\t" \
149     #name"_k: \n\t" \
150     ".long "Str(func));
151
152/************************************************
153 * Dummy interrupt service procedure for
154 * interrupts being not allowed --> Trap 34
155 ************************************************/
156asm(" .section .text
157.global __dummy_isp
158__dummy_isp:
159      mov.l r14,@-r15
160      mov   r15, r14
161      trapa #34
162      mov.l @r15+,r14
163      rte
164      nop");
165
166/*******************************************************************
167 *     ISP Vector Table for sh7045 family of processors            *
168 *******************************************************************/
169
170
171/*****************************
172 * Non maskable interrupt
173 *****************************/
174isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
175
176/*****************************
177 * User break controller
178 *****************************/
179isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
180
181/*****************************
182 *  External interrupts 0-7
183 *****************************/
184isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
185isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler);
186isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler);
187isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler);
188isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler);
189isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler);
190isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler);
191isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler);
192
193/*****************************
194 * DMA - controller
195 *****************************/
196isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
197isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler);
198isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler);
199isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler);
200
201
202/*****************************
203 * Match timer unit
204 *****************************/
205
206/*****************************
207 * Timer 0
208 *****************************/
209isp( _mtua0_isp, MTUA0_ISP_V, ___ISR_Handler);
210isp( _mtub0_isp, MTUB0_ISP_V, ___ISR_Handler);
211isp( _mtuc0_isp, MTUC0_ISP_V, ___ISR_Handler);
212isp( _mtud0_isp, MTUD0_ISP_V, ___ISR_Handler);
213isp( _mtuv0_isp, MTUV0_ISP_V, ___ISR_Handler);
214
215/*****************************
216 * Timer 1
217 *****************************/
218isp( _mtua1_isp, MTUA1_ISP_V, ___ISR_Handler);
219isp( _mtub1_isp, MTUB1_ISP_V, ___ISR_Handler);
220isp( _mtuv1_isp, MTUV1_ISP_V, ___ISR_Handler);
221isp( _mtuu1_isp, MTUU1_ISP_V, ___ISR_Handler);
222
223/*****************************
224 * Timer 2
225 *****************************/
226isp( _mtua2_isp, MTUA2_ISP_V, ___ISR_Handler);
227isp( _mtub2_isp, MTUB2_ISP_V, ___ISR_Handler);
228isp( _mtuv2_isp, MTUV2_ISP_V, ___ISR_Handler);
229isp( _mtuu2_isp, MTUU2_ISP_V, ___ISR_Handler);
230
231/*****************************
232 * Timer 3
233 *****************************/
234isp( _mtua3_isp, MTUA3_ISP_V, ___ISR_Handler);
235isp( _mtub3_isp, MTUB3_ISP_V, ___ISR_Handler);
236isp( _mtuc3_isp, MTUC3_ISP_V, ___ISR_Handler);
237isp( _mtud3_isp, MTUD3_ISP_V, ___ISR_Handler);
238isp( _mtuv3_isp, MTUV3_ISP_V, ___ISR_Handler);
239
240/*****************************
241 * Timer 4
242 *****************************/
243isp( _mtua4_isp, MTUA4_ISP_V, ___ISR_Handler);
244isp( _mtub4_isp, MTUB4_ISP_V, ___ISR_Handler);
245isp( _mtuc4_isp, MTUC4_ISP_V, ___ISR_Handler);
246isp( _mtud4_isp, MTUD4_ISP_V, ___ISR_Handler);
247isp( _mtuv4_isp, MTUV4_ISP_V, ___ISR_Handler);
248
249
250/*****************************
251 * Serial interfaces
252 *****************************/
253
254/*****************************
255 * Serial interface 0
256 *****************************/
257isp( _eri0_isp,  ERI0_ISP_V, ___ISR_Handler);
258isp( _rxi0_isp,  RXI0_ISP_V, ___ISR_Handler);
259isp( _txi0_isp,  TXI0_ISP_V, ___ISR_Handler);
260isp( _tei0_isp,  TEI0_ISP_V, ___ISR_Handler);
261
262/*****************************
263 * Serial interface 1
264 *****************************/
265isp( _eri1_isp,  ERI1_ISP_V, ___ISR_Handler);
266isp( _rxi1_isp,  RXI1_ISP_V, ___ISR_Handler);
267isp( _txi1_isp,  TXI1_ISP_V, ___ISR_Handler);
268isp( _tei1_isp,  TEI1_ISP_V, ___ISR_Handler);
269
270
271/******************************
272 * A/D converters
273 * ADC0-1
274 ******************************/
275isp( _adi0_isp,  ADI0_ISP_V, ___ISR_Handler);
276isp( _adi1_isp,  ADI1_ISP_V, ___ISR_Handler);
277
278
279/******************************
280 *  Data transfer controller
281 ******************************/
282isp( _dtci_isp,  DTC_ISP_V, ___ISR_Handler);
283
284
285/******************************
286 *  Counter match timer
287 ******************************/
288isp( _cmt0_isp,  CMT0_ISP_V, ___ISR_Handler);
289isp( _cmt1_isp,  CMT1_ISP_V, ___ISR_Handler);
290
291
292/******************************
293 *  Watchdog timer
294 ******************************/
295isp( _wdt_isp,  WDT_ISP_V, ___ISR_Handler);
296
297
298/******************************
299 * DRAM refresh control unit
300 * of bus state controller
301 ******************************/
302isp( _bsc_isp,  CMI_ISP_V, ___ISR_Handler);
303
304/******************************
305 *  I/O port
306 ******************************/
307isp( _oei_isp,  OEI_ISP_V, ___ISR_Handler);
308
309
310/*****************************
311 * Parity control unit of
312 * the bus state controller
313 * NOT PROVIDED IN SH-2
314 *****************************/
315/* isp( _prt_isp,  PRT_ISP_V, ___ISR_Handler); */
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