source: rtems/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c @ d4895132

4.104.114.84.95
Last change on this file since d4895132 was d4895132, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 1, 2002 at 10:33:53 PM

2002-11-01 Joel Sherrill <joel@…>

  • sh7045/score/cpu_asm.c: Fixed typo.
  • Property mode set to 100644
File size: 7.1 KB
Line 
1/*
2 *  This file contains the basic algorithms for all assembly code used
3 *  in an specific CPU port of RTEMS.  These algorithms must be implemented
4 *  in assembly language
5 *
6 *  NOTE:  This port uses a C file with inline assembler instructions
7 *
8 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
9 *           Bernd Becker (becker@faw.uni-ulm.de)
10 *
11 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
12 *
13 *  This program is distributed in the hope that it will be useful,
14 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
15 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
16 *
17 *
18 *  COPYRIGHT (c) 1998.
19 *  On-Line Applications Research Corporation (OAR).
20 *
21 *  The license and distribution terms for this file may be
22 *  found in the file LICENSE in this distribution or at
23 *  http://www.OARcorp.com/rtems/license.html.
24 *
25 *  $Id$
26 *
27 *  This material may be reproduced by or for the U.S. Government pursuant
28 *  to the copyright license under the clause at DFARS 252.227-7013.  This
29 *  notice must appear in all copies of this file and its derivatives.
30 *
31 */
32
33/*
34 *  This is supposed to be an assembly file.  This means that system.h
35 *  and cpu.h should not be included in a "real" cpu_asm file.  An
36 *  implementation in assembly should include "cpu_asm.h"
37 */
38
39#include <rtems/system.h>
40#include <rtems/score/cpu.h>
41#include <rtems/score/isr.h>
42#include <rtems/score/thread.h>
43#include <rtems/score/sh.h>
44
45#include <rtems/score/ispsh7045.h>
46#include <rtems/score/iosh7045.h>
47#include <rtems/score/sh_io.h>
48
49/* from cpu_isps.c */
50extern proc_ptr         _Hardware_isr_Table[];
51
52#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
53  unsigned long    *_old_stack_ptr;
54#endif
55
56register unsigned long  *stack_ptr asm("r15"); 
57
58/*
59 * sh_set_irq_priority
60 *
61 * this function sets the interrupt level of the specified interrupt
62 *
63 * parameters:
64 *             - irq : interrupt number
65 *             - prio: priority to set for this interrupt number
66 *
67 * returns:    0 if ok
68 *             -1 on error
69 */
70
71unsigned int sh_set_irq_priority( 
72  unsigned int irq, 
73  unsigned int prio )
74{
75  unsigned32 shiftcount;
76  unsigned32 prioreg;
77  unsigned16 temp16;
78  unsigned32 level;
79
80  /*
81   * first check for valid interrupt
82   */
83  if(( irq > 156) || (irq < 64) || (_Hardware_isr_Table[irq] == _dummy_isp))
84    return -1;
85  /*
86   * check for valid irq priority
87   */
88  if( prio > 15 )
89    return -1;
90
91  /*
92   * look up appropriate interrupt priority register
93   */
94  if( irq > 71)
95    {
96      irq = irq - 72;
97      shiftcount = 12 - ((irq & ~0x03) % 16);
98     
99      switch( irq / 16)
100        {
101        case 0: { prioreg = INTC_IPRC; break;}
102        case 1: { prioreg = INTC_IPRD; break;}
103        case 2: { prioreg = INTC_IPRE; break;}
104        case 3: { prioreg = INTC_IPRF; break;}
105        case 4: { prioreg = INTC_IPRG; break;}
106        case 5: { prioreg = INTC_IPRH; break;}
107        default: return -1;
108        }
109    }
110  else
111    {
112      shiftcount = 12 - 4 * ( irq % 4);
113      if( irq > 67)
114        prioreg = INTC_IPRB;
115      else
116        prioreg = INTC_IPRA;
117    }
118
119  /*
120   * Set the interrupt priority register
121   */
122  _CPU_ISR_Disable( level );
123
124  temp16 = read16( prioreg);
125  temp16 &= ~( 15 << shiftcount);
126  temp16 |= prio << shiftcount;
127  write16( temp16, prioreg);
128
129  _CPU_ISR_Enable( level );
130
131  return 0;
132}
133
134/*
135 *  _CPU_Context_save_fp_context
136 *
137 *  This routine is responsible for saving the FP context
138 *  at *fp_context_ptr.  If the point to load the FP context
139 *  from is changed then the pointer is modified by this routine.
140 *
141 *  Sometimes a macro implementation of this is in cpu.h which dereferences
142 *  the ** and a similarly named routine in this file is passed something
143 *  like a (Context_Control_fp *).  The general rule on making this decision
144 *  is to avoid writing assembly language.
145 */
146
147void _CPU_Context_save_fp(
148  void **fp_context_ptr
149)
150{
151}
152
153/*
154 *  _CPU_Context_restore_fp_context
155 *
156 *  This routine is responsible for restoring the FP context
157 *  at *fp_context_ptr.  If the point to load the FP context
158 *  from is changed then the pointer is modified by this routine.
159 *
160 *  Sometimes a macro implementation of this is in cpu.h which dereferences
161 *  the ** and a similarly named routine in this file is passed something
162 *  like a (Context_Control_fp *).  The general rule on making this decision
163 *  is to avoid writing assembly language.
164 */
165
166void _CPU_Context_restore_fp(
167  void **fp_context_ptr
168)
169{
170}
171
172/*  _CPU_Context_switch
173 *
174 *  This routine performs a normal non-FP context switch.
175 */
176
177/*  within __CPU_Context_switch:
178 *  _CPU_Context_switch
179 *  _CPU_Context_restore
180 *
181 *  This routine is generally used only to restart self in an
182 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
183 *
184 * NOTE: It should be safe not to store r4, r5
185 *
186 * NOTE: It is doubtful if r0 is really needed to be stored
187 *
188 * NOTE: gbr is added, but should not be necessary, as it is
189 *      only used globally in this port.
190 */
191
192/*
193 * FIXME: This is an ugly hack, but we wanted to avoid recalculating
194 *        the offset each time Context_Control is changed
195 */
196void __CPU_Context_switch(
197  Context_Control  *run,        /* r4 */
198  Context_Control  *heir        /* r5 */
199)
200{
201
202asm volatile("\n\
203        .global __CPU_Context_switch\n\
204__CPU_Context_switch:\n\
205\n\
206        add     %0,r4\n\
207  \n\
208        stc.l   sr,@-r4\n\
209        stc.l   gbr,@-r4\n\
210        mov.l   r0,@-r4\n\
211        mov.l   r1,@-r4\n\
212        mov.l   r2,@-r4\n\
213        mov.l   r3,@-r4\n\
214\n\
215        mov.l   r6,@-r4\n\
216        mov.l   r7,@-r4\n\
217        mov.l   r8,@-r4\n\
218        mov.l   r9,@-r4\n\
219        mov.l   r10,@-r4\n\
220        mov.l   r11,@-r4\n\
221        mov.l   r12,@-r4\n\
222        mov.l   r13,@-r4\n\
223        mov.l   r14,@-r4\n\
224        sts.l   pr,@-r4\n\
225        sts.l   mach,@-r4\n\
226        sts.l   macl,@-r4\n\
227        mov.l   r15,@-r4\n\
228\n\
229        mov     r5, r4"
230  :: "I" (sizeof(Context_Control))
231  );
232
233  asm volatile("\n\
234        .global __CPU_Context_restore\n\
235__CPU_Context_restore:\n\
236        mov.l   @r4+,r15\n\
237        lds.l   @r4+,macl\n\
238        lds.l   @r4+,mach\n\
239        lds.l   @r4+,pr\n\
240        mov.l   @r4+,r14\n\
241        mov.l   @r4+,r13\n\
242        mov.l   @r4+,r12\n\
243        mov.l   @r4+,r11\n\
244        mov.l   @r4+,r10\n\
245        mov.l   @r4+,r9\n\
246        mov.l   @r4+,r8\n\
247        mov.l   @r4+,r7\n\
248        mov.l   @r4+,r6\n\
249\n\
250        mov.l   @r4+,r3\n\
251        mov.l   @r4+,r2\n\
252        mov.l   @r4+,r1\n\
253        mov.l   @r4+,r0\n\
254        ldc.l   @r4+,gbr\n\
255        ldc.l   @r4+,sr\n\
256\n\
257        rts\n\
258        nop" );
259}
260
261/* 
262 *  This routine provides the RTEMS interrupt management.
263 */
264 
265void __ISR_Handler( unsigned32 vector)
266{
267  register unsigned32 level;
268
269  _CPU_ISR_Disable( level );
270
271  _Thread_Dispatch_disable_level++;
272
273#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
274  if( _ISR_Nest_level == 0 )
275    {
276      /* Install irq stack */
277      _old_stack_ptr = stack_ptr;
278      stack_ptr = _CPU_Interrupt_stack_high;
279    }
280
281#endif
282
283  _ISR_Nest_level++;
284
285  _CPU_ISR_Enable( level );
286
287  /* call isp */
288  if( _ISR_Vector_table[ vector])
289    (*_ISR_Vector_table[ vector ])( vector );
290
291  _CPU_ISR_Disable( level );
292
293  _ISR_Nest_level--;
294
295#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
296
297  if( _ISR_Nest_level == 0 )
298    /* restore old stack pointer */
299    stack_ptr = _old_stack_ptr; 
300#endif
301
302  _Thread_Dispatch_disable_level--;
303
304  _CPU_ISR_Enable( level );
305
306  if ( _Thread_Dispatch_disable_level == 0 )
307    {
308      if(( _Context_Switch_necessary) || (! _ISR_Signals_to_thread_executing))
309        {
310          _ISR_Signals_to_thread_executing = FALSE;
311          _Thread_Dispatch();
312        }
313  }
314}
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