source: rtems/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c @ c8f3e82

Last change on this file since c8f3e82 was f0c0491f, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 4, 2003 at 5:32:43 PM

2003-09-04 Joel Sherrill <joel@…>

  • score/cpu_asm.c: Removed incorrect statement about copyright assignment.
  • Property mode set to 100644
File size: 6.9 KB
Line 
1/*
2 *  This file contains the basic algorithms for all assembly code used
3 *  in an specific CPU port of RTEMS.  These algorithms must be implemented
4 *  in assembly language
5 *
6 *  NOTE:  This port uses a C file with inline assembler instructions
7 *
8 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
9 *           Bernd Becker (becker@faw.uni-ulm.de)
10 *
11 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
12 *
13 *  This program is distributed in the hope that it will be useful,
14 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
15 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
16 *
17 *
18 *  COPYRIGHT (c) 1998.
19 *  On-Line Applications Research Corporation (OAR).
20 *
21 *  The license and distribution terms for this file may be
22 *  found in the file LICENSE in this distribution or at
23 *  http://www.OARcorp.com/rtems/license.html.
24 *
25 *  $Id$
26 */
27
28/*
29 *  This is supposed to be an assembly file.  This means that system.h
30 *  and cpu.h should not be included in a "real" cpu_asm file.  An
31 *  implementation in assembly should include "cpu_asm.h"
32 */
33
34#include <rtems/system.h>
35#include <rtems/score/cpu.h>
36#include <rtems/score/isr.h>
37#include <rtems/score/thread.h>
38#include <rtems/score/sh.h>
39
40#include <rtems/score/ispsh7045.h>
41#include <rtems/score/iosh7045.h>
42#include <rtems/score/sh_io.h>
43
44/* from cpu_isps.c */
45extern proc_ptr         _Hardware_isr_Table[];
46
47#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
48  unsigned long    *_old_stack_ptr;
49#endif
50
51register unsigned long  *stack_ptr asm("r15"); 
52
53/*
54 * sh_set_irq_priority
55 *
56 * this function sets the interrupt level of the specified interrupt
57 *
58 * parameters:
59 *             - irq : interrupt number
60 *             - prio: priority to set for this interrupt number
61 *
62 * returns:    0 if ok
63 *             -1 on error
64 */
65
66unsigned int sh_set_irq_priority( 
67  unsigned int irq, 
68  unsigned int prio )
69{
70  unsigned32 shiftcount;
71  unsigned32 prioreg;
72  unsigned16 temp16;
73  unsigned32 level;
74
75  /*
76   * first check for valid interrupt
77   */
78  if(( irq > 156) || (irq < 64) || (_Hardware_isr_Table[irq] == _dummy_isp))
79    return -1;
80  /*
81   * check for valid irq priority
82   */
83  if( prio > 15 )
84    return -1;
85
86  /*
87   * look up appropriate interrupt priority register
88   */
89  if( irq > 71)
90    {
91      irq = irq - 72;
92      shiftcount = 12 - ((irq & ~0x03) % 16);
93     
94      switch( irq / 16)
95        {
96        case 0: { prioreg = INTC_IPRC; break;}
97        case 1: { prioreg = INTC_IPRD; break;}
98        case 2: { prioreg = INTC_IPRE; break;}
99        case 3: { prioreg = INTC_IPRF; break;}
100        case 4: { prioreg = INTC_IPRG; break;}
101        case 5: { prioreg = INTC_IPRH; break;}
102        default: return -1;
103        }
104    }
105  else
106    {
107      shiftcount = 12 - 4 * ( irq % 4);
108      if( irq > 67)
109        prioreg = INTC_IPRB;
110      else
111        prioreg = INTC_IPRA;
112    }
113
114  /*
115   * Set the interrupt priority register
116   */
117  _CPU_ISR_Disable( level );
118
119  temp16 = read16( prioreg);
120  temp16 &= ~( 15 << shiftcount);
121  temp16 |= prio << shiftcount;
122  write16( temp16, prioreg);
123
124  _CPU_ISR_Enable( level );
125
126  return 0;
127}
128
129/*
130 *  _CPU_Context_save_fp_context
131 *
132 *  This routine is responsible for saving the FP context
133 *  at *fp_context_ptr.  If the point to load the FP context
134 *  from is changed then the pointer is modified by this routine.
135 *
136 *  Sometimes a macro implementation of this is in cpu.h which dereferences
137 *  the ** and a similarly named routine in this file is passed something
138 *  like a (Context_Control_fp *).  The general rule on making this decision
139 *  is to avoid writing assembly language.
140 */
141
142void _CPU_Context_save_fp(
143  void **fp_context_ptr
144)
145{
146}
147
148/*
149 *  _CPU_Context_restore_fp_context
150 *
151 *  This routine is responsible for restoring the FP context
152 *  at *fp_context_ptr.  If the point to load the FP context
153 *  from is changed then the pointer is modified by this routine.
154 *
155 *  Sometimes a macro implementation of this is in cpu.h which dereferences
156 *  the ** and a similarly named routine in this file is passed something
157 *  like a (Context_Control_fp *).  The general rule on making this decision
158 *  is to avoid writing assembly language.
159 */
160
161void _CPU_Context_restore_fp(
162  void **fp_context_ptr
163)
164{
165}
166
167/*  _CPU_Context_switch
168 *
169 *  This routine performs a normal non-FP context switch.
170 */
171
172/*  within __CPU_Context_switch:
173 *  _CPU_Context_switch
174 *  _CPU_Context_restore
175 *
176 *  This routine is generally used only to restart self in an
177 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
178 *
179 * NOTE: It should be safe not to store r4, r5
180 *
181 * NOTE: It is doubtful if r0 is really needed to be stored
182 *
183 * NOTE: gbr is added, but should not be necessary, as it is
184 *      only used globally in this port.
185 */
186
187/*
188 * FIXME: This is an ugly hack, but we wanted to avoid recalculating
189 *        the offset each time Context_Control is changed
190 */
191void __CPU_Context_switch(
192  Context_Control  *run,        /* r4 */
193  Context_Control  *heir        /* r5 */
194)
195{
196
197asm volatile("\n\
198        .global __CPU_Context_switch\n\
199__CPU_Context_switch:\n\
200\n\
201        add     %0,r4\n\
202  \n\
203        stc.l   sr,@-r4\n\
204        stc.l   gbr,@-r4\n\
205        mov.l   r0,@-r4\n\
206        mov.l   r1,@-r4\n\
207        mov.l   r2,@-r4\n\
208        mov.l   r3,@-r4\n\
209\n\
210        mov.l   r6,@-r4\n\
211        mov.l   r7,@-r4\n\
212        mov.l   r8,@-r4\n\
213        mov.l   r9,@-r4\n\
214        mov.l   r10,@-r4\n\
215        mov.l   r11,@-r4\n\
216        mov.l   r12,@-r4\n\
217        mov.l   r13,@-r4\n\
218        mov.l   r14,@-r4\n\
219        sts.l   pr,@-r4\n\
220        sts.l   mach,@-r4\n\
221        sts.l   macl,@-r4\n\
222        mov.l   r15,@-r4\n\
223\n\
224        mov     r5, r4"
225  :: "I" (sizeof(Context_Control))
226  );
227
228  asm volatile("\n\
229        .global __CPU_Context_restore\n\
230__CPU_Context_restore:\n\
231        mov.l   @r4+,r15\n\
232        lds.l   @r4+,macl\n\
233        lds.l   @r4+,mach\n\
234        lds.l   @r4+,pr\n\
235        mov.l   @r4+,r14\n\
236        mov.l   @r4+,r13\n\
237        mov.l   @r4+,r12\n\
238        mov.l   @r4+,r11\n\
239        mov.l   @r4+,r10\n\
240        mov.l   @r4+,r9\n\
241        mov.l   @r4+,r8\n\
242        mov.l   @r4+,r7\n\
243        mov.l   @r4+,r6\n\
244\n\
245        mov.l   @r4+,r3\n\
246        mov.l   @r4+,r2\n\
247        mov.l   @r4+,r1\n\
248        mov.l   @r4+,r0\n\
249        ldc.l   @r4+,gbr\n\
250        ldc.l   @r4+,sr\n\
251\n\
252        rts\n\
253        nop" );
254}
255
256/* 
257 *  This routine provides the RTEMS interrupt management.
258 */
259 
260void __ISR_Handler( unsigned32 vector)
261{
262  register unsigned32 level;
263
264  _CPU_ISR_Disable( level );
265
266  _Thread_Dispatch_disable_level++;
267
268#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
269  if( _ISR_Nest_level == 0 )
270    {
271      /* Install irq stack */
272      _old_stack_ptr = stack_ptr;
273      stack_ptr = _CPU_Interrupt_stack_high;
274    }
275
276#endif
277
278  _ISR_Nest_level++;
279
280  _CPU_ISR_Enable( level );
281
282  /* call isp */
283  if( _ISR_Vector_table[ vector])
284    (*_ISR_Vector_table[ vector ])( vector );
285
286  _CPU_ISR_Disable( level );
287
288  _Thread_Dispatch_disable_level--;
289
290  _ISR_Nest_level--;
291
292#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
293
294  if( _ISR_Nest_level == 0 )
295    /* restore old stack pointer */
296    stack_ptr = _old_stack_ptr; 
297#endif
298
299  _CPU_ISR_Enable( level );
300
301  if ( _ISR_Nest_level )
302    return;
303
304  if ( _Thread_Dispatch_disable_level ) {
305    _ISR_Signals_to_thread_executing = FALSE;
306    return;
307  }
308
309  if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
310    _ISR_Signals_to_thread_executing = FALSE;
311    _Thread_Dispatch();
312  }
313}
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