source: rtems/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c @ 7ae5125

4.104.114.84.95
Last change on this file since 7ae5125 was 7ae5125, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 16, 2001 at 9:08:28 PM

2001-08-10 Radzislaw Galler <rgaller@…>

  • score/cpu_asm.c (sh_set_irq_priority): Changed interrupt vector number range check and handling of interrupt priority regs to conform SH2 specs.
  • sci/sci_termios.c: New file.
  • include/sci_termios.h: New file.
  • include/Makefile.am (EXTRA_DIST): Added sci_termios.h. (include_sh_HEADERS): Added sci_termios.h.
  • score/ispsh7045.c (isp): Calling an ISR with immediate argument casued negative sign extension for vector numbers of 128 and above. This was fixed.
  • sci/sci.c: Cleaned initialization of SCI registers; added necessary setup for new TERMIOS console cooperation
  • Property mode set to 100644
File size: 7.0 KB
Line 
1/*
2 *  This file contains the basic algorithms for all assembly code used
3 *  in an specific CPU port of RTEMS.  These algorithms must be implemented
4 *  in assembly language
5 *
6 *  NOTE:  This port uses a C file with inline assembler instructions
7 *
8 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
9 *           Bernd Becker (becker@faw.uni-ulm.de)
10 *
11 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
12 *
13 *  This program is distributed in the hope that it will be useful,
14 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
15 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
16 *
17 *
18 *  COPYRIGHT (c) 1998.
19 *  On-Line Applications Research Corporation (OAR).
20 *  Copyright assigned to U.S. Government, 1994.
21 *
22 *  The license and distribution terms for this file may be
23 *  found in the file LICENSE in this distribution or at
24 *  http://www.OARcorp.com/rtems/license.html.
25 *
26 *  $Id$
27 *
28 *  This material may be reproduced by or for the U.S. Government pursuant
29 *  to the copyright license under the clause at DFARS 252.227-7013.  This
30 *  notice must appear in all copies of this file and its derivatives.
31 *
32 */
33
34/*
35 *  This is supposed to be an assembly file.  This means that system.h
36 *  and cpu.h should not be included in a "real" cpu_asm file.  An
37 *  implementation in assembly should include "cpu_asm.h"
38 */
39
40#include <rtems/system.h>
41#include <rtems/score/cpu.h>
42#include <rtems/score/isr.h>
43#include <rtems/score/thread.h>
44#include <rtems/score/sh.h>
45
46#include <rtems/score/ispsh7045.h>
47#include <rtems/score/iosh7045.h>
48#include <rtems/score/sh_io.h>
49
50/* from cpu_isps.c */
51extern proc_ptr         _Hardware_isr_Table[];
52
53#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
54  unsigned long    *_old_stack_ptr;
55#endif
56
57register unsigned long  *stack_ptr asm("r15"); 
58
59/*
60 * sh_set_irq_priority
61 *
62 * this function sets the interrupt level of the specified interrupt
63 *
64 * parameters:
65 *             - irq : interrupt number
66 *             - prio: priority to set for this interrupt number
67 *
68 * returns:    0 if ok
69 *             -1 on error
70 */
71
72unsigned int sh_set_irq_priority( 
73  unsigned int irq, 
74  unsigned int prio )
75{
76  unsigned32 shiftcount;
77  unsigned32 prioreg;
78  unsigned16 temp16;
79  unsigned32 level;
80
81  /*
82   * first check for valid interrupt
83   */
84  if(( irq > 156) || (irq < 64) || (_Hardware_isr_Table[irq] == _dummy_isp))
85    return -1;
86  /*
87   * check for valid irq priority
88   */
89  if( prio > 15 )
90    return -1;
91
92  /*
93   * look up appropriate interrupt priority register
94   */
95  if( irq > 71)
96    {
97      irq = irq - 72;
98      shiftcount = 12 - ((irq & ~0x03) % 16);
99     
100      switch( irq / 16)
101        {
102        case 0: { prioreg = INTC_IPRC; break;}
103        case 1: { prioreg = INTC_IPRD; break;}
104        case 2: { prioreg = INTC_IPRE; break;}
105        case 3: { prioreg = INTC_IPRF; break;}
106        case 4: { prioreg = INTC_IPRG; break;}
107        case 5: { prioreg = INTC_IPRH; break;}
108        default: return -1;
109        }
110    }
111  else
112    {
113      shiftcount = 12 - 4 * ( irq % 4);
114      if( irq > 67)
115        prioreg = INTC_IPRB;
116      else
117        prioreg = INTC_IPRA;
118    }
119
120  /*
121   * Set the interrupt priority register
122   */
123  _CPU_ISR_Disable( level );
124
125  temp16 = read16( prioreg);
126  temp16 &= ~( 15 << shiftcount);
127  temp16 |= prio << shiftcount;
128  write16( temp16, prioreg);
129
130  _CPU_ISR_Enable( level );
131
132  return 0;
133}
134
135/*
136 *  _CPU_Context_save_fp_context
137 *
138 *  This routine is responsible for saving the FP context
139 *  at *fp_context_ptr.  If the point to load the FP context
140 *  from is changed then the pointer is modified by this routine.
141 *
142 *  Sometimes a macro implementation of this is in cpu.h which dereferences
143 *  the ** and a similarly named routine in this file is passed something
144 *  like a (Context_Control_fp *).  The general rule on making this decision
145 *  is to avoid writing assembly language.
146 */
147
148void _CPU_Context_save_fp(
149  void **fp_context_ptr
150)
151{
152}
153
154/*
155 *  _CPU_Context_restore_fp_context
156 *
157 *  This routine is responsible for restoring the FP context
158 *  at *fp_context_ptr.  If the point to load the FP context
159 *  from is changed then the pointer is modified by this routine.
160 *
161 *  Sometimes a macro implementation of this is in cpu.h which dereferences
162 *  the ** and a similarly named routine in this file is passed something
163 *  like a (Context_Control_fp *).  The general rule on making this decision
164 *  is to avoid writing assembly language.
165 */
166
167void _CPU_Context_restore_fp(
168  void **fp_context_ptr
169)
170{
171}
172
173/*  _CPU_Context_switch
174 *
175 *  This routine performs a normal non-FP context switch.
176 */
177
178/*  within __CPU_Context_switch:
179 *  _CPU_Context_switch
180 *  _CPU_Context_restore
181 *
182 *  This routine is generally used only to restart self in an
183 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
184 *
185 * NOTE: It should be safe not to store r4, r5
186 *
187 * NOTE: It is doubtful if r0 is really needed to be stored
188 *
189 * NOTE: gbr is added, but should not be necessary, as it is
190 *      only used globally in this port.
191 */
192
193/*
194 * FIXME: This is an ugly hack, but we wanted to avoid recalculating
195 *        the offset each time Context_Control is changed
196 */
197void __CPU_Context_switch(
198  Context_Control  *run,        /* r4 */
199  Context_Control  *heir        /* r5 */
200)
201{
202
203asm volatile("
204        .global __CPU_Context_switch
205__CPU_Context_switch:
206
207        add     %0,r4
208 
209        stc.l   sr,@-r4
210        stc.l   gbr,@-r4
211        mov.l   r0,@-r4
212        mov.l   r1,@-r4
213        mov.l   r2,@-r4
214        mov.l   r3,@-r4
215
216        mov.l   r6,@-r4
217        mov.l   r7,@-r4
218        mov.l   r8,@-r4
219        mov.l   r9,@-r4
220        mov.l   r10,@-r4
221        mov.l   r11,@-r4
222        mov.l   r12,@-r4
223        mov.l   r13,@-r4
224        mov.l   r14,@-r4
225        sts.l   pr,@-r4
226        sts.l   mach,@-r4
227        sts.l   macl,@-r4
228        mov.l   r15,@-r4
229
230        mov     r5, r4"
231  :: "I" (sizeof(Context_Control))
232  );
233
234  asm volatile("
235        .global __CPU_Context_restore
236__CPU_Context_restore:
237        mov.l   @r4+,r15
238        lds.l   @r4+,macl
239        lds.l   @r4+,mach
240        lds.l   @r4+,pr
241        mov.l   @r4+,r14
242        mov.l   @r4+,r13
243        mov.l   @r4+,r12
244        mov.l   @r4+,r11
245        mov.l   @r4+,r10
246        mov.l   @r4+,r9
247        mov.l   @r4+,r8
248        mov.l   @r4+,r7
249        mov.l   @r4+,r6
250
251        mov.l   @r4+,r3
252        mov.l   @r4+,r2
253        mov.l   @r4+,r1
254        mov.l   @r4+,r0
255        ldc.l   @r4+,gbr
256        ldc.l   @r4+,sr
257
258        rts
259        nop" );
260}
261
262/* 
263 *  This routine provides the RTEMS interrupt management.
264 */
265 
266void __ISR_Handler( unsigned32 vector)
267{
268  register unsigned32 level;
269
270  _CPU_ISR_Disable( level );
271
272  _Thread_Dispatch_disable_level++;
273
274#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
275  if( _ISR_Nest_level == 0 )
276    {
277      /* Install irq stack */
278      _old_stack_ptr = stack_ptr;
279      stack_ptr = _CPU_Interrupt_stack_high;
280    }
281
282#endif
283
284  _ISR_Nest_level++;
285
286  _CPU_ISR_Enable( level );
287
288  /* call isp */
289  if( _ISR_Vector_table[ vector])
290    (*_ISR_Vector_table[ vector ])( vector );
291
292  _CPU_ISR_Disable( level );
293
294  _ISR_Nest_level--;
295
296#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
297
298  if( _ISR_Nest_level == 0 )
299    /* restore old stack pointer */
300    stack_ptr = _old_stack_ptr; 
301#endif
302
303  _Thread_Dispatch_disable_level--;
304
305  _CPU_ISR_Enable( level );
306
307  if ( _Thread_Dispatch_disable_level == 0 )
308    {
309      if(( _Context_Switch_necessary) || (! _ISR_Signals_to_thread_executing))
310        {
311          _ISR_Signals_to_thread_executing = FALSE;
312          _Thread_Dispatch();
313        }
314  }
315}
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