[50cf94da] | 1 | /* |
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| 2 | * This file contains the basic algorithms for all assembly code used |
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| 3 | * in an specific CPU port of RTEMS. These algorithms must be implemented |
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| 4 | * in assembly language |
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| 5 | * |
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| 6 | * NOTE: This port uses a C file with inline assembler instructions |
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| 7 | * |
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| 8 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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| 9 | * Bernd Becker (becker@faw.uni-ulm.de) |
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| 10 | * |
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| 11 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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| 12 | * |
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| 13 | * This program is distributed in the hope that it will be useful, |
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| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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| 16 | * |
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| 17 | * |
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| 18 | * COPYRIGHT (c) 1998. |
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| 19 | * On-Line Applications Research Corporation (OAR). |
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| 20 | * |
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| 21 | * The license and distribution terms for this file may be |
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| 22 | * found in the file LICENSE in this distribution or at |
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| 23 | * http://www.OARcorp.com/rtems/license.html. |
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| 24 | * |
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| 25 | * $Id$ |
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| 26 | * |
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| 27 | * This material may be reproduced by or for the U.S. Government pursuant |
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| 28 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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| 29 | * notice must appear in all copies of this file and its derivatives. |
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| 30 | * |
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| 31 | */ |
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| 32 | |
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| 33 | /* |
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| 34 | * This is supposed to be an assembly file. This means that system.h |
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| 35 | * and cpu.h should not be included in a "real" cpu_asm file. An |
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| 36 | * implementation in assembly should include "cpu_asm.h" |
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| 37 | */ |
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| 38 | |
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| 39 | #include <rtems/system.h> |
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| 40 | #include <rtems/score/cpu.h> |
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| 41 | #include <rtems/score/isr.h> |
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| 42 | #include <rtems/score/thread.h> |
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| 43 | #include <rtems/score/sh.h> |
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[4a238002] | 44 | |
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| 45 | #include <rtems/score/ispsh7045.h> |
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| 46 | #include <rtems/score/iosh7045.h> |
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| 47 | #include <rtems/score/sh_io.h> |
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[50cf94da] | 48 | |
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| 49 | /* from cpu_isps.c */ |
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| 50 | extern proc_ptr _Hardware_isr_Table[]; |
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| 51 | |
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| 52 | #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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| 53 | unsigned long *_old_stack_ptr; |
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| 54 | #endif |
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| 55 | |
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| 56 | register unsigned long *stack_ptr asm("r15"); |
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| 57 | |
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| 58 | /* |
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| 59 | * sh_set_irq_priority |
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| 60 | * |
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| 61 | * this function sets the interrupt level of the specified interrupt |
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| 62 | * |
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| 63 | * parameters: |
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| 64 | * - irq : interrupt number |
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| 65 | * - prio: priority to set for this interrupt number |
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| 66 | * |
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| 67 | * returns: 0 if ok |
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| 68 | * -1 on error |
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| 69 | */ |
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| 70 | |
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| 71 | unsigned int sh_set_irq_priority( |
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| 72 | unsigned int irq, |
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| 73 | unsigned int prio ) |
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| 74 | { |
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| 75 | unsigned32 shiftcount; |
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| 76 | unsigned32 prioreg; |
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| 77 | unsigned16 temp16; |
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| 78 | unsigned32 level; |
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| 79 | |
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| 80 | /* |
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| 81 | * first check for valid interrupt |
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| 82 | */ |
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[7ae5125] | 83 | if(( irq > 156) || (irq < 64) || (_Hardware_isr_Table[irq] == _dummy_isp)) |
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[50cf94da] | 84 | return -1; |
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| 85 | /* |
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| 86 | * check for valid irq priority |
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| 87 | */ |
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| 88 | if( prio > 15 ) |
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| 89 | return -1; |
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| 90 | |
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| 91 | /* |
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| 92 | * look up appropriate interrupt priority register |
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| 93 | */ |
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| 94 | if( irq > 71) |
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| 95 | { |
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| 96 | irq = irq - 72; |
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| 97 | shiftcount = 12 - ((irq & ~0x03) % 16); |
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| 98 | |
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| 99 | switch( irq / 16) |
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| 100 | { |
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| 101 | case 0: { prioreg = INTC_IPRC; break;} |
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| 102 | case 1: { prioreg = INTC_IPRD; break;} |
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| 103 | case 2: { prioreg = INTC_IPRE; break;} |
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[7ae5125] | 104 | case 3: { prioreg = INTC_IPRF; break;} |
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| 105 | case 4: { prioreg = INTC_IPRG; break;} |
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| 106 | case 5: { prioreg = INTC_IPRH; break;} |
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[50cf94da] | 107 | default: return -1; |
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| 108 | } |
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| 109 | } |
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| 110 | else |
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| 111 | { |
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| 112 | shiftcount = 12 - 4 * ( irq % 4); |
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| 113 | if( irq > 67) |
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| 114 | prioreg = INTC_IPRB; |
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| 115 | else |
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| 116 | prioreg = INTC_IPRA; |
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| 117 | } |
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| 118 | |
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| 119 | /* |
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| 120 | * Set the interrupt priority register |
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| 121 | */ |
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| 122 | _CPU_ISR_Disable( level ); |
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| 123 | |
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| 124 | temp16 = read16( prioreg); |
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| 125 | temp16 &= ~( 15 << shiftcount); |
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| 126 | temp16 |= prio << shiftcount; |
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| 127 | write16( temp16, prioreg); |
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| 128 | |
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| 129 | _CPU_ISR_Enable( level ); |
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| 130 | |
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| 131 | return 0; |
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| 132 | } |
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| 133 | |
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| 134 | /* |
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| 135 | * _CPU_Context_save_fp_context |
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| 136 | * |
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| 137 | * This routine is responsible for saving the FP context |
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| 138 | * at *fp_context_ptr. If the point to load the FP context |
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| 139 | * from is changed then the pointer is modified by this routine. |
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| 140 | * |
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| 141 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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| 142 | * the ** and a similarly named routine in this file is passed something |
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| 143 | * like a (Context_Control_fp *). The general rule on making this decision |
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| 144 | * is to avoid writing assembly language. |
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| 145 | */ |
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| 146 | |
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| 147 | void _CPU_Context_save_fp( |
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| 148 | void **fp_context_ptr |
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| 149 | ) |
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| 150 | { |
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| 151 | } |
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| 152 | |
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| 153 | /* |
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| 154 | * _CPU_Context_restore_fp_context |
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| 155 | * |
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| 156 | * This routine is responsible for restoring the FP context |
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| 157 | * at *fp_context_ptr. If the point to load the FP context |
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| 158 | * from is changed then the pointer is modified by this routine. |
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| 159 | * |
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| 160 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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| 161 | * the ** and a similarly named routine in this file is passed something |
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| 162 | * like a (Context_Control_fp *). The general rule on making this decision |
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| 163 | * is to avoid writing assembly language. |
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| 164 | */ |
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| 165 | |
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| 166 | void _CPU_Context_restore_fp( |
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| 167 | void **fp_context_ptr |
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| 168 | ) |
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| 169 | { |
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| 170 | } |
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| 171 | |
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| 172 | /* _CPU_Context_switch |
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| 173 | * |
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| 174 | * This routine performs a normal non-FP context switch. |
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| 175 | */ |
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| 176 | |
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| 177 | /* within __CPU_Context_switch: |
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| 178 | * _CPU_Context_switch |
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| 179 | * _CPU_Context_restore |
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| 180 | * |
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| 181 | * This routine is generally used only to restart self in an |
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| 182 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
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| 183 | * |
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| 184 | * NOTE: It should be safe not to store r4, r5 |
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| 185 | * |
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| 186 | * NOTE: It is doubtful if r0 is really needed to be stored |
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| 187 | * |
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| 188 | * NOTE: gbr is added, but should not be necessary, as it is |
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| 189 | * only used globally in this port. |
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| 190 | */ |
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| 191 | |
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| 192 | /* |
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| 193 | * FIXME: This is an ugly hack, but we wanted to avoid recalculating |
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| 194 | * the offset each time Context_Control is changed |
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| 195 | */ |
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| 196 | void __CPU_Context_switch( |
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| 197 | Context_Control *run, /* r4 */ |
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| 198 | Context_Control *heir /* r5 */ |
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| 199 | ) |
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| 200 | { |
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| 201 | |
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[fa5a451] | 202 | asm volatile("\n\ |
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| 203 | .global __CPU_Context_switch\n\ |
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| 204 | __CPU_Context_switch:\n\ |
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| 205 | \n\ |
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| 206 | add %0,r4\n\ |
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| 207 | \n\ |
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| 208 | stc.l sr,@-r4\n\ |
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| 209 | stc.l gbr,@-r4\n\ |
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| 210 | mov.l r0,@-r4\n\ |
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| 211 | mov.l r1,@-r4\n\ |
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| 212 | mov.l r2,@-r4\n\ |
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| 213 | mov.l r3,@-r4\n\ |
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| 214 | \n\ |
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| 215 | mov.l r6,@-r4\n\ |
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| 216 | mov.l r7,@-r4\n\ |
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| 217 | mov.l r8,@-r4\n\ |
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| 218 | mov.l r9,@-r4\n\ |
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| 219 | mov.l r10,@-r4\n\ |
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| 220 | mov.l r11,@-r4\n\ |
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| 221 | mov.l r12,@-r4\n\ |
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| 222 | mov.l r13,@-r4\n\ |
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| 223 | mov.l r14,@-r4\n\ |
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| 224 | sts.l pr,@-r4\n\ |
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| 225 | sts.l mach,@-r4\n\ |
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| 226 | sts.l macl,@-r4\n\ |
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| 227 | mov.l r15,@-r4\n\ |
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| 228 | \n\ |
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[d4895132] | 229 | mov r5, r4" |
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[50cf94da] | 230 | :: "I" (sizeof(Context_Control)) |
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| 231 | ); |
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| 232 | |
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[fa5a451] | 233 | asm volatile("\n\ |
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| 234 | .global __CPU_Context_restore\n\ |
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| 235 | __CPU_Context_restore:\n\ |
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| 236 | mov.l @r4+,r15\n\ |
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| 237 | lds.l @r4+,macl\n\ |
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| 238 | lds.l @r4+,mach\n\ |
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| 239 | lds.l @r4+,pr\n\ |
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| 240 | mov.l @r4+,r14\n\ |
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| 241 | mov.l @r4+,r13\n\ |
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| 242 | mov.l @r4+,r12\n\ |
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| 243 | mov.l @r4+,r11\n\ |
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| 244 | mov.l @r4+,r10\n\ |
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| 245 | mov.l @r4+,r9\n\ |
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| 246 | mov.l @r4+,r8\n\ |
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| 247 | mov.l @r4+,r7\n\ |
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| 248 | mov.l @r4+,r6\n\ |
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| 249 | \n\ |
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| 250 | mov.l @r4+,r3\n\ |
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| 251 | mov.l @r4+,r2\n\ |
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| 252 | mov.l @r4+,r1\n\ |
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| 253 | mov.l @r4+,r0\n\ |
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| 254 | ldc.l @r4+,gbr\n\ |
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| 255 | ldc.l @r4+,sr\n\ |
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| 256 | \n\ |
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| 257 | rts\n\ |
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[50cf94da] | 258 | nop" ); |
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| 259 | } |
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| 260 | |
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| 261 | /* |
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| 262 | * This routine provides the RTEMS interrupt management. |
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| 263 | */ |
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| 264 | |
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| 265 | void __ISR_Handler( unsigned32 vector) |
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| 266 | { |
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| 267 | register unsigned32 level; |
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| 268 | |
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| 269 | _CPU_ISR_Disable( level ); |
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| 270 | |
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| 271 | _Thread_Dispatch_disable_level++; |
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| 272 | |
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| 273 | #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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| 274 | if( _ISR_Nest_level == 0 ) |
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| 275 | { |
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| 276 | /* Install irq stack */ |
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| 277 | _old_stack_ptr = stack_ptr; |
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| 278 | stack_ptr = _CPU_Interrupt_stack_high; |
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| 279 | } |
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| 280 | |
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| 281 | #endif |
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| 282 | |
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| 283 | _ISR_Nest_level++; |
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| 284 | |
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| 285 | _CPU_ISR_Enable( level ); |
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| 286 | |
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| 287 | /* call isp */ |
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| 288 | if( _ISR_Vector_table[ vector]) |
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| 289 | (*_ISR_Vector_table[ vector ])( vector ); |
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| 290 | |
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| 291 | _CPU_ISR_Disable( level ); |
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| 292 | |
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| 293 | _ISR_Nest_level--; |
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| 294 | |
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| 295 | #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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| 296 | |
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| 297 | if( _ISR_Nest_level == 0 ) |
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| 298 | /* restore old stack pointer */ |
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| 299 | stack_ptr = _old_stack_ptr; |
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| 300 | #endif |
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| 301 | |
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| 302 | _Thread_Dispatch_disable_level--; |
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| 303 | |
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| 304 | _CPU_ISR_Enable( level ); |
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| 305 | |
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| 306 | if ( _Thread_Dispatch_disable_level == 0 ) |
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| 307 | { |
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| 308 | if(( _Context_Switch_necessary) || (! _ISR_Signals_to_thread_executing)) |
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| 309 | { |
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| 310 | _ISR_Signals_to_thread_executing = FALSE; |
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| 311 | _Thread_Dispatch(); |
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| 312 | } |
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| 313 | } |
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| 314 | } |
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