[3a5fec8] | 1 | /* |
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| 2 | * Termios console serial driver. |
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| 3 | * |
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| 4 | * Based on SCI driver by Ralf Corsepius and John M. Mills |
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| 5 | * |
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| 6 | * Author: Radzislaw Galler <rgaller@et.put.poznan.pl> |
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| 7 | * |
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| 8 | * COPYRIGHT (c) 1989-2001. |
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| 9 | * On-Line Applications Research Corporation (OAR). |
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| 10 | * |
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| 11 | * The license and distribution terms for this file may be |
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| 12 | * found in the file LICENSE in this distribution or at |
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[85a18cc] | 13 | * http://www.rtems.com/license/LICENSE. |
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[3a5fec8] | 14 | * |
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| 15 | * $Id$ |
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| 16 | * |
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| 17 | */ |
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| 18 | |
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| 19 | #include <bsp.h> |
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| 20 | #include <stdlib.h> |
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| 21 | |
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| 22 | #include <libchip/serial.h> |
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| 23 | #include <libchip/sersupp.h> |
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| 24 | |
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| 25 | #include <rtems/libio.h> |
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[c0a200e] | 26 | #include <rtems/iosupp.h> |
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[3a5fec8] | 27 | |
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| 28 | #include <rtems/score/sh_io.h> |
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| 29 | #include <rtems/score/ispsh7045.h> |
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| 30 | #include <rtems/score/iosh7045.h> |
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| 31 | |
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| 32 | #include <sh/sh7_sci.h> |
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| 33 | #include <sh/sh7_pfc.h> |
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| 34 | #include <sh/sci_termios.h> |
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| 35 | |
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| 36 | |
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[3906b3ea] | 37 | /* |
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[3a5fec8] | 38 | * Some handy macros |
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| 39 | */ |
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| 40 | #define SH_SCI_REG_DATA(_data, _minor, _register) \ |
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[7431fdc] | 41 | (write8(_data, Console_Port_Tbl[_minor]->ulCtrlPort1 + (_register))) |
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[3a5fec8] | 42 | |
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| 43 | #define SH_SCI_REG_FLAG(_flag, _minor, _register) \ |
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[7431fdc] | 44 | (write8(read8(Console_Port_Tbl[_minor]->ulCtrlPort1 + (_register)) | (_flag), \ |
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| 45 | Console_Port_Tbl[_minor]->ulCtrlPort1 + (_register))) |
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[3a5fec8] | 46 | |
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| 47 | #define SH_SCI_REG_MASK(_flag, _minor, _register) \ |
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[7431fdc] | 48 | (write8(read8(Console_Port_Tbl[_minor]->ulCtrlPort1 + (_register)) & ~(_flag),\ |
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| 49 | Console_Port_Tbl[_minor]->ulCtrlPort1 + (_register))) |
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[3a5fec8] | 50 | |
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| 51 | /* |
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| 52 | * NOTE: Some SH variants have 3 sci devices |
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| 53 | */ |
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[3906b3ea] | 54 | |
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[3a5fec8] | 55 | #define SCI_MINOR_DEVICES 2 |
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| 56 | |
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| 57 | |
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[3906b3ea] | 58 | /* |
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| 59 | * Automatically generated function imported from scitab.rel |
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[3a5fec8] | 60 | */ |
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| 61 | extern int _sci_get_brparms( |
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| 62 | tcflag_t cflag, |
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| 63 | unsigned char *smr, |
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[2afd852a] | 64 | unsigned char *brr |
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| 65 | ); |
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[3a5fec8] | 66 | |
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[3906b3ea] | 67 | /* |
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[3a5fec8] | 68 | * Translate termios flags into SCI settings |
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| 69 | */ |
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[3906b3ea] | 70 | int sh_sci_set_attributes( |
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[3a5fec8] | 71 | int minor, |
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| 72 | const struct termios *t |
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| 73 | ) |
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| 74 | { |
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[2afd852a] | 75 | uint8_t smr; |
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| 76 | uint8_t brr; |
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[3a5fec8] | 77 | int a; |
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[3906b3ea] | 78 | |
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[3a5fec8] | 79 | tcflag_t c_cflag = t->c_cflag; |
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| 80 | |
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[2afd852a] | 81 | if ( c_cflag & CBAUD ) { |
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[3a5fec8] | 82 | if ( _sci_get_brparms( c_cflag, &smr, &brr ) != 0 ) |
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| 83 | return -1 ; |
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| 84 | } |
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[3906b3ea] | 85 | |
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[2afd852a] | 86 | if ( c_cflag & CSIZE ) { |
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[3a5fec8] | 87 | if ( c_cflag & CS8 ) |
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| 88 | smr &= ~SCI_SEVEN_BIT_DATA; |
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| 89 | else if ( c_cflag & CS7 ) |
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| 90 | smr |= SCI_SEVEN_BIT_DATA; |
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| 91 | else |
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| 92 | return -1 ; |
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| 93 | } |
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| 94 | |
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| 95 | if ( c_cflag & CSTOPB ) |
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| 96 | smr |= SCI_STOP_BITS_2; |
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| 97 | else |
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| 98 | smr &= ~SCI_STOP_BITS_2; |
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| 99 | |
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| 100 | if ( c_cflag & PARENB ) |
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| 101 | smr |= SCI_PARITY_ON ; |
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| 102 | else |
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| 103 | smr &= ~SCI_PARITY_ON ; |
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| 104 | |
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| 105 | if ( c_cflag & PARODD ) |
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| 106 | smr |= SCI_ODD_PARITY ; |
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| 107 | else |
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| 108 | smr &= ~SCI_ODD_PARITY; |
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| 109 | |
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| 110 | SH_SCI_REG_MASK((SCI_RE | SCI_TE), minor, SCI_SCR); |
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[3906b3ea] | 111 | |
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[3a5fec8] | 112 | SH_SCI_REG_DATA(smr, minor, SCI_SMR); |
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| 113 | SH_SCI_REG_DATA(brr, minor, SCI_BRR); |
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[3906b3ea] | 114 | |
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[2afd852a] | 115 | for (a=0; a < 10000L; a++) { /* Delay one bit */ |
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[3d0af835] | 116 | __asm__ volatile ("nop"); |
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[3a5fec8] | 117 | } |
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| 118 | |
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| 119 | SH_SCI_REG_FLAG((SCI_RE | SCI_TE), minor, SCI_SCR); |
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[3906b3ea] | 120 | |
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[3a5fec8] | 121 | return 0; |
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| 122 | } |
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| 123 | |
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[3906b3ea] | 124 | /* |
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[3a5fec8] | 125 | * Receive-data-full ISR |
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| 126 | * |
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[3906b3ea] | 127 | * The same routine for all interrupt sources of the same type. |
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[3a5fec8] | 128 | */ |
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| 129 | rtems_isr sh_sci_rx_isr(rtems_vector_number vector) |
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| 130 | { |
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| 131 | int minor; |
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[3906b3ea] | 132 | |
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[2afd852a] | 133 | for (minor = 0; minor < Console_Port_Count; minor++) { |
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[7431fdc] | 134 | if (Console_Port_Tbl[minor]->ulIntVector == vector) { |
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[2afd852a] | 135 | char temp8; |
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[3906b3ea] | 136 | |
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[3a5fec8] | 137 | /* |
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| 138 | * FIXME: error handling should be added |
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| 139 | */ |
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[7431fdc] | 140 | temp8 = read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_RDR); |
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[3a5fec8] | 141 | |
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| 142 | rtems_termios_enqueue_raw_characters( |
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[2afd852a] | 143 | Console_Port_Data[minor].termios_data, &temp8, 1); |
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[3a5fec8] | 144 | |
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| 145 | SH_SCI_REG_MASK(SCI_RDRF, minor, SCI_SSR); |
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| 146 | break; |
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| 147 | } |
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| 148 | } |
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| 149 | } |
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| 150 | |
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[3906b3ea] | 151 | /* |
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[3a5fec8] | 152 | * Transmit-data-empty ISR |
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| 153 | * |
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| 154 | * The same routine for all interrupt sources of the same type. |
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| 155 | */ |
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| 156 | rtems_isr sh_sci_tx_isr(rtems_vector_number vector) |
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| 157 | { |
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| 158 | int minor; |
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| 159 | |
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[2afd852a] | 160 | for (minor = 0; minor < Console_Port_Count; minor++) { |
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[7431fdc] | 161 | if (Console_Port_Tbl[minor]->ulDataPort == vector) { |
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[3906b3ea] | 162 | /* |
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[3a5fec8] | 163 | * FIXME: Error handling should be added |
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| 164 | */ |
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[3906b3ea] | 165 | |
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| 166 | /* |
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[3a5fec8] | 167 | * Mask end-of-transmission interrupt |
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| 168 | */ |
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| 169 | SH_SCI_REG_MASK(SCI_TIE, minor, SCI_SCR); |
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| 170 | |
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[2afd852a] | 171 | if (rtems_termios_dequeue_characters( |
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| 172 | Console_Port_Data[minor].termios_data, 1)) { |
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[3906b3ea] | 173 | /* |
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[3a5fec8] | 174 | * More characters to be received - interrupt must be enabled |
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| 175 | */ |
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| 176 | SH_SCI_REG_FLAG(SCI_TIE, minor, SCI_SCR); |
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| 177 | } |
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| 178 | break; |
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| 179 | } |
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| 180 | } |
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| 181 | } |
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| 182 | |
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| 183 | |
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[3906b3ea] | 184 | /* |
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[3a5fec8] | 185 | * Initialization of serial port |
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| 186 | */ |
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| 187 | void sh_sci_init(int minor) |
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| 188 | { |
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[e96a950b] | 189 | uint16_t temp16; |
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[3906b3ea] | 190 | |
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| 191 | /* |
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| 192 | * set PFC registers to enable I/O pins |
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[3a5fec8] | 193 | */ |
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[2afd852a] | 194 | if ((minor == 0)) { |
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[3a5fec8] | 195 | temp16 = read16(PFC_PACRL2); /* disable SCK0, DMA, IRQ */ |
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| 196 | temp16 &= ~(PA2MD1 | PA2MD0); |
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| 197 | temp16 |= (PA_TXD0 | PA_RXD0); /* enable pins for Tx0, Rx0 */ |
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| 198 | write16(temp16, PFC_PACRL2); |
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[3906b3ea] | 199 | |
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[2afd852a] | 200 | } else if (minor == 1) { |
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[3a5fec8] | 201 | temp16 = read16(PFC_PACRL2); /* disable SCK1, DMA, IRQ */ |
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| 202 | temp16 &= ~(PA5MD1 | PA5MD0); |
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| 203 | temp16 |= (PA_TXD1 | PA_RXD1); /* enable pins for Tx1, Rx1 */ |
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| 204 | write16(temp16, PFC_PACRL2); |
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[3906b3ea] | 205 | } |
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[3a5fec8] | 206 | |
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[3906b3ea] | 207 | /* |
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[3a5fec8] | 208 | * Non-default hardware setup occurs in sh_sci_first_open |
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| 209 | */ |
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| 210 | } |
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| 211 | |
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[3906b3ea] | 212 | /* |
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[3a5fec8] | 213 | * Initialization of interrupts |
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| 214 | * |
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| 215 | * Interrupts can be started only after opening a device, so interrupt |
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| 216 | * flags are set up in sh_sci_first_open function |
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| 217 | */ |
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| 218 | void sh_sci_initialize_interrupts(int minor) |
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| 219 | { |
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| 220 | rtems_isr_entry old_isr; |
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| 221 | rtems_status_code status; |
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| 222 | |
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| 223 | sh_sci_init(minor); |
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[3906b3ea] | 224 | /* |
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[3a5fec8] | 225 | * Disable IRQ of SCIx |
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| 226 | */ |
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[7431fdc] | 227 | status = sh_set_irq_priority( Console_Port_Tbl[minor]->ulIntVector, 0); |
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[3a5fec8] | 228 | |
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[2afd852a] | 229 | if (status != RTEMS_SUCCESSFUL) |
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[3a5fec8] | 230 | rtems_fatal_error_occurred(status); |
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| 231 | |
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| 232 | SH_SCI_REG_MASK(SCI_RIE, minor, SCI_SCR); |
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| 233 | |
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[3906b3ea] | 234 | /* |
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[3a5fec8] | 235 | * Catch apropriate vectors |
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| 236 | */ |
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| 237 | status = rtems_interrupt_catch( |
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[3906b3ea] | 238 | sh_sci_rx_isr, |
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[7431fdc] | 239 | Console_Port_Tbl[minor]->ulIntVector, |
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[3a5fec8] | 240 | &old_isr); |
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| 241 | |
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[2afd852a] | 242 | if (status != RTEMS_SUCCESSFUL) |
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[3a5fec8] | 243 | rtems_fatal_error_occurred(status); |
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| 244 | |
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| 245 | status = rtems_interrupt_catch( |
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| 246 | sh_sci_tx_isr, |
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[7431fdc] | 247 | Console_Port_Tbl[minor]->ulDataPort, |
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[3a5fec8] | 248 | &old_isr); |
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| 249 | |
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[2afd852a] | 250 | if (status != RTEMS_SUCCESSFUL) |
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[3a5fec8] | 251 | rtems_fatal_error_occurred(status); |
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[3906b3ea] | 252 | |
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| 253 | /* |
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| 254 | * Enable IRQ of SCIx |
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[3a5fec8] | 255 | */ |
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| 256 | SH_SCI_REG_FLAG(SCI_RIE, minor, SCI_SCR); |
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| 257 | |
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| 258 | status = sh_set_irq_priority( |
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[7431fdc] | 259 | Console_Port_Tbl[minor]->ulIntVector, |
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| 260 | Console_Port_Tbl[minor]->ulCtrlPort2); |
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[3a5fec8] | 261 | |
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[2afd852a] | 262 | if (status != RTEMS_SUCCESSFUL) |
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[3a5fec8] | 263 | rtems_fatal_error_occurred(status); |
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| 264 | } |
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| 265 | |
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| 266 | |
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| 267 | /* |
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| 268 | * Open entry point |
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| 269 | * Sets up port and pins for selected sci. |
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| 270 | */ |
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| 271 | |
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| 272 | int sh_sci_first_open( |
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| 273 | int major, |
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| 274 | int minor, |
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[2afd852a] | 275 | void *arg |
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| 276 | ) |
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[3a5fec8] | 277 | { |
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[2afd852a] | 278 | char temp8; |
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[3a5fec8] | 279 | unsigned int a ; |
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[3906b3ea] | 280 | |
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| 281 | /* |
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| 282 | * check for valid minor number |
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[3a5fec8] | 283 | */ |
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[2afd852a] | 284 | if (( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 )) { |
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[3a5fec8] | 285 | return RTEMS_INVALID_NUMBER; |
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| 286 | } |
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| 287 | |
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[3906b3ea] | 288 | /* |
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| 289 | * set up SCI registers |
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[3a5fec8] | 290 | */ |
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| 291 | /* Clear SCR - disable Tx and Rx */ |
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| 292 | SH_SCI_REG_DATA(0x00, minor, SCI_SCR); |
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[3906b3ea] | 293 | |
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[3a5fec8] | 294 | /* set SMR and BRR - baudrate and format */ |
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[7431fdc] | 295 | sh_sci_set_attributes(minor, Console_Port_Tbl[minor]->pDeviceParams); |
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[3a5fec8] | 296 | |
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[2afd852a] | 297 | for (a=0; a < 10000L; a++) { /* Delay */ |
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[3d0af835] | 298 | __asm__ volatile ("nop"); |
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[3a5fec8] | 299 | } |
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| 300 | |
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| 301 | write8((SCI_RE | SCI_TE), /* enable async. Tx and Rx */ |
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[7431fdc] | 302 | Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SCR); |
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[3a5fec8] | 303 | |
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[3906b3ea] | 304 | /* |
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| 305 | * clear error flags |
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[3a5fec8] | 306 | */ |
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[7431fdc] | 307 | temp8 = read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SSR); |
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[2afd852a] | 308 | while(temp8 & (SCI_RDRF | SCI_ORER | SCI_FER | SCI_PER)) { |
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[3a5fec8] | 309 | /* flush input */ |
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[7431fdc] | 310 | temp8 = read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_RDR); |
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[3a5fec8] | 311 | |
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| 312 | /* clear some flags */ |
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[7431fdc] | 313 | SH_SCI_REG_FLAG((SCI_RDRF|SCI_ORER|SCI_FER|SCI_PER), minor, SCI_SSR); |
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[3906b3ea] | 314 | |
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[3a5fec8] | 315 | /* check if everything is OK */ |
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[7431fdc] | 316 | temp8 = read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SSR); |
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[3906b3ea] | 317 | } |
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| 318 | |
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[3a5fec8] | 319 | /* Clear RDRF flag */ |
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| 320 | SH_SCI_REG_DATA(0x00, minor, SCI_TDR); /* force output */ |
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[3906b3ea] | 321 | |
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[3a5fec8] | 322 | /* Clear the TDRE bit */ |
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| 323 | SH_SCI_REG_FLAG(SCI_TDRE, minor, SCI_SSR); |
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[3906b3ea] | 324 | |
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| 325 | /* |
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| 326 | * Interrupt setup |
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[3a5fec8] | 327 | */ |
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[7431fdc] | 328 | if (Console_Port_Tbl[minor]->pDeviceFns->deviceOutputUsesInterrupts) { |
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[3a5fec8] | 329 | SH_SCI_REG_FLAG(SCI_RIE, minor, SCI_SCR); |
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| 330 | } |
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[3906b3ea] | 331 | |
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[3a5fec8] | 332 | return RTEMS_SUCCESSFUL ; |
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| 333 | } |
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| 334 | |
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| 335 | /* |
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| 336 | * Close entry point |
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| 337 | */ |
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| 338 | |
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| 339 | int sh_sci_last_close( |
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| 340 | int major, |
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| 341 | int minor, |
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| 342 | void *arg |
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| 343 | ) |
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| 344 | { |
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| 345 | /* FIXME: Incomplete */ |
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| 346 | |
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| 347 | /* Shutdown interrupts if necessary */ |
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[7431fdc] | 348 | if (Console_Port_Tbl[minor]->pDeviceFns->deviceOutputUsesInterrupts) |
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[3a5fec8] | 349 | { |
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| 350 | SH_SCI_REG_MASK((SCI_TIE | SCI_RIE), minor, SCI_SCR); |
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| 351 | } |
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| 352 | return RTEMS_SUCCESSFUL ; |
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| 353 | } |
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| 354 | |
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[3906b3ea] | 355 | /* |
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[3a5fec8] | 356 | * Interrupt aware write routine |
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| 357 | */ |
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[a5fb3d1b] | 358 | ssize_t sh_sci_write_support_int( |
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[2afd852a] | 359 | int minor, |
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| 360 | const char *buf, |
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[a5fb3d1b] | 361 | size_t len |
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[3a5fec8] | 362 | ) |
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| 363 | { |
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[2afd852a] | 364 | if (!len) |
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[3a5fec8] | 365 | return 0; |
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| 366 | /* |
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| 367 | * Put data into TDR and clear transmission-end-flag |
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| 368 | */ |
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| 369 | SH_SCI_REG_DATA(*buf, minor, SCI_TDR); |
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| 370 | SH_SCI_REG_MASK(SCI_TDRE, minor, SCI_SSR); |
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[3906b3ea] | 371 | /* |
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[3a5fec8] | 372 | * Enable interrupt |
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| 373 | */ |
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| 374 | SH_SCI_REG_FLAG(SCI_TIE, minor, SCI_SCR); |
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[3906b3ea] | 375 | |
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[3a5fec8] | 376 | return 1; |
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| 377 | } |
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| 378 | |
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[3906b3ea] | 379 | /* |
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[3a5fec8] | 380 | * Polled write method |
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| 381 | */ |
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[a5fb3d1b] | 382 | ssize_t sh_sci_write_support_polled( |
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[2afd852a] | 383 | int minor, |
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| 384 | const char *buf, |
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[a5fb3d1b] | 385 | size_t len |
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[3a5fec8] | 386 | ) |
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| 387 | { |
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| 388 | int count = 0; |
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[3906b3ea] | 389 | |
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[2afd852a] | 390 | while(count < len) { |
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[3a5fec8] | 391 | sh_sci_write_polled(minor, buf[count]); |
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| 392 | count++; |
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| 393 | } |
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[3906b3ea] | 394 | /* |
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[3a5fec8] | 395 | * Return number of bytes written |
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| 396 | */ |
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| 397 | return count; |
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| 398 | } |
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| 399 | |
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[3906b3ea] | 400 | /* |
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[3a5fec8] | 401 | * Polled write of one character at a time |
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| 402 | */ |
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| 403 | void sh_sci_write_polled( |
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[2afd852a] | 404 | int minor, |
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| 405 | char c |
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[3a5fec8] | 406 | ) |
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| 407 | { |
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[3906b3ea] | 408 | /* |
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[3a5fec8] | 409 | * Wait for end of previous character |
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| 410 | */ |
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[7431fdc] | 411 | while(!(read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SSR) & SCI_TDRE)); |
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[3906b3ea] | 412 | /* |
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[3a5fec8] | 413 | * Send the character |
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| 414 | */ |
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| 415 | SH_SCI_REG_DATA(c, minor, SCI_TDR); |
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[3906b3ea] | 416 | |
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| 417 | /* |
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[3a5fec8] | 418 | * Clear TDRE flag |
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| 419 | */ |
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| 420 | SH_SCI_REG_MASK(SCI_TDRE, minor, SCI_SSR); |
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| 421 | } |
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| 422 | |
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[3906b3ea] | 423 | /* |
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| 424 | * Non-blocking read |
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[3a5fec8] | 425 | */ |
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| 426 | int sh_sci_inbyte_nonblocking_polled(int minor) |
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| 427 | { |
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[2afd852a] | 428 | char inbyte; |
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[3a5fec8] | 429 | |
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[3906b3ea] | 430 | /* |
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[3a5fec8] | 431 | * Check if input buffer is full |
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| 432 | */ |
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[7431fdc] | 433 | if (read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SSR) & SCI_RDRF) { |
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| 434 | inbyte = read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_RDR); |
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[3a5fec8] | 435 | SH_SCI_REG_MASK(SCI_RDRF, minor, SCI_SSR); |
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[3906b3ea] | 436 | |
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| 437 | /* |
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[3a5fec8] | 438 | * Check for errors |
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| 439 | */ |
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[7431fdc] | 440 | if (read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SSR) & |
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[2afd852a] | 441 | (SCI_ORER | SCI_FER | SCI_PER)) { |
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[3a5fec8] | 442 | SH_SCI_REG_MASK((SCI_ORER | SCI_FER | SCI_PER), minor, SCI_SSR); |
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| 443 | return -1; |
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[3906b3ea] | 444 | } |
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[3a5fec8] | 445 | return (int)inbyte; |
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| 446 | } |
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| 447 | return -1; |
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| 448 | } |
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