[4a238002] | 1 | /* |
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| 2 | * Bit values for the serial control registers of the Hitachi SH704X |
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| 3 | * |
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| 4 | * From Hitachi tutorials |
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| 5 | * |
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| 6 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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| 7 | * Bernd Becker (becker@faw.uni-ulm.de) |
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| 8 | * |
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| 9 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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| 10 | * |
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| 11 | * This program is distributed in the hope that it will be useful, |
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| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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| 14 | * |
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| 15 | * |
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| 16 | * COPYRIGHT (c) 1998. |
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| 17 | * On-Line Applications Research Corporation (OAR). |
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| 18 | * Copyright assigned to U.S. Government, 1994. |
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| 19 | * |
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| 20 | * The license and distribution terms for this file may be |
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| 21 | * found in the file LICENSE in this distribution or at |
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| 22 | * http://www.OARcorp.com/rtems/license.html. |
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| 23 | * |
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| 24 | * $Id$ |
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| 25 | */ |
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| 26 | |
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| 27 | #ifndef _sh7_sci_h |
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| 28 | #define _sh7_sci_h |
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| 29 | |
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| 30 | #include <rtems/score/iosh7045.h> |
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| 31 | |
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| 32 | /* |
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| 33 | * Serial mode register bits |
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| 34 | */ |
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| 35 | |
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| 36 | #define SCI_SYNC_MODE 0x80 |
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| 37 | #define SCI_SEVEN_BIT_DATA 0x40 |
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| 38 | #define SCI_PARITY_ON 0x20 |
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| 39 | #define SCI_ODD_PARITY 0x10 |
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| 40 | #define SCI_STOP_BITS_2 0x08 |
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| 41 | #define SCI_ENABLE_MULTIP 0x04 |
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| 42 | #define SCI_PHI_64 0x03 |
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| 43 | #define SCI_PHI_16 0x02 |
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| 44 | #define SCI_PHI_4 0x01 |
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| 45 | #define SCI_PHI_0 0x00 |
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| 46 | |
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| 47 | /* |
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| 48 | * Serial register offsets, relative to SCI0_SMR or SCI1_SMR |
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| 49 | */ |
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| 50 | |
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| 51 | #define SCI_SMR 0x00 |
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| 52 | #define SCI_BRR 0x01 |
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| 53 | #define SCI_SCR 0x02 |
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| 54 | #define SCI_TDR 0x03 |
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| 55 | #define SCI_SSR 0x04 |
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| 56 | #define SCI_RDR 0x05 |
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| 57 | |
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| 58 | /* |
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| 59 | * Serial control register bits |
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| 60 | */ |
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| 61 | #define SCI_TIE 0x80 /* Transmit interrupt enable */ |
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| 62 | #define SCI_RIE 0x40 /* Receive interrupt enable */ |
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| 63 | #define SCI_TE 0x20 /* Transmit enable */ |
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| 64 | #define SCI_RE 0x10 /* Receive enable */ |
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| 65 | #define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */ |
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| 66 | #define SCI_TEIE 0x04 /* Transmit end interrupt enable */ |
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| 67 | #define SCI_CKE1 0x02 /* Clock enable 1 */ |
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| 68 | #define SCI_CKE0 0x01 /* Clock enable 0 */ |
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| 69 | |
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| 70 | /* |
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| 71 | * Serial status register bits |
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| 72 | */ |
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| 73 | #define SCI_TDRE 0x80 /* Transmit data register empty */ |
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| 74 | #define SCI_RDRF 0x40 /* Receive data register full */ |
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| 75 | #define SCI_ORER 0x20 /* Overrun error */ |
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| 76 | #define SCI_FER 0x10 /* Framing error */ |
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| 77 | #define SCI_PER 0x08 /* Parity error */ |
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| 78 | #define SCI_TEND 0x04 /* Transmit end */ |
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| 79 | #define SCI_MPB 0x02 /* Multiprocessor bit */ |
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| 80 | #define SCI_MPBT 0x01 /* Multiprocessor bit transfer */ |
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| 81 | |
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| 82 | /* |
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| 83 | * INTC Priority Settings |
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| 84 | */ |
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| 85 | |
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| 86 | #define SCI0_IPMSK 0x00F0 |
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| 87 | #define SCI0_LOWIP 0x0010 |
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| 88 | #define SCI1_IPMSK 0x000F |
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| 89 | #define SCI1_LOWIP 0x0001 |
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| 90 | |
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| 91 | #endif /* _sh7_sci_h */ |
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