source: rtems/c/src/lib/libcpu/sh/sh7045/include/sh7_pfc.h @ c8f3e82

Last change on this file since c8f3e82 was fc0ac39c, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 12, 2001 at 9:00:52 PM

2001-10-12 Joel Sherrill <joel@…>

  • clock/ckinit.c, include/iosh7045.h, include/ispsh7045.h, include/sci.h, include/sh7_pfc.h, include/sh7_sci.h, sci/sci.c, score/cpu_asm.c, score/ispsh7045.c, timer/timer.c: Fixed typo.
  • Property mode set to 100644
File size: 4.8 KB
Line 
1/*
2 * Bit values for the pin function controller of the Hitachi SH704x
3 *
4 * From Hitachi tutorials
5 *
6 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
7 *           Bernd Becker (becker@faw.uni-ulm.de)
8 *
9 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
10 *
11 *  This program is distributed in the hope that it will be useful,
12 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
13 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14 *
15 *
16 *  COPYRIGHT (c) 1998.
17 *  On-Line Applications Research Corporation (OAR).
18 *
19 *  The license and distribution terms for this file may be
20 *  found in the file LICENSE in this distribution or at
21 *  http://www.OARcorp.com/rtems/license.html.
22 *
23 *  $Id$
24 */
25
26#ifndef _sh7_pfc_h
27#define _sh7_pfc_h
28
29#include <rtems/score/iosh7045.h>
30
31/*
32 * Port A IO Registers (PAIORH, PAIORL)
33 *    1 => OUTPUT
34 *    0 => INPUT
35 */
36#define PAIORH     PFC_PAIORH
37#define PAIORL     PFC_PAIORL
38
39/* PAIORH */
40#define PA23IOR    0x0080
41#define PA22IOR    0x0040
42#define PA21IOR    0x0020
43#define PA20IOR    0x0010
44#define PA19IOR    0x0008
45#define PA18IOR    0x0004
46#define PA17IOR    0x0002
47#define PA16IOR    0x0001
48
49/* PAIORL */
50#define PA15IOR    0x8000
51#define PA14IOR    0x4000
52#define PA13IOR    0x2000
53#define PA12IOR    0x1000
54#define PA11IOR    0x0800
55#define PA10IOR    0x0400
56#define PA9IOR     0x0200
57#define PA8IOR     0x0100
58#define PA7IOR     0x0080
59#define PA6IOR     0x0040
60#define PA5IOR     0x0020
61#define PA4IOR     0x0010
62#define PA3IOR     0x0008
63#define PA2IOR     0x0004
64#define PA1IOR     0x0002
65#define PA0IOR     0x0001
66
67/*
68 * Port A Control Registers (PACRH, PACRL1, PACRL2)
69 * and mode bits
70 */
71#define PACRH      PFC_PACRH
72#define PACRL1     PFC_PACRL1
73#define PACRL2     PFC_PACRL2
74
75/* PACRH */
76#define PA23MD0    0x4000
77#define PA22MD0    0x1000
78#define PA21MD0    0x0400
79#define PA20MD0    0x0100
80#define PA19MD1    0x0080
81#define PA19MD0    0x0040
82#define PA18MD1    0x0020
83#define PA18MD0    0x0010
84#define PA17MD0    0x0004
85#define PA16MD0    0x0001
86
87/* PACRL1 */
88#define PA15MD0    0x4000
89#define PA14MD0    0x1000
90#define PA13MD0    0x0400
91#define PA12MD0    0x0100
92#define PA11MD0    0x0040
93#define PA10MD0    0x0010
94#define PA9MD1     0x0008
95#define PA9MD0     0x0004
96#define PA8MD1     0x0002
97#define PA8MD0     0x0001
98
99/* PACRL2 */
100#define PA7MD1     0x8000
101#define PA7MD0     0x4000
102#define PA6MD1     0x2000
103#define PA6MD0     0x1000
104#define PA5MD1     0x0800
105#define PA5MD0     0x0400
106#define PA4MD0     0x0100
107#define PA3MD0     0x0040
108#define PA2MD1     0x0020
109#define PA2MD0     0x0010
110#define PA1MD0     0x0004
111#define PA0MD0     0x0001
112
113#define PA_TXD1    PA4MD0
114#define PA_RXD1    PA3MD0
115#define PA_TXD0    PA1MD0
116#define PA_RXD0    PA0MD0
117
118/*
119 * Port B IO Register (PBIOR)
120 */
121#define PBIOR      PFC_PBIOR
122#define PB15IOR    0x8000
123#define PB14IOR    0x4000
124#define PB13IOR    0x2000
125#define PB12IOR    0x1000
126#define PB11IOR    0x0800
127#define PB10IOR    0x0400
128#define PB9IOR     0x0200
129#define PB8IOR     0x0100
130#define PB7IOR     0x0080
131#define PB6IOR     0x0040
132#define PB5IOR     0x0020
133#define PB4IOR     0x0010
134#define PB3IOR     0x0008
135#define PB2IOR     0x0004
136#define PB1IOR     0x0002
137#define PB0IOR     0x0001
138
139/*
140 * Port B Control Register (PBCR1)
141 */
142#define PBCR1      PFC_PBCR1
143#define PB15MD1    0x8000
144#define PB15MD0    0x4000
145#define PB14MD1    0x2000
146#define PB14MD0    0x1000
147#define PB13MD1    0x0800
148#define PB13MD0    0x0400
149#define PB12MD1    0x0200
150#define PB12MD0    0x0100
151#define PB11MD1    0x0080
152#define PB11MD0    0x0040
153#define PB10MD1    0x0020
154#define PB10MD0    0x0010
155#define PB9MD1     0x0008
156#define PB9MD0     0x0004
157#define PB8MD1     0x0002
158#define PB8MD0     0x0001
159
160#define PB15MD     PB15MD1|PB14MD0
161#define PB14MD     PB14MD1|PB14MD0
162#define PB13MD     PB13MD1|PB13MD0
163#define PB12MD     PB12MD1|PB12MD0
164#define PB11MD     PB11MD1|PB11MD0
165#define PB10MD     PB10MD1|PB10MD0
166#define PB9MD      PB9MD1|PB9MD0
167#define PB8MD      PB8MD1|PB8MD0
168
169#define PB_TXD1    PB11MD1
170#define PB_RXD1    PB10MD1
171#define PB_TXD0    PB9MD1
172#define PB_RXD0    PB8MD1
173
174/*
175 * Port B Control Register (PBCR2)
176 */
177#define PBCR2      PFC_PBCR2
178#define PB7MD1     0x8000
179#define PB7MD0     0x4000
180#define PB6MD1     0x2000
181#define PB6MD0     0x1000
182#define PB5MD1     0x0800
183#define PB5MD0     0x0400
184#define PB4MD1     0x0200
185#define PB4MD0     0x0100
186#define PB3MD1     0x0080
187#define PB3MD0     0x0040
188#define PB2MD1     0x0020
189#define PB2MD0     0x0010
190#define PB1MD1     0x0008
191#define PB1MD0     0x0004
192#define PB0MD1     0x0002
193#define PB0MD0     0x0001
194       
195#define PB7MD      PB7MD1|PB7MD0
196#define PB6MD      PB6MD1|PB6MD0
197#define PB5MD      PB5MD1|PB5MD0
198#define PB4MD      PB4MD1|PB4MD0
199#define PB3MD      PB3MD1|PB3MD0
200#define PB2MD      PB2MD1|PB2MD0
201#define PB1MD      PB1MD1|PB1MD0
202#define PB0MD      PB0MD1|PB0MD0
203
204#endif /* _sh7_pfc_h */
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