source: rtems/c/src/lib/libcpu/sh/sh7045/include/sh7_pfc.h @ 8b91282

4.104.114.84.95
Last change on this file since 8b91282 was 8b91282, checked in by Joel Sherrill <joel.sherrill@…>, on Dec 21, 1999 at 2:27:52 PM

Patch rtems-rc-19991203-5.diff from Ralf Corsepius <corsepiu@…>
which cleans up and merges some Hitachi SH-2 modifications from
John Mills <jmills@…>.

  • Property mode set to 100644
File size: 4.8 KB
Line 
1/*
2 * Bit values for the pin function controller of the Hitachi SH704x
3 *
4 * From Hitachi tutorials
5 *
6 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
7 *           Bernd Becker (becker@faw.uni-ulm.de)
8 *
9 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
10 *
11 *  This program is distributed in the hope that it will be useful,
12 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
13 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14 *
15 *
16 *  COPYRIGHT (c) 1998.
17 *  On-Line Applications Research Corporation (OAR).
18 *  Copyright assigned to U.S. Government, 1994.
19 *
20 *  The license and distribution terms for this file may be
21 *  found in the file LICENSE in this distribution or at
22 *  http://www.OARcorp.com/rtems/license.html.
23 *
24 *  $Id$
25 */
26
27#ifndef _sh7_pfc_h
28#define _sh7_pfc_h
29
30#include <rtems/score/iosh7045.h>
31
32/*
33 * Port A IO Registers (PAIORH, PAIORL)
34 *    1 => OUTPUT
35 *    0 => INPUT
36 */
37#define PAIORH     PFC_PAIORH
38#define PAIORL     PFC_PAIORL
39
40/* PAIORH */
41#define PA23IOR    0x0080
42#define PA22IOR    0x0040
43#define PA21IOR    0x0020
44#define PA20IOR    0x0010
45#define PA19IOR    0x0008
46#define PA18IOR    0x0004
47#define PA17IOR    0x0002
48#define PA16IOR    0x0001
49
50/* PAIORL */
51#define PA15IOR    0x8000
52#define PA14IOR    0x4000
53#define PA13IOR    0x2000
54#define PA12IOR    0x1000
55#define PA11IOR    0x0800
56#define PA10IOR    0x0400
57#define PA9IOR     0x0200
58#define PA8IOR     0x0100
59#define PA7IOR     0x0080
60#define PA6IOR     0x0040
61#define PA5IOR     0x0020
62#define PA4IOR     0x0010
63#define PA3IOR     0x0008
64#define PA2IOR     0x0004
65#define PA1IOR     0x0002
66#define PA0IOR     0x0001
67
68/*
69 * Port A Control Registers (PACRH, PACRL1, PACRL2)
70 * and mode bits
71 */
72#define PACRH      PFC_PACRH
73#define PACRL1     PFC_PACRL1
74#define PACRL2     PFC_PACRL2
75
76/* PACRH */
77#define PA23MD0    0x4000
78#define PA22MD0    0x1000
79#define PA21MD0    0x0400
80#define PA20MD0    0x0100
81#define PA19MD1    0x0080
82#define PA19MD0    0x0040
83#define PA18MD1    0x0020
84#define PA18MD0    0x0010
85#define PA17MD0    0x0004
86#define PA16MD0    0x0001
87
88/* PACRL1 */
89#define PA15MD0    0x4000
90#define PA14MD0    0x1000
91#define PA13MD0    0x0400
92#define PA12MD0    0x0100
93#define PA11MD0    0x0040
94#define PA10MD0    0x0010
95#define PA9MD1     0x0008
96#define PA9MD0     0x0004
97#define PA8MD1     0x0002
98#define PA8MD0     0x0001
99
100/* PACRL2 */
101#define PA7MD1     0x8000
102#define PA7MD0     0x4000
103#define PA6MD1     0x2000
104#define PA6MD0     0x1000
105#define PA5MD1     0x0800
106#define PA5MD0     0x0400
107#define PA4MD0     0x0100
108#define PA3MD0     0x0040
109#define PA2MD1     0x0020
110#define PA2MD0     0x0010
111#define PA1MD0     0x0004
112#define PA0MD0     0x0001
113
114#define PA_TXD1    PA4MD0
115#define PA_RXD1    PA3MD0
116#define PA_TXD0    PA1MD0
117#define PA_RXD0    PA0MD0
118
119/*
120 * Port B IO Register (PBIOR)
121 */
122#define PBIOR      PFC_PBIOR
123#define PB15IOR    0x8000
124#define PB14IOR    0x4000
125#define PB13IOR    0x2000
126#define PB12IOR    0x1000
127#define PB11IOR    0x0800
128#define PB10IOR    0x0400
129#define PB9IOR     0x0200
130#define PB8IOR     0x0100
131#define PB7IOR     0x0080
132#define PB6IOR     0x0040
133#define PB5IOR     0x0020
134#define PB4IOR     0x0010
135#define PB3IOR     0x0008
136#define PB2IOR     0x0004
137#define PB1IOR     0x0002
138#define PB0IOR     0x0001
139
140/*
141 * Port B Control Register (PBCR1)
142 */
143#define PBCR1      PFC_PBCR1
144#define PB15MD1    0x8000
145#define PB15MD0    0x4000
146#define PB14MD1    0x2000
147#define PB14MD0    0x1000
148#define PB13MD1    0x0800
149#define PB13MD0    0x0400
150#define PB12MD1    0x0200
151#define PB12MD0    0x0100
152#define PB11MD1    0x0080
153#define PB11MD0    0x0040
154#define PB10MD1    0x0020
155#define PB10MD0    0x0010
156#define PB9MD1     0x0008
157#define PB9MD0     0x0004
158#define PB8MD1     0x0002
159#define PB8MD0     0x0001
160
161#define PB15MD     PB15MD1|PB14MD0
162#define PB14MD     PB14MD1|PB14MD0
163#define PB13MD     PB13MD1|PB13MD0
164#define PB12MD     PB12MD1|PB12MD0
165#define PB11MD     PB11MD1|PB11MD0
166#define PB10MD     PB10MD1|PB10MD0
167#define PB9MD      PB9MD1|PB9MD0
168#define PB8MD      PB8MD1|PB8MD0
169
170#define PB_TXD1    PB11MD1
171#define PB_RXD1    PB10MD1
172#define PB_TXD0    PB9MD1
173#define PB_RXD0    PB8MD1
174
175/*
176 * Port B Control Register (PBCR2)
177 */
178#define PBCR2      PFC_PBCR2
179#define PB7MD1     0x8000
180#define PB7MD0     0x4000
181#define PB6MD1     0x2000
182#define PB6MD0     0x1000
183#define PB5MD1     0x0800
184#define PB5MD0     0x0400
185#define PB4MD1     0x0200
186#define PB4MD0     0x0100
187#define PB3MD1     0x0080
188#define PB3MD0     0x0040
189#define PB2MD1     0x0020
190#define PB2MD0     0x0010
191#define PB1MD1     0x0008
192#define PB1MD0     0x0004
193#define PB0MD1     0x0002
194#define PB0MD0     0x0001
195       
196#define PB7MD      PB7MD1|PB7MD0
197#define PB6MD      PB6MD1|PB6MD0
198#define PB5MD      PB5MD1|PB5MD0
199#define PB4MD      PB4MD1|PB4MD0
200#define PB3MD      PB3MD1|PB3MD0
201#define PB2MD      PB2MD1|PB2MD0
202#define PB1MD      PB1MD1|PB1MD0
203#define PB0MD      PB0MD1|PB0MD0
204
205#endif /* _sh7_pfc_h */
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