source: rtems/c/src/lib/libcpu/sh/sh7045/include/ispsh7045.h @ c8f3e82

Last change on this file since c8f3e82 was d911f16c, checked in by Joel Sherrill <joel.sherrill@…>, on Apr 3, 2002 at 2:09:20 PM

2001-04-03 Joel Sherrill <joel@…>

  • Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
  • include/ispsh7045.h, score/ispsh7045.c: Account for name change.
  • Property mode set to 100644
File size: 4.9 KB
Line 
1/*
2 *  This include file contains information pertaining to the Hitachi SH
3 *  processor.
4 *
5 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
6 *           Bernd Becker (becker@faw.uni-ulm.de)
7 *
8 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
9 *
10 *  This program is distributed in the hope that it will be useful,
11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 *
15 *  COPYRIGHT (c) 1998.
16 *  On-Line Applications Research Corporation (OAR).
17 *
18 *  The license and distribution terms for this file may be
19 *  found in the file LICENSE in this distribution or at
20 *  http://www.OARcorp.com/rtems/license.html.
21 *
22 *  Modified to reflect isp entries for sh7045 processor:
23 *  John M. Mills (jmills@tga.com)
24 *  TGA Technologies, Inc.
25 *  100 Pinnacle Way, Suite 140
26 *  Norcross, GA 30071 U.S.A.
27 * 
28 *
29 *  This modified file may be copied and distributed in accordance
30 *  the above-referenced license. It is provided for critique and
31 *  developmental purposes without any warranty nor representation
32 *  by the authors or by TGA Technologies.
33 *
34 *  $Id$
35 */
36
37#ifndef __CPU_ISPS_H
38#define __CPU_ISPS_H
39
40#ifdef __cplusplus
41extern "C" {
42#endif
43
44#include <rtems/score/types.h>
45
46extern void __ISR_Handler( unsigned32 vector );
47
48
49/*
50 * interrupt vector table offsets
51 */
52#define NMI_ISP_V 11
53#define USB_ISP_V 12
54#define IRQ0_ISP_V 64
55#define IRQ1_ISP_V 65
56#define IRQ2_ISP_V 66
57#define IRQ3_ISP_V 67
58#define IRQ4_ISP_V 68
59#define IRQ5_ISP_V 69
60#define IRQ6_ISP_V 70
61#define IRQ7_ISP_V 71
62#define DMA0_ISP_V 72
63#define DMA1_ISP_V 76
64#define DMA2_ISP_V 80
65#define DMA3_ISP_V 84
66
67#define MTUA0_ISP_V 88
68#define MTUB0_ISP_V 89
69#define MTUC0_ISP_V 90
70#define MTUD0_ISP_V 91
71#define MTUV0_ISP_V 92
72
73#define MTUA1_ISP_V 96
74#define MTUB1_ISP_V 97
75#define MTUV1_ISP_V 100
76#define MTUU1_ISP_V 101
77
78#define MTUA2_ISP_V 104
79#define MTUB2_ISP_V 105
80#define MTUV2_ISP_V 108
81#define MTUU2_ISP_V 109
82
83#define MTUA3_ISP_V 112
84#define MTUB3_ISP_V 113
85#define MTUC3_ISP_V 114
86#define MTUD3_ISP_V 115
87#define MTUV3_ISP_V 116
88
89#define MTUA4_ISP_V 120
90#define MTUB4_ISP_V 121
91#define MTUC4_ISP_V 122
92#define MTUD4_ISP_V 123
93#define MTUV4_ISP_V 124
94
95#define ERI0_ISP_V 128
96#define RXI0_ISP_V 129
97#define TXI0_ISP_V 130
98#define TEI0_ISP_V 131
99
100#define ERI1_ISP_V 132
101#define RXI1_ISP_V 133
102#define TXI1_ISP_V 134
103#define TEI1_ISP_V 135
104
105#define ADI0_ISP_V 136
106#define ADI1_ISP_V 137
107#define DTC_ISP_V 140  /* Data Transfer Controller */
108#define CMT0_ISP_V 144 /* Compare Match Timer */
109#define CMT1_ISP_V 148
110#define WDT_ISP_V 152  /* Wtachdog Timer */
111#define CMI_ISP_V 153  /* BSC RAS interrupt */
112#define OEI_ISP_V 156  /* I/O Port */
113#define DREF_ISP_V CMI_ISP_V /* DRAM Refresh from BSC */
114#if 0
115#define PRT_ISP_V /* parity error - no equivalent */
116#endif
117
118/* dummy ISP */
119extern void _dummy_isp( void );
120
121/* Non Maskable Interrupt */
122extern void _nmi_isp( void );
123
124/* User Break Controller */
125extern void _usb_isp( void );
126
127/* External interrupts 0-7 */
128extern void _irq0_isp( void );
129extern void _irq1_isp( void );
130extern void _irq2_isp( void );
131extern void _irq3_isp( void );
132extern void _irq4_isp( void );
133extern void _irq5_isp( void );
134extern void _irq6_isp( void );
135extern void _irq7_isp( void );
136
137/* DMA - Controller */
138extern void _dma0_isp( void );
139extern void _dma1_isp( void );
140extern void _dma2_isp( void );
141extern void _dma3_isp( void );
142
143/* Interrupt Timer Unit */
144/* Timer 0 */
145extern void _mtua0_isp( void );
146extern void _mtub0_isp( void );
147extern void _mtuc0_isp( void );
148extern void _mtud0_isp( void );
149extern void _mtuv0_isp( void );
150/* Timer 1 */
151extern void _mtua1_isp( void );
152extern void _mtub1_isp( void );
153extern void _mtuv1_isp( void );
154extern void _mtuu1_isp( void );
155/* Timer 2 */
156extern void _mtua2_isp( void );
157extern void _mtub2_isp( void );
158extern void _mtuv2_isp( void );
159extern void _mtuu2_isp( void );
160/* Timer 3 */
161extern void _mtua3_isp( void );
162extern void _mtub3_isp( void );
163extern void _mtuc3_isp( void );
164extern void _mtud3_isp( void );
165extern void _mtuv3_isp( void );
166/* Timer 4 */
167extern void _mtua4_isp( void );
168extern void _mtub4_isp( void );
169extern void _mtuc4_isp( void );
170extern void _mtud4_isp( void );
171extern void _mtuv4_isp( void );
172
173/* serial interfaces */
174extern void _eri0_isp( void );
175extern void _rxi0_isp( void );
176extern void _txi0_isp( void );
177extern void _tei0_isp( void );
178extern void _eri1_isp( void );
179extern void _rxi1_isp( void );
180extern void _txi1_isp( void );
181extern void _tei1_isp( void );
182
183/* ADC */
184extern void _adi0_isp( void );
185extern void _adi1_isp( void );
186
187/* Data Transfer Controller */
188extern void _dtci_isp( void );
189
190/* Compare Match Timer */
191extern void _cmt0_isp( void );
192extern void _cmt1_isp( void );
193
194/* Watchdog Timer */
195extern void _wdt_isp( void );
196
197/* DRAM refresh control unit of bus state controller */
198extern void _bsc_isp( void );
199
200/* I/O Port */
201extern void _oei_isp( void );
202
203/* Parity Control Unit of the Bus State Controllers */
204/* extern void _prt_isp( void ); */
205
206#ifdef __cplusplus
207}
208#endif
209
210#endif
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