source: rtems/c/src/lib/libcpu/sh/sh7045/include/ispsh7045.h @ b22a19e

4.104.114.84.95
Last change on this file since b22a19e was b22a19e, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 22, 1999 at 1:46:50 PM

Adding files not added as part of merger of SH2 port.

  • Property mode set to 100644
File size: 5.0 KB
Line 
1/*
2 *  This include file contains information pertaining to the Hitachi SH
3 *  processor.
4 *
5 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
6 *           Bernd Becker (becker@faw.uni-ulm.de)
7 *
8 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
9 *
10 *  This program is distributed in the hope that it will be useful,
11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 *
15 *  COPYRIGHT (c) 1998.
16 *  On-Line Applications Research Corporation (OAR).
17 *  Copyright assigned to U.S. Government, 1994.
18 *
19 *  The license and distribution terms for this file may be
20 *  found in the file LICENSE in this distribution or at
21 *  http://www.OARcorp.com/rtems/license.html.
22 *
23 *  Modified to reflect isp entries for sh7045 processor:
24 *  John M. Mills (jmills@tga.com)
25 *  TGA Technologies, Inc.
26 *  100 Pinnacle Way, Suite 140
27 *  Norcross, GA 30071 U.S.A.
28 * 
29 *
30 *  This modified file may be copied and distributed in accordance
31 *  the above-referenced license. It is provided for critique and
32 *  developmental purposes without any warranty nor representation
33 *  by the authors or by TGA Technologies.
34 *
35 *  $Id$
36 */
37
38#ifndef __CPU_ISPS_H
39#define __CPU_ISPS_H
40
41#ifdef __cplusplus
42extern "C" {
43#endif
44
45#include <rtems/score/shtypes.h>
46
47extern void __ISR_Handler( unsigned32 vector );
48
49
50/*
51 * interrupt vector table offsets
52 */
53#define NMI_ISP_V 11
54#define USB_ISP_V 12
55#define IRQ0_ISP_V 64
56#define IRQ1_ISP_V 65
57#define IRQ2_ISP_V 66
58#define IRQ3_ISP_V 67
59#define IRQ4_ISP_V 68
60#define IRQ5_ISP_V 69
61#define IRQ6_ISP_V 70
62#define IRQ7_ISP_V 71
63#define DMA0_ISP_V 72
64#define DMA1_ISP_V 76
65#define DMA2_ISP_V 80
66#define DMA3_ISP_V 84
67
68#define MTUA0_ISP_V 88
69#define MTUB0_ISP_V 89
70#define MTUC0_ISP_V 90
71#define MTUD0_ISP_V 91
72#define MTUV0_ISP_V 92
73
74#define MTUA1_ISP_V 96
75#define MTUB1_ISP_V 97
76#define MTUV1_ISP_V 100
77#define MTUU1_ISP_V 101
78
79#define MTUA2_ISP_V 104
80#define MTUB2_ISP_V 105
81#define MTUV2_ISP_V 108
82#define MTUU2_ISP_V 109
83
84#define MTUA3_ISP_V 112
85#define MTUB3_ISP_V 113
86#define MTUC3_ISP_V 114
87#define MTUD3_ISP_V 115
88#define MTUV3_ISP_V 116
89
90#define MTUA4_ISP_V 120
91#define MTUB4_ISP_V 121
92#define MTUC4_ISP_V 122
93#define MTUD4_ISP_V 123
94#define MTUV4_ISP_V 124
95
96#define ERI0_ISP_V 128
97#define RXI0_ISP_V 129
98#define TXI0_ISP_V 130
99#define TEI0_ISP_V 131
100
101#define ERI1_ISP_V 132
102#define RXI1_ISP_V 133
103#define TXI1_ISP_V 134
104#define TEI1_ISP_V 135
105
106#define ADI0_ISP_V 136
107#define ADI1_ISP_V 137
108#define DTC_ISP_V 140  /* Data Transfer Controller */
109#define CMT0_ISP_V 144 /* Compare Match Timer */
110#define CMT1_ISP_V 148
111#define WDT_ISP_V 152  /* Wtachdog Timer */
112#define CMI_ISP_V 153  /* BSC RAS interrupt */
113#define OEI_ISP_V 156  /* I/O Port */
114#define DREF_ISP_V CMI_ISP_V /* DRAM Refresh from BSC */
115#if 0
116#define PRT_ISP_V /* parity error - no equivalent */
117#endif
118
119/* dummy ISP */
120extern void _dummy_isp( void );
121
122/* Non Maskable Interrupt */
123extern void _nmi_isp( void );
124
125/* User Break Controller */
126extern void _usb_isp( void );
127
128/* External interrupts 0-7 */
129extern void _irq0_isp( void );
130extern void _irq1_isp( void );
131extern void _irq2_isp( void );
132extern void _irq3_isp( void );
133extern void _irq4_isp( void );
134extern void _irq5_isp( void );
135extern void _irq6_isp( void );
136extern void _irq7_isp( void );
137
138/* DMA - Controller */
139extern void _dma0_isp( void );
140extern void _dma1_isp( void );
141extern void _dma2_isp( void );
142extern void _dma3_isp( void );
143
144/* Interrupt Timer Unit */
145/* Timer 0 */
146extern void _mtua0_isp( void );
147extern void _mtub0_isp( void );
148extern void _mtuc0_isp( void );
149extern void _mtud0_isp( void );
150extern void _mtuv0_isp( void );
151/* Timer 1 */
152extern void _mtua1_isp( void );
153extern void _mtub1_isp( void );
154extern void _mtuv1_isp( void );
155extern void _mtuu1_isp( void );
156/* Timer 2 */
157extern void _mtua2_isp( void );
158extern void _mtub2_isp( void );
159extern void _mtuv2_isp( void );
160extern void _mtuu2_isp( void );
161/* Timer 3 */
162extern void _mtua3_isp( void );
163extern void _mtub3_isp( void );
164extern void _mtuc3_isp( void );
165extern void _mtud3_isp( void );
166extern void _mtuv3_isp( void );
167/* Timer 4 */
168extern void _mtua4_isp( void );
169extern void _mtub4_isp( void );
170extern void _mtuc4_isp( void );
171extern void _mtud4_isp( void );
172extern void _mtuv4_isp( void );
173
174/* serial interfaces */
175extern void _eri0_isp( void );
176extern void _rxi0_isp( void );
177extern void _txi0_isp( void );
178extern void _tei0_isp( void );
179extern void _eri1_isp( void );
180extern void _rxi1_isp( void );
181extern void _txi1_isp( void );
182extern void _tei1_isp( void );
183
184/* ADC */
185extern void _adi0_isp( void );
186extern void _adi1_isp( void );
187
188/* Data Transfer Controller */
189extern void _dtci_isp( void );
190
191/* Compare Match Timer */
192extern void _cmt0_isp( void );
193extern void _cmt1_isp( void );
194
195/* Watchdog Timer */
196extern void _wdt_isp( void );
197
198/* DRAM refresh control unit of bus state controller */
199extern void _bsc_isp( void );
200
201/* I/O Port */
202extern void _oei_isp( void );
203
204/* Parity Control Unit of the Bus State Controllers */
205/* extern void _prt_isp( void ); */
206
207#ifdef __cplusplus
208}
209#endif
210
211#endif
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