1 | /* |
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2 | * This include file contains information pertaining to the Hitachi SH |
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3 | * processor. |
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4 | * |
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5 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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6 | * Bernd Becker (becker@faw.uni-ulm.de) |
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7 | * |
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8 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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9 | * |
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10 | * This program is distributed in the hope that it will be useful, |
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11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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13 | * |
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14 | * |
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15 | * COPYRIGHT (c) 1998. |
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16 | * On-Line Applications Research Corporation (OAR). |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.com/license/LICENSE. |
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21 | * |
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22 | * Modified to reflect isp entries for sh7045 processor: |
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23 | * John M. Mills (jmills@tga.com) |
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24 | * TGA Technologies, Inc. |
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25 | * 100 Pinnacle Way, Suite 140 |
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26 | * Norcross, GA 30071 U.S.A. |
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27 | * |
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28 | * |
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29 | * This modified file may be copied and distributed in accordance |
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30 | * the above-referenced license. It is provided for critique and |
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31 | * developmental purposes without any warranty nor representation |
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32 | * by the authors or by TGA Technologies. |
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33 | * |
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34 | * $Id$ |
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35 | */ |
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36 | |
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37 | #ifndef __CPU_ISPS_H |
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38 | #define __CPU_ISPS_H |
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39 | |
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40 | #ifdef __cplusplus |
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41 | extern "C" { |
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42 | #endif |
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43 | |
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44 | #include <rtems/score/types.h> |
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45 | |
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46 | extern void __ISR_Handler( uint32_t vector ); |
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47 | |
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48 | |
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49 | /* |
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50 | * interrupt vector table offsets |
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51 | */ |
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52 | #define NMI_ISP_V 11 |
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53 | #define USB_ISP_V 12 |
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54 | #define IRQ0_ISP_V 64 |
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55 | #define IRQ1_ISP_V 65 |
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56 | #define IRQ2_ISP_V 66 |
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57 | #define IRQ3_ISP_V 67 |
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58 | #define IRQ4_ISP_V 68 |
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59 | #define IRQ5_ISP_V 69 |
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60 | #define IRQ6_ISP_V 70 |
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61 | #define IRQ7_ISP_V 71 |
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62 | #define DMA0_ISP_V 72 |
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63 | #define DMA1_ISP_V 76 |
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64 | #define DMA2_ISP_V 80 |
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65 | #define DMA3_ISP_V 84 |
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66 | |
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67 | #define MTUA0_ISP_V 88 |
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68 | #define MTUB0_ISP_V 89 |
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69 | #define MTUC0_ISP_V 90 |
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70 | #define MTUD0_ISP_V 91 |
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71 | #define MTUV0_ISP_V 92 |
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72 | |
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73 | #define MTUA1_ISP_V 96 |
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74 | #define MTUB1_ISP_V 97 |
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75 | #define MTUV1_ISP_V 100 |
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76 | #define MTUU1_ISP_V 101 |
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77 | |
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78 | #define MTUA2_ISP_V 104 |
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79 | #define MTUB2_ISP_V 105 |
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80 | #define MTUV2_ISP_V 108 |
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81 | #define MTUU2_ISP_V 109 |
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82 | |
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83 | #define MTUA3_ISP_V 112 |
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84 | #define MTUB3_ISP_V 113 |
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85 | #define MTUC3_ISP_V 114 |
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86 | #define MTUD3_ISP_V 115 |
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87 | #define MTUV3_ISP_V 116 |
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88 | |
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89 | #define MTUA4_ISP_V 120 |
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90 | #define MTUB4_ISP_V 121 |
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91 | #define MTUC4_ISP_V 122 |
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92 | #define MTUD4_ISP_V 123 |
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93 | #define MTUV4_ISP_V 124 |
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94 | |
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95 | #define ERI0_ISP_V 128 |
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96 | #define RXI0_ISP_V 129 |
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97 | #define TXI0_ISP_V 130 |
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98 | #define TEI0_ISP_V 131 |
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99 | |
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100 | #define ERI1_ISP_V 132 |
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101 | #define RXI1_ISP_V 133 |
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102 | #define TXI1_ISP_V 134 |
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103 | #define TEI1_ISP_V 135 |
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104 | |
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105 | #define ADI0_ISP_V 136 |
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106 | #define ADI1_ISP_V 137 |
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107 | #define DTC_ISP_V 140 /* Data Transfer Controller */ |
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108 | #define CMT0_ISP_V 144 /* Compare Match Timer */ |
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109 | #define CMT1_ISP_V 148 |
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110 | #define WDT_ISP_V 152 /* Wtachdog Timer */ |
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111 | #define CMI_ISP_V 153 /* BSC RAS interrupt */ |
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112 | #define OEI_ISP_V 156 /* I/O Port */ |
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113 | #define DREF_ISP_V CMI_ISP_V /* DRAM Refresh from BSC */ |
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114 | #if 0 |
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115 | #define PRT_ISP_V /* parity error - no equivalent */ |
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116 | #endif |
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117 | |
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118 | /* dummy ISP */ |
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119 | extern void _dummy_isp( void ); |
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120 | |
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121 | /* Non Maskable Interrupt */ |
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122 | extern void _nmi_isp( void ); |
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123 | |
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124 | /* User Break Controller */ |
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125 | extern void _usb_isp( void ); |
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126 | |
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127 | /* External interrupts 0-7 */ |
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128 | extern void _irq0_isp( void ); |
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129 | extern void _irq1_isp( void ); |
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130 | extern void _irq2_isp( void ); |
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131 | extern void _irq3_isp( void ); |
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132 | extern void _irq4_isp( void ); |
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133 | extern void _irq5_isp( void ); |
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134 | extern void _irq6_isp( void ); |
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135 | extern void _irq7_isp( void ); |
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136 | |
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137 | /* DMA - Controller */ |
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138 | extern void _dma0_isp( void ); |
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139 | extern void _dma1_isp( void ); |
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140 | extern void _dma2_isp( void ); |
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141 | extern void _dma3_isp( void ); |
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142 | |
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143 | /* Interrupt Timer Unit */ |
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144 | /* Timer 0 */ |
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145 | extern void _mtua0_isp( void ); |
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146 | extern void _mtub0_isp( void ); |
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147 | extern void _mtuc0_isp( void ); |
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148 | extern void _mtud0_isp( void ); |
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149 | extern void _mtuv0_isp( void ); |
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150 | /* Timer 1 */ |
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151 | extern void _mtua1_isp( void ); |
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152 | extern void _mtub1_isp( void ); |
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153 | extern void _mtuv1_isp( void ); |
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154 | extern void _mtuu1_isp( void ); |
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155 | /* Timer 2 */ |
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156 | extern void _mtua2_isp( void ); |
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157 | extern void _mtub2_isp( void ); |
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158 | extern void _mtuv2_isp( void ); |
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159 | extern void _mtuu2_isp( void ); |
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160 | /* Timer 3 */ |
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161 | extern void _mtua3_isp( void ); |
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162 | extern void _mtub3_isp( void ); |
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163 | extern void _mtuc3_isp( void ); |
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164 | extern void _mtud3_isp( void ); |
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165 | extern void _mtuv3_isp( void ); |
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166 | /* Timer 4 */ |
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167 | extern void _mtua4_isp( void ); |
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168 | extern void _mtub4_isp( void ); |
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169 | extern void _mtuc4_isp( void ); |
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170 | extern void _mtud4_isp( void ); |
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171 | extern void _mtuv4_isp( void ); |
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172 | |
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173 | /* serial interfaces */ |
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174 | extern void _eri0_isp( void ); |
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175 | extern void _rxi0_isp( void ); |
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176 | extern void _txi0_isp( void ); |
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177 | extern void _tei0_isp( void ); |
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178 | extern void _eri1_isp( void ); |
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179 | extern void _rxi1_isp( void ); |
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180 | extern void _txi1_isp( void ); |
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181 | extern void _tei1_isp( void ); |
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182 | |
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183 | /* ADC */ |
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184 | extern void _adi0_isp( void ); |
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185 | extern void _adi1_isp( void ); |
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186 | |
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187 | /* Data Transfer Controller */ |
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188 | extern void _dtci_isp( void ); |
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189 | |
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190 | /* Compare Match Timer */ |
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191 | extern void _cmt0_isp( void ); |
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192 | extern void _cmt1_isp( void ); |
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193 | |
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194 | /* Watchdog Timer */ |
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195 | extern void _wdt_isp( void ); |
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196 | |
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197 | /* DRAM refresh control unit of bus state controller */ |
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198 | extern void _bsc_isp( void ); |
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199 | |
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200 | /* I/O Port */ |
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201 | extern void _oei_isp( void ); |
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202 | |
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203 | /* Parity Control Unit of the Bus State Controllers */ |
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204 | /* extern void _prt_isp( void ); */ |
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205 | |
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206 | #ifdef __cplusplus |
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207 | } |
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208 | #endif |
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209 | |
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210 | #endif |
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