[b22a19e] | 1 | /* |
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| 2 | * This include file contains information pertaining to the Hitachi SH |
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| 3 | * processor. |
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| 4 | * |
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| 5 | * NOTE: NOT ALL VALUES HAVE BEEN CHECKED !! |
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| 6 | * |
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| 7 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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| 8 | * Bernd Becker (becker@faw.uni-ulm.de) |
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| 9 | * |
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| 10 | * Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which |
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| 11 | * contained no copyright notice. |
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| 12 | * |
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| 13 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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| 14 | * |
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| 15 | * This program is distributed in the hope that it will be useful, |
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| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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| 18 | * |
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| 19 | * |
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| 20 | * COPYRIGHT (c) 1998. |
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| 21 | * On-Line Applications Research Corporation (OAR). |
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| 22 | * |
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| 23 | * The license and distribution terms for this file may be |
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| 24 | * found in the file LICENSE in this distribution or at |
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| 25 | * http://www.OARcorp.com/rtems/license.html. |
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| 26 | * |
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| 27 | * Modified to reflect on-chip registers for sh7045 processor, based on |
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| 28 | * "Register.h" distributed with Hitachi's EVB7045F tutorials, and which |
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| 29 | * contained no copyright notice: |
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| 30 | * John M. Mills (jmills@tga.com) |
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| 31 | * TGA Technologies, Inc. |
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| 32 | * 100 Pinnacle Way, Suite 140 |
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| 33 | * Norcross, GA 30071 U.S.A. |
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| 34 | * August, 1999 |
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| 35 | * |
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| 36 | * This modified file may be copied and distributed in accordance |
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| 37 | * the above-referenced license. It is provided for critique and |
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| 38 | * developmental purposes without any warranty nor representation |
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| 39 | * by the authors or by TGA Technologies. |
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| 40 | * |
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| 41 | * $Id$ |
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| 42 | */ |
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| 43 | |
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| 44 | #ifndef __IOSH7045_H |
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| 45 | #define __IOSH7045_H |
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| 46 | |
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| 47 | /* |
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| 48 | * After each line is explained whether the access is char short or long. |
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| 49 | * The functions read/writeb, w, l, 8, 16, 32 can be found |
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| 50 | * in exec/score/cpu/sh/sh_io.h |
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| 51 | * |
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| 52 | * 8 bit == char ( readb, writeb, read8, write8) |
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| 53 | * 16 bit == short ( readw, writew, read16, write16 ) |
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| 54 | * 32 bit == long ( readl, writel, read32, write32 ) |
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| 55 | * JMM: Addresses noted "[char, ]short,word" are per Hitachi _SuperH_RISC_ |
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| 56 | * ENGINE_..Hardware_Manual; alignment access-restrictions may apply |
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| 57 | */ |
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| 58 | |
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| 59 | #define REG_BASE 0xFFFF8000 |
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| 60 | |
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| 61 | /* SCI0 Registers */ |
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| 62 | #define SCI_SMR0 (REG_BASE + 0x01a0) /*char: Serial mode ch 0 */ |
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| 63 | #define SCI_BRR0 (REG_BASE + 0x01a1) /*char: Bit rate ch 0 */ |
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| 64 | #define SCI_SCR0 (REG_BASE + 0x01a2) /*char: Serial control ch 0 */ |
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| 65 | #define SCI_TDR0 (REG_BASE + 0x01a3) /*char: Transmit data ch 0 */ |
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| 66 | #define SCI_SSR0 (REG_BASE + 0x01a4) /*char: Serial status ch 0 */ |
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| 67 | #define SCI_RDR0 (REG_BASE + 0x01a5) /*char: Receive data ch 0 */ |
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| 68 | |
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| 69 | /* SCI1 Registers */ |
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| 70 | #define SCI_SMR1 (REG_BASE + 0x01b0) /* char: Serial mode ch 1 */ |
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| 71 | #define SCI_BRR1 (REG_BASE + 0x01b1) /* char: Bit rate ch 1 */ |
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| 72 | #define SCI_SCR1 (REG_BASE + 0x01b2) /* char: Serial control ch 1 */ |
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| 73 | #define SCI_TDR1 (REG_BASE + 0x01b3) /* char: Transmit data ch 1 */ |
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| 74 | #define SCI_SSR1 (REG_BASE + 0x01b4) /* char: Serial status ch 1 */ |
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| 75 | #define SCI_RDR1 (REG_BASE + 0x01b5) /* char: Receive data ch 1 */ |
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| 76 | |
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| 77 | /* ADI */ |
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| 78 | /* High Speed A/D (Excluding A-Mask Part)*/ |
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| 79 | #define ADDRA (REG_BASE + 0x03F0) /* short */ |
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| 80 | #define ADDRB (REG_BASE + 0x03F2) /* short */ |
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| 81 | #define ADDRC (REG_BASE + 0x03F4) /* short */ |
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| 82 | #define ADDRD (REG_BASE + 0x03F6) /* short */ |
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| 83 | #define ADDRE (REG_BASE + 0x03F8) /* short */ |
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| 84 | #define ADDRF (REG_BASE + 0x03FA) /* short */ |
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| 85 | #define ADDRG (REG_BASE + 0x03FC) /* short */ |
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| 86 | #define ADDRH (REG_BASE + 0x03FE) /* short */ |
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| 87 | #define ADCSR (REG_BASE + 0x03E0) /* char */ |
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| 88 | #define ADCR (REG_BASE + 0x03E1) /* char */ |
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| 89 | |
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| 90 | /* Mid-Speed A/D (A-Mask part)*/ |
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| 91 | #define ADDRA0 (REG_BASE + 0x0400) /* char, short */ |
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| 92 | #define ADDRA0H (REG_BASE + 0x0400) /* char, short */ |
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| 93 | #define ADDRA0L (REG_BASE + 0x0401) /* char */ |
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| 94 | #define ADDRB0 (REG_BASE + 0x0402) /* char, short */ |
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| 95 | #define ADDRB0H (REG_BASE + 0x0402) /* char, short */ |
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| 96 | #define ADDRB0L (REG_BASE + 0x0403) /* char */ |
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| 97 | #define ADDRC0 (REG_BASE + 0x0404) /* char, short */ |
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| 98 | #define ADDRC0H (REG_BASE + 0x0404) /* char, short */ |
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| 99 | #define ADDRC0L (REG_BASE + 0x0405) /* char */ |
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| 100 | #define ADDRD0 (REG_BASE + 0x0406) /* char, short */ |
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| 101 | #define ADDRD0H (REG_BASE + 0x0406) /* char, short */ |
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| 102 | #define ADDRD0L (REG_BASE + 0x0407) /* char */ |
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| 103 | #define ADCSR0 (REG_BASE + 0x0410) /* char */ |
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| 104 | #define ADCR0 (REG_BASE + 0x0412) /* char */ |
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| 105 | #define ADDRA1 (REG_BASE + 0x0408) /* char, short */ |
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| 106 | #define ADDRA1H (REG_BASE + 0x0408) /* char, short */ |
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| 107 | #define ADDRA1L (REG_BASE + 0x0409) /* char */ |
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| 108 | #define ADDRB1 (REG_BASE + 0x040A) /* char, short */ |
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| 109 | #define ADDRB1H (REG_BASE + 0x040A) /* char, short */ |
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| 110 | #define ADDRB1L (REG_BASE + 0x040B) /* char */ |
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| 111 | #define ADDRC1 (REG_BASE + 0x040C) /* char, short */ |
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| 112 | #define ADDRC1H (REG_BASE + 0x040C) /* char, short */ |
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| 113 | #define ADDRC1L (REG_BASE + 0x040D) /* char */ |
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| 114 | #define ADDRD1 (REG_BASE + 0x040E) /* char, short */ |
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| 115 | #define ADDRD1H (REG_BASE + 0x040E) /* char, short */ |
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| 116 | #define ADDRD1L (REG_BASE + 0x040F) /* char */ |
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| 117 | #define ADCSR1 (REG_BASE + 0x0411) /* char */ |
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| 118 | #define ADCR1 (REG_BASE + 0x0413) /* char */ |
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| 119 | |
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| 120 | /*MTU SHARED*/ |
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| 121 | #define MTU_TSTR (REG_BASE + 0x0240) /* char, short, word */ |
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| 122 | #define MTU_TSYR (REG_BASE + 0x0241) /* char, short, word */ |
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| 123 | #define MTU_ICSR (REG_BASE + 0x03C0) /* input lev. CSR */ |
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| 124 | #define MTU_OCSR (REG_BASE + 0x03C0) /* output lev. CSR */ |
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| 125 | |
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| 126 | /*MTU CHANNEL 0*/ |
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| 127 | #define MTU_TCR0 (REG_BASE + 0x0260) /* char, short, word */ |
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| 128 | #define MTU_TMDR0 (REG_BASE + 0x0261) /* char, short, word */ |
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| 129 | #define MTU_TIORH0 (REG_BASE + 0x0262) /* char, short, word */ |
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| 130 | #define MTU_TIORL0 (REG_BASE + 0x0263) /* char, short, word */ |
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| 131 | #define MTU_TIER0 (REG_BASE + 0x0264) /* char, short, word */ |
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| 132 | #define MTU_TSR0 (REG_BASE + 0x0265) /* char, short, word */ |
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| 133 | #define MTU_TCNT0 (REG_BASE + 0x0266) /* short, word */ |
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| 134 | #define MTU_GR0A (REG_BASE + 0x0268) /* short, word */ |
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| 135 | #define MTU_GR0B (REG_BASE + 0x026A) /* short, word */ |
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| 136 | #define MTU_GR0C (REG_BASE + 0x026C) /* short, word */ |
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| 137 | #define MTU_GR0D (REG_BASE + 0x026E) /* short, word */ |
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| 138 | |
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| 139 | /*MTU CHANNEL 1*/ |
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| 140 | #define MTU_TCR1 (REG_BASE + 0x0280) /* char, short, word */ |
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| 141 | #define MTU_TMDR1 (REG_BASE + 0x0281) /* char, short, word */ |
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| 142 | #define MTU_TIOR1 (REG_BASE + 0x0282) /* char, short, word */ |
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| 143 | #define MTU_TIER1 (REG_BASE + 0x0284) /* char, short, word */ |
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| 144 | #define MTU_TSR1 (REG_BASE + 0x0285) /* char, short, word */ |
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| 145 | #define MTU_TCNT1 (REG_BASE + 0x0286) /* short, word */ |
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| 146 | #define MTU_GR1A (REG_BASE + 0x0288) /* short, word */ |
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| 147 | #define MTU_GR1B (REG_BASE + 0x028A) /* short, word */ |
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| 148 | |
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| 149 | /*MTU CHANNEL 2*/ |
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| 150 | #define MTU_TCR2 (REG_BASE + 0x02A0) /* char, short, word */ |
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| 151 | #define MTU_TMDR2 (REG_BASE + 0x02A1) /* char, short, word */ |
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| 152 | #define MTU_TIOR2 (REG_BASE + 0x02A2) /* char, short, word */ |
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| 153 | #define MTU_TIER2 (REG_BASE + 0x02A4) /* char, short, word */ |
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| 154 | #define MTU_TSR2 (REG_BASE + 0x02A5) /* char, short, word */ |
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| 155 | #define MTU_TCNT2 (REG_BASE + 0x02A6) /* short, word */ |
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| 156 | #define MTU_GR2A (REG_BASE + 0x02A8) /* short, word */ |
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| 157 | #define MTU_GR2B (REG_BASE + 0x02AA) /* short, word */ |
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| 158 | |
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| 159 | /*MTU CHANNELS 3-4 SHARED*/ |
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| 160 | #define MTU_TOER (REG_BASE + 0x020A) /* char, short, word */ |
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| 161 | #define MTU_TOCR (REG_BASE + 0x020B) /* char, short, word */ |
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| 162 | #define MTU_TGCR (REG_BASE + 0x020D) /* char, short, word */ |
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| 163 | #define MTU_TCDR (REG_BASE + 0x0214) /* short, word */ |
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| 164 | #define MTU_TDDR (REG_BASE + 0x0216) /* short, word */ |
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| 165 | #define MTU_TCNTS (REG_BASE + 0x0220) /* short, word */ |
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| 166 | #define MTU_TCBR (REG_BASE + 0x0222) /* short, word */ |
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| 167 | |
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| 168 | /*MTU CHANNEL 3*/ |
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| 169 | #define MTU_TCR3 (REG_BASE + 0x0200) /* char, short, word */ |
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| 170 | #define MTU_TMDR3 (REG_BASE + 0x0202) /* char, short, word */ |
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| 171 | #define MTU_TIORH3 (REG_BASE + 0x0204) /* char, short, word */ |
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| 172 | #define MTU_TIORL3 (REG_BASE + 0x0205) /* char, short, word */ |
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| 173 | #define MTU_TIER3 (REG_BASE + 0x0208) /* char, short, word */ |
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| 174 | #define MTU_TSR3 (REG_BASE + 0x022C) /* char, short, word */ |
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| 175 | #define MTU_TCNT3 (REG_BASE + 0x0210) /* short, word */ |
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| 176 | #define MTU_GR3A (REG_BASE + 0x0218) /* short, word */ |
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| 177 | #define MTU_GR3B (REG_BASE + 0x021A) /* short, word */ |
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| 178 | #define MTU_GR3C (REG_BASE + 0x0224) /* short, word */ |
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| 179 | #define MTU_GR3D (REG_BASE + 0x0226) /* short, word */ |
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| 180 | |
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| 181 | /*MTU CHANNEL 4*/ |
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| 182 | #define MTU_TCR4 (REG_BASE + 0x0201) /* char, short, word */ |
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| 183 | #define MTU_TMDR4 (REG_BASE + 0x0203) /* char, short, word */ |
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| 184 | #define MTU_TIOR4 (REG_BASE + 0x0206) /* char, short, word */ |
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| 185 | #define MTU_TIORH4 (REG_BASE + 0x0206) /* char, short, word */ |
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| 186 | #define MTU_TIORL4 (REG_BASE + 0x0207) /* char, short, word */ |
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| 187 | #define MTU_TIER4 (REG_BASE + 0x0209) /* char, short, word */ |
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| 188 | #define MTU_TSR4 (REG_BASE + 0x022D) /* char, short, word */ |
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| 189 | #define MTU_TCNT4 (REG_BASE + 0x0212) /* short, word */ |
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| 190 | #define MTU_GR4A (REG_BASE + 0x021C) /* short, word */ |
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| 191 | #define MTU_GR4B (REG_BASE + 0x021E) /* short, word */ |
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| 192 | #define MTU_GR4C (REG_BASE + 0x0228) /* short, word */ |
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| 193 | #define MTU_GR4D (REG_BASE + 0x022A) /* short, word */ |
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| 194 | |
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| 195 | /*DMAC CHANNELS 0-3 SHARED*/ |
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| 196 | #define DMAOR (REG_BASE + 0x06B0) /* short */ |
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| 197 | |
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| 198 | /*DMAC CHANNEL 0*/ |
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| 199 | #define DMA_SAR0 (REG_BASE + 0x06C0) /* short, word */ |
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| 200 | #define DMA_DAR0 (REG_BASE + 0x06C4) /* short, word */ |
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| 201 | #define DMA_DMATCR0 (REG_BASE + 0x06C8) /* short, word */ |
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| 202 | #define DMA_CHCR0 (REG_BASE + 0x06CC) /* short, word */ |
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| 203 | |
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| 204 | /*DMAC CHANNEL 1*/ |
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| 205 | #define DMA_SAR1 (REG_BASE + 0x06D0) /* short, word */ |
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| 206 | #define DMA_DAR1 (REG_BASE + 0x06D4) /* short, word */ |
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| 207 | #define DMA_DMATCR1 (REG_BASE + 0x06D8) /* short, wordt */ |
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| 208 | #define DMA_CHCR1 (REG_BASE + 0x06DC) /* short, word */ |
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| 209 | |
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| 210 | /*DMAC CHANNEL 3*/ |
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| 211 | #define DMA_SAR3 (REG_BASE + 0x06E0) /* short, word */ |
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| 212 | #define DMA_DAR3 (REG_BASE + 0x06E4) /* short, word */ |
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| 213 | #define DMA_DMATCR3 (REG_BASE + 0x06E8) /* short, word */ |
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| 214 | #define DMA_CHCR3 (REG_BASE + 0x06EC) /* short, word */ |
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| 215 | |
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| 216 | /*DMAC CHANNEL 4*/ |
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| 217 | #define DMA_SAR4 (REG_BASE + 0x06F0) /* short, word */ |
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| 218 | #define DMA_DAR4 (REG_BASE + 0x06F4) /* short, word */ |
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| 219 | #define DMA_DMATCR4 (REG_BASE + 0x06F8) /* short, word */ |
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| 220 | #define DMA_CHCR4 (REG_BASE + 0x06FC) /* short, word */ |
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| 221 | |
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| 222 | /*Data Transfer Controller*/ |
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| 223 | #define DTC_DTEA (REG_BASE + 0x0700) /* char, short, word */ |
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| 224 | #define DTC_DTEB (REG_BASE + 0x0701) /* char, short(?), word(?) */ |
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| 225 | #define DTC_DTEC (REG_BASE + 0x0702) /* char, short(?), word(?) */ |
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| 226 | #define DTC_DTED (REG_BASE + 0x0703) /* char, short(?), word(?) */ |
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| 227 | #define DTC_DTEE (REG_BASE + 0x0704) /* char, short(?), word(?) */ |
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| 228 | #define DTC_DTCSR (REG_BASE + 0x0706) /* char, short, word */ |
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| 229 | #define DTC_DTBR (REG_BASE + 0x0708) /* short, word */ |
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| 230 | |
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| 231 | /*Cache Memory*/ |
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| 232 | #define CAC_CCR (REG_BASE + 0x0740) /* char, short, word */ |
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| 233 | |
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| 234 | /*INTC*/ |
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| 235 | #define INTC_IPRA (REG_BASE + 0x0348) /* char, short, word */ |
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| 236 | #define INTC_IPRB (REG_BASE + 0x034A) /* char, short, word */ |
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| 237 | #define INTC_IPRC (REG_BASE + 0x034C) /* char, short, word */ |
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| 238 | #define INTC_IPRD (REG_BASE + 0x034E) /* char, short, word */ |
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| 239 | #define INTC_IPRE (REG_BASE + 0x0350) /* char, short, word */ |
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| 240 | #define INTC_IPRF (REG_BASE + 0x0352) /* char, short, word */ |
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| 241 | #define INTC_IPRG (REG_BASE + 0x0354) /* char, short, word */ |
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| 242 | #define INTC_IPRH (REG_BASE + 0x0356) /* char, short, word */ |
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| 243 | #define INTC_ICR (REG_BASE + 0x0358) /* char, short, word */ |
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| 244 | #define INTC_ISR (REG_BASE + 0x035A) /* char, short, word */ |
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| 245 | |
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| 246 | /*Flash (F-ZTAT)*/ |
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| 247 | #define FL_FLMCR1 (REG_BASE + 0x0580) /* Fl.Mem.Contr.Reg 1: char */ |
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| 248 | #define FL_FLMCR2 (REG_BASE + 0x0581) /* Fl.Mem.Contr.Reg 2: char */ |
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| 249 | #define FL_EBR1 (REG_BASE + 0x0582) /* Fl.Mem.Erase Blk.1: char */ |
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| 250 | #define FL_EBR2 (REG_BASE + 0x0584) /* Fl.Mem.Erase Blk.2: char */ |
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| 251 | #define FL_RAMER (REG_BASE + 0x0628) /* Ram Emul.Reg.- char,short,word */ |
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| 252 | |
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| 253 | /*UBC*/ |
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| 254 | #define UBC_BARH (REG_BASE + 0x0600) /* char, short, word */ |
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| 255 | #define UBC_BARL (REG_BASE + 0x0602) /* char, short, word */ |
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| 256 | #define UBC_BAMRH (REG_BASE + 0x0604) /* char, short, word */ |
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| 257 | #define UBC_BAMRL (REG_BASE + 0x0606) /* char, short, word */ |
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| 258 | #define UBC_BBR (REG_BASE + 0x0608) /* char, short, word */ |
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| 259 | /*BSC*/ |
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| 260 | #define BSC_BCR1 (REG_BASE + 0x0620) /* short */ |
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| 261 | #define BSC_BCR2 (REG_BASE + 0x0622) /* short */ |
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| 262 | #define BSC_WCR1 (REG_BASE + 0x0624) /* short */ |
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| 263 | #define BSC_WCR2 (REG_BASE + 0x0626) /* short */ |
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| 264 | #define BSC_DCR (REG_BASE + 0x062A) /* short */ |
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| 265 | #define BSC_RTCSR (REG_BASE + 0x062C) /* short */ |
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| 266 | #define BSC_RTCNT (REG_BASE + 0x062E) /* short */ |
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| 267 | #define BSC_RTCOR (REG_BASE + 0x0630) /* short */ |
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| 268 | |
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| 269 | /*WDT*/ |
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| 270 | #define WDT_R_TCSR (REG_BASE + 0x0610) /* rd: char */ |
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| 271 | #define WDT_R_TCNT (REG_BASE + 0x0611) /* rd: char */ |
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| 272 | #define WDT_R_RSTCSR (REG_BASE + 0x0613) /* rd: char */ |
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| 273 | #define WDT_W_TCSR (REG_BASE + 0x0610) /* wrt: short */ |
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| 274 | #define WDT_W_TCNT (REG_BASE + 0x0610) /* wrt: short */ |
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| 275 | #define WDT_W_RSTCSR (REG_BASE + 0x0612) /* wrt: short */ |
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| 276 | |
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| 277 | /*POWER DOWN STATE*/ |
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| 278 | #define PDT_SBYCR (REG_BASE + 0x0614) /* char */ |
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| 279 | |
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| 280 | /* Port I/O Control Registers */ |
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| 281 | #define IO_PADRH (REG_BASE + 0x0380) /* Port A Data Register */ |
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| 282 | #define IO_PADRL (REG_BASE + 0x0382) /* Port A Data Register */ |
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| 283 | #define IO_PBDR (REG_BASE + 0x0390) /* Port B Data Register */ |
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| 284 | #define IO_PCDR (REG_BASE + 0x0392) /* Port C Data Register */ |
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| 285 | #define IO_PDDRH (REG_BASE + 0x03A0) /* Port D Data Register */ |
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| 286 | #define IO_PDDRL (REG_BASE + 0x03A2) /* Port D Data Register */ |
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| 287 | #define IO_PEDR (REG_BASE + 0x03B0) /* Port E Data Register */ |
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| 288 | #define IO_PFDR (REG_BASE + 0x03B2) /* Port F Data Register */ |
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| 289 | |
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| 290 | /*Pin Function Control Register*/ |
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| 291 | #define PFC_PAIORH (REG_BASE + 0x0384) /* Port A I/O Reg. H */ |
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| 292 | #define PFC_PAIORL (REG_BASE + 0x0386) /* Port A I/O Reg. L */ |
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| 293 | #define PFC_PACRH (REG_BASE + 0x0388) /* Port A Ctr. Reg. H */ |
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| 294 | #define PFC_PACRL1 (REG_BASE + 0x038C) /* Port A Ctr. Reg. L1 */ |
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| 295 | #define PFC_PACRL2 (REG_BASE + 0x038E) /* Port A Ctr. Reg. L2 */ |
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| 296 | #define PFC_PBIOR (REG_BASE + 0x0394) /* Port B I/O Register */ |
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| 297 | #define PFC_PBCR1 (REG_BASE + 0x0398) /* Port B Ctr. Reg. R1 */ |
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| 298 | #define PFC_PBCR2 (REG_BASE + 0x039A) /* Port B Ctr. Reg. R2 */ |
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| 299 | #define PFC_PCIOR (REG_BASE + 0x0396) /* Port C I/O Register */ |
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| 300 | #define PFC_PCCR (REG_BASE + 0x039C) /* Port C Ctr. Reg. */ |
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| 301 | #define PFC_PDIORH (REG_BASE + 0x03A4) /* Port D I/O Reg. H */ |
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| 302 | #define PFC_PDIORL (REG_BASE + 0x03A6) /* Port D I/O Reg. L */ |
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| 303 | #define PFC_PDCRH1 (REG_BASE + 0x03A8) /* Port D Ctr. Reg. H1 */ |
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| 304 | #define PFC_PDCRH2 (REG_BASE + 0x03AA) /* Port D Ctr. Reg. H2 */ |
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| 305 | #define PFC_PDCRL (REG_BASE + 0x03AC) /* Port D Ctr. Reg. L */ |
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| 306 | #define PFC_PEIOR (REG_BASE + 0x03B4) /* Port E I/O Register */ |
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| 307 | #define PFC_PECR1 (REG_BASE + 0x03B8) /* Port E Ctr. Reg. 1 */ |
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| 308 | #define PFC_PECR2 (REG_BASE + 0x03BA) /* Port E Ctr. Reg. 2 */ |
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[8b91282] | 309 | #define PFC_IFCR (REG_BASE + 0x03C8) /* short */ |
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[b22a19e] | 310 | |
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| 311 | /*Compare/Match Timer*/ |
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| 312 | #define CMT_CMSTR (REG_BASE + 0x3D0) /* Start Reg. char, short, word */ |
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| 313 | #define CMT_CMCSR0 (REG_BASE + 0x3D2) /* C0 SCR short, word */ |
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| 314 | #define CMT_CMCNT0 (REG_BASE + 0x3D4) /* C0 Counter char, short, word */ |
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| 315 | #define CMT_CMCOR0 (REG_BASE + 0x3D6) /* C0 Const.Reg. char, short, word */ |
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| 316 | #define CMT_CMCSR1 (REG_BASE + 0x3D8) /* C1 SCR short, word */ |
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| 317 | #define CMT_CMCNT1 (REG_BASE + 0x3DA) /* C1 Counter char, short, word */ |
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| 318 | #define CMT_CMCOR1 (REG_BASE + 0x3DC) /* C1 Const.Reg. char, short, word */ |
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| 319 | |
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| 320 | #endif |
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