source: rtems/c/src/lib/libcpu/sh/sh7045/clock/ckinit.c @ 4dd1aa5

4.104.114.84.95
Last change on this file since 4dd1aa5 was 4dd1aa5, checked in by Joel Sherrill <joel.sherrill@…>, on Jan 22, 2001 at 2:11:09 PM

2001-01-22 Radzislaw Galler <rgaller@…>

  • clock/ckinit.c (Install_clock): Modified MTU timer 0 initialization to generate an interrupt exactly every 1us
  • Property mode set to 100644
File size: 7.1 KB
Line 
1/*
2 *  This file contains the clock driver the Hitachi SH 704X
3 *
4 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
5 *           Bernd Becker (becker@faw.uni-ulm.de)
6 *
7 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
8 *
9 *  This program is distributed in the hope that it will be useful,
10 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
11 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
12 *
13 *
14 *  COPYRIGHT (c) 1998.
15 *  On-Line Applications Research Corporation (OAR).
16 *  Copyright assigned to U.S. Government, 1994.
17 *
18 *      Modified to reflect registers of sh7045 processor:
19 *      John M. Mills (jmills@tga.com)
20 *      TGA Technologies, Inc.
21 *      100 Pinnacle Way, Suite 140
22 *      Norcross, GA 30071 U.S.A.
23 *      August, 1999
24 *
25 *      This modified file may be copied and distributed in accordance
26 *      the above-referenced license. It is provided for critique and
27 *      developmental purposes without any warranty nor representation
28 *      by the authors or by TGA Technologies.
29 *
30 *  The license and distribution terms for this file may be
31 *  found in the file LICENSE in this distribution or at
32 *  http://www.OARcorp.com/rtems/license.html.
33 *
34 *  $Id$
35 */
36
37#include <rtems.h>
38
39#include <stdlib.h>
40
41#include <rtems/libio.h>
42#include <rtems/score/sh_io.h>
43#include <rtems/score/sh.h>
44#include <rtems/score/ispsh7045.h>
45#include <rtems/score/iosh7045.h>
46
47#define _MTU_COUNTER0_MICROSECOND (Clock_MHZ/16)
48
49#ifndef CLOCKPRIO
50#define CLOCKPRIO 10
51#endif
52
53#define MTU0_STARTMASK  0xfe
54#define MTU0_SYNCMASK   0xfe
55#define MTU0_MODEMASK   0xc0
56#define MTU0_TCRMASK    0x22 /* bit 7 also used, vs 703x */
57#define MTU0_STAT_MASK  0xc0
58#define MTU0_IRQMASK    0xfe
59#define MTU0_TIERMASK   0x01
60#define IPRC_MTU0_MASK  0xff0f
61#define MTU0_TIORVAL    0x08
62
63/*
64 *  The interrupt vector number associated with the clock tick device
65 *  driver.
66 */
67
68#define CLOCK_VECTOR MTUA0_ISP_V
69
70/*
71 *  Clock_driver_ticks is a monotonically increasing counter of the
72 *  number of clock ticks since the driver was initialized.
73 */
74
75volatile rtems_unsigned32 Clock_driver_ticks;
76
77static void Clock_exit( void );
78static rtems_isr Clock_isr( rtems_vector_number vector );
79static rtems_unsigned32 Clock_MHZ ;
80
81/*
82 *  Clock_isrs is the number of clock ISRs until the next invocation of
83 *  the RTEMS clock tick routine.  The clock tick device driver
84 *  gets an interrupt once a millisecond and counts down until the
85 *  length of time between the user configured microseconds per tick
86 *  has passed.
87 */
88
89rtems_unsigned32 Clock_isrs;              /* ISRs until next tick */
90static rtems_unsigned32 Clock_isrs_const;        /* only calculated once */
91
92/*
93 * These are set by clock driver during its init
94 */
95 
96rtems_device_major_number rtems_clock_major = ~0;
97rtems_device_minor_number rtems_clock_minor;
98
99/*
100 *  The previous ISR on this clock tick interrupt vector.
101 */
102
103rtems_isr_entry  Old_ticker;
104
105/*
106 *  Isr Handler
107 */
108
109rtems_isr Clock_isr(
110  rtems_vector_number vector
111)
112{
113  /*
114   * bump the number of clock driver ticks since initialization
115   *
116
117   * determine if it is time to announce the passing of tick as configured
118   * to RTEMS through the rtems_clock_tick directive
119   *
120   * perform any timer dependent tasks
121   */
122  unsigned8 temp;
123
124  /* reset the flags of the status register */
125  temp = read8( MTU_TSR0) & MTU0_STAT_MASK;
126  write8( temp, MTU_TSR0);
127
128  Clock_driver_ticks++ ;
129
130  if( Clock_isrs == 1)
131    {
132      rtems_clock_tick();
133      Clock_isrs = Clock_isrs_const;
134    }
135  else
136    {
137      Clock_isrs-- ;
138    }
139}
140
141/*
142 *  Install_clock
143 *
144 *  Install a clock tick handler and reprograms the chip.  This
145 *  is used to initially establish the clock tick.
146 */
147
148void Install_clock(
149  rtems_isr_entry clock_isr
150)
151{
152  unsigned8 temp8 = 0;
153  unsigned32 factor = 1000000;
154 
155 
156  /*
157   *  Initialize the clock tick device driver variables
158   */
159
160  Clock_driver_ticks = 0;
161  Clock_isrs_const = rtems_configuration_get_microseconds_per_tick() / 10000;
162  Clock_isrs = Clock_isrs_const;
163 
164  factor /= rtems_configuration_get_microseconds_per_tick(); /* minimalization of integer division error */
165  Clock_MHZ = rtems_cpu_configuration_get_clicks_per_second() / factor ;
166
167  rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker );
168
169  /*
170   *  Hardware specific initialize goes here
171   */
172   
173  /* stop Timer 0 */
174  temp8 = read8( MTU_TSTR) & MTU0_STARTMASK;
175  write8( temp8, MTU_TSTR);
176
177  /* set initial counter value to 0 */
178  write16( 0, MTU_TCNT0);
179
180  /* Timer 0 runs independent */
181  temp8 = read8( MTU_TSYR) & MTU0_SYNCMASK;
182  write8( temp8, MTU_TSYR);
183
184  /* Timer 0 normal mode */
185  temp8 = read8( MTU_TMDR0) & MTU0_MODEMASK;
186  write8( temp8, MTU_TMDR0);
187
188  /* TCNT is cleared by GRA ; internal clock /16 */
189  write8( MTU0_TCRMASK , MTU_TCR0);
190
191  /* use GRA without I/O - pins  */
192  write8( MTU0_TIORVAL, MTU_TIORL0); 
193   
194  /* reset flags of the status register */
195  temp8 = read8( MTU_TSR0) & MTU0_STAT_MASK;
196  write8( temp8, MTU_TSR0);
197
198  /* Irq if is equal GRA */
199  temp8 = read8( MTU_TIER0) | MTU0_TIERMASK;
200  write8( temp8, MTU_TIER0);
201
202  /* set interrupt priority */
203  if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL)
204    rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
205
206  /* set counter limits */
207  write16( _MTU_COUNTER0_MICROSECOND, MTU_GR0A);
208   
209  /* start counter */
210  temp8 = read8( MTU_TSTR) |~MTU0_STARTMASK;
211  write8( temp8, MTU_TSTR);
212
213  /*
214   *  Schedule the clock cleanup routine to execute if the application exits.
215   */
216
217  atexit( Clock_exit );
218}
219
220/*
221 *  Clean up before the application exits
222 */
223
224void Clock_exit( void )
225{
226  unsigned8 temp8 = 0;
227
228  /* turn off the timer interrupts */
229  /* set interrupt priority to 0 */
230  if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL)
231    rtems_fatal_error_occurred( RTEMS_UNSATISFIED);
232
233/*
234 *   temp16 = read16( MTU_TIER0) & IPRC_MTU0_IRQMASK;
235 *   write16( temp16, MTU_TIER0);
236 */
237
238  /* stop counter */
239  temp8 = read8( MTU_TSTR) & MTU0_STARTMASK;
240  write8( temp8, MTU_TSTR);
241
242  /* old vector shall not be installed */
243}
244
245/*
246 *  Clock_initialize
247 *
248 *  Device driver entry point for clock tick driver initialization.
249 */
250
251rtems_device_driver Clock_initialize(
252  rtems_device_major_number major,
253  rtems_device_minor_number minor,
254  void *pargp
255)
256{
257  Install_clock( Clock_isr );
258 
259  /*
260   * make major/minor avail to others such as shared memory driver
261   */
262 
263  rtems_clock_major = major;
264  rtems_clock_minor = minor;
265 
266  return RTEMS_SUCCESSFUL;
267}
268
269rtems_device_driver Clock_control(
270  rtems_device_major_number major,
271  rtems_device_minor_number minor,
272  void *pargp
273)
274{
275  rtems_unsigned32 isrlevel;
276  rtems_libio_ioctl_args_t *args = pargp;
277 
278  if (args != 0)
279    {
280      /*
281       * This is hokey, but until we get a defined interface
282       * to do this, it will just be this simple...
283       */
284     
285      if (args->command == rtems_build_name('I', 'S', 'R', ' '))
286        {
287          Clock_isr(CLOCK_VECTOR);
288        }
289      else if (args->command == rtems_build_name('N', 'E', 'W', ' '))
290        {
291          rtems_isr_entry       ignored ;
292          rtems_interrupt_disable( isrlevel );
293          rtems_interrupt_catch( args->buffer, CLOCK_VECTOR, &ignored );
294         
295          rtems_interrupt_enable( isrlevel );
296        }
297    }
298  return RTEMS_SUCCESSFUL;
299}
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