[4a238002] | 1 | /* |
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| 2 | * This file contains the clock driver the Hitachi SH 704X |
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| 3 | * |
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| 4 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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| 5 | * Bernd Becker (becker@faw.uni-ulm.de) |
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| 6 | * |
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| 7 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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| 8 | * |
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| 9 | * This program is distributed in the hope that it will be useful, |
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| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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| 12 | * |
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| 13 | * |
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| 14 | * COPYRIGHT (c) 1998. |
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| 15 | * On-Line Applications Research Corporation (OAR). |
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| 16 | * Copyright assigned to U.S. Government, 1994. |
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| 17 | * |
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| 18 | * Modified to reflect registers of sh7045 processor: |
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| 19 | * John M. Mills (jmills@tga.com) |
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| 20 | * TGA Technologies, Inc. |
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| 21 | * 100 Pinnacle Way, Suite 140 |
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| 22 | * Norcross, GA 30071 U.S.A. |
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| 23 | * August, 1999 |
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| 24 | * |
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| 25 | * This modified file may be copied and distributed in accordance |
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| 26 | * the above-referenced license. It is provided for critique and |
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| 27 | * developmental purposes without any warranty nor representation |
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| 28 | * by the authors or by TGA Technologies. |
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| 29 | * |
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| 30 | * The license and distribution terms for this file may be |
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| 31 | * found in the file LICENSE in this distribution or at |
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| 32 | * http://www.OARcorp.com/rtems/license.html. |
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| 33 | * |
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| 34 | * $Id$ |
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| 35 | */ |
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| 36 | |
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| 37 | #include <rtems.h> |
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| 38 | |
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| 39 | #include <stdlib.h> |
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| 40 | |
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| 41 | #include <rtems/libio.h> |
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| 42 | #include <rtems/score/sh_io.h> |
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| 43 | #include <rtems/score/sh.h> |
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| 44 | #include <rtems/score/ispsh7045.h> |
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| 45 | #include <rtems/score/iosh7045.h> |
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| 46 | |
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[4dd1aa5] | 47 | #define _MTU_COUNTER0_MICROSECOND (Clock_MHZ/16) |
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[4a238002] | 48 | |
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| 49 | #ifndef CLOCKPRIO |
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| 50 | #define CLOCKPRIO 10 |
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| 51 | #endif |
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| 52 | |
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| 53 | #define MTU0_STARTMASK 0xfe |
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| 54 | #define MTU0_SYNCMASK 0xfe |
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| 55 | #define MTU0_MODEMASK 0xc0 |
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[4dd1aa5] | 56 | #define MTU0_TCRMASK 0x22 /* bit 7 also used, vs 703x */ |
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[4a238002] | 57 | #define MTU0_STAT_MASK 0xc0 |
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| 58 | #define MTU0_IRQMASK 0xfe |
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| 59 | #define MTU0_TIERMASK 0x01 |
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| 60 | #define IPRC_MTU0_MASK 0xff0f |
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| 61 | #define MTU0_TIORVAL 0x08 |
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| 62 | |
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| 63 | /* |
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| 64 | * The interrupt vector number associated with the clock tick device |
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| 65 | * driver. |
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| 66 | */ |
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| 67 | |
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| 68 | #define CLOCK_VECTOR MTUA0_ISP_V |
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| 69 | |
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| 70 | /* |
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| 71 | * Clock_driver_ticks is a monotonically increasing counter of the |
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| 72 | * number of clock ticks since the driver was initialized. |
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| 73 | */ |
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| 74 | |
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| 75 | volatile rtems_unsigned32 Clock_driver_ticks; |
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| 76 | |
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| 77 | static void Clock_exit( void ); |
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| 78 | static rtems_isr Clock_isr( rtems_vector_number vector ); |
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| 79 | static rtems_unsigned32 Clock_MHZ ; |
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| 80 | |
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| 81 | /* |
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| 82 | * Clock_isrs is the number of clock ISRs until the next invocation of |
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| 83 | * the RTEMS clock tick routine. The clock tick device driver |
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| 84 | * gets an interrupt once a millisecond and counts down until the |
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| 85 | * length of time between the user configured microseconds per tick |
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| 86 | * has passed. |
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| 87 | */ |
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| 88 | |
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| 89 | rtems_unsigned32 Clock_isrs; /* ISRs until next tick */ |
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| 90 | static rtems_unsigned32 Clock_isrs_const; /* only calculated once */ |
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| 91 | |
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| 92 | /* |
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| 93 | * These are set by clock driver during its init |
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| 94 | */ |
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| 95 | |
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| 96 | rtems_device_major_number rtems_clock_major = ~0; |
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| 97 | rtems_device_minor_number rtems_clock_minor; |
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| 98 | |
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| 99 | /* |
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| 100 | * The previous ISR on this clock tick interrupt vector. |
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| 101 | */ |
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| 102 | |
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| 103 | rtems_isr_entry Old_ticker; |
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| 104 | |
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| 105 | /* |
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| 106 | * Isr Handler |
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| 107 | */ |
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| 108 | |
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| 109 | rtems_isr Clock_isr( |
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| 110 | rtems_vector_number vector |
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| 111 | ) |
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| 112 | { |
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| 113 | /* |
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| 114 | * bump the number of clock driver ticks since initialization |
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| 115 | * |
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| 116 | |
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| 117 | * determine if it is time to announce the passing of tick as configured |
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| 118 | * to RTEMS through the rtems_clock_tick directive |
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| 119 | * |
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| 120 | * perform any timer dependent tasks |
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| 121 | */ |
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| 122 | unsigned8 temp; |
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| 123 | |
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| 124 | /* reset the flags of the status register */ |
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| 125 | temp = read8( MTU_TSR0) & MTU0_STAT_MASK; |
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| 126 | write8( temp, MTU_TSR0); |
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| 127 | |
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| 128 | Clock_driver_ticks++ ; |
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| 129 | |
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| 130 | if( Clock_isrs == 1) |
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| 131 | { |
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| 132 | rtems_clock_tick(); |
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| 133 | Clock_isrs = Clock_isrs_const; |
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| 134 | } |
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| 135 | else |
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| 136 | { |
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| 137 | Clock_isrs-- ; |
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| 138 | } |
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| 139 | } |
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| 140 | |
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| 141 | /* |
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| 142 | * Install_clock |
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| 143 | * |
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| 144 | * Install a clock tick handler and reprograms the chip. This |
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| 145 | * is used to initially establish the clock tick. |
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| 146 | */ |
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| 147 | |
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| 148 | void Install_clock( |
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| 149 | rtems_isr_entry clock_isr |
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| 150 | ) |
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| 151 | { |
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| 152 | unsigned8 temp8 = 0; |
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[4dd1aa5] | 153 | unsigned32 factor = 1000000; |
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| 154 | |
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[4a238002] | 155 | |
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| 156 | /* |
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| 157 | * Initialize the clock tick device driver variables |
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| 158 | */ |
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| 159 | |
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| 160 | Clock_driver_ticks = 0; |
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| 161 | Clock_isrs_const = rtems_configuration_get_microseconds_per_tick() / 10000; |
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| 162 | Clock_isrs = Clock_isrs_const; |
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[4dd1aa5] | 163 | |
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| 164 | factor /= rtems_configuration_get_microseconds_per_tick(); /* minimalization of integer division error */ |
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| 165 | Clock_MHZ = rtems_cpu_configuration_get_clicks_per_second() / factor ; |
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[4a238002] | 166 | |
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[0dd1d44] | 167 | rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker ); |
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| 168 | |
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[4a238002] | 169 | /* |
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[0dd1d44] | 170 | * Hardware specific initialize goes here |
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[4a238002] | 171 | */ |
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| 172 | |
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[0dd1d44] | 173 | /* stop Timer 0 */ |
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| 174 | temp8 = read8( MTU_TSTR) & MTU0_STARTMASK; |
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| 175 | write8( temp8, MTU_TSTR); |
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[4a238002] | 176 | |
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[0dd1d44] | 177 | /* set initial counter value to 0 */ |
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| 178 | write16( 0, MTU_TCNT0); |
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[4a238002] | 179 | |
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[0dd1d44] | 180 | /* Timer 0 runs independent */ |
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| 181 | temp8 = read8( MTU_TSYR) & MTU0_SYNCMASK; |
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| 182 | write8( temp8, MTU_TSYR); |
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[4a238002] | 183 | |
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[0dd1d44] | 184 | /* Timer 0 normal mode */ |
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| 185 | temp8 = read8( MTU_TMDR0) & MTU0_MODEMASK; |
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| 186 | write8( temp8, MTU_TMDR0); |
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[4a238002] | 187 | |
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[4dd1aa5] | 188 | /* TCNT is cleared by GRA ; internal clock /16 */ |
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[0dd1d44] | 189 | write8( MTU0_TCRMASK , MTU_TCR0); |
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[4a238002] | 190 | |
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[0dd1d44] | 191 | /* use GRA without I/O - pins */ |
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| 192 | write8( MTU0_TIORVAL, MTU_TIORL0); |
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[4a238002] | 193 | |
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[0dd1d44] | 194 | /* reset flags of the status register */ |
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| 195 | temp8 = read8( MTU_TSR0) & MTU0_STAT_MASK; |
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| 196 | write8( temp8, MTU_TSR0); |
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[4a238002] | 197 | |
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[0dd1d44] | 198 | /* Irq if is equal GRA */ |
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| 199 | temp8 = read8( MTU_TIER0) | MTU0_TIERMASK; |
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| 200 | write8( temp8, MTU_TIER0); |
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[4a238002] | 201 | |
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[0dd1d44] | 202 | /* set interrupt priority */ |
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| 203 | if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL) |
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| 204 | rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); |
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[4a238002] | 205 | |
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[0dd1d44] | 206 | /* set counter limits */ |
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[4dd1aa5] | 207 | write16( _MTU_COUNTER0_MICROSECOND, MTU_GR0A); |
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[4a238002] | 208 | |
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[0dd1d44] | 209 | /* start counter */ |
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| 210 | temp8 = read8( MTU_TSTR) |~MTU0_STARTMASK; |
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| 211 | write8( temp8, MTU_TSTR); |
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[4a238002] | 212 | |
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| 213 | /* |
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| 214 | * Schedule the clock cleanup routine to execute if the application exits. |
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| 215 | */ |
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| 216 | |
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| 217 | atexit( Clock_exit ); |
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| 218 | } |
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| 219 | |
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| 220 | /* |
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| 221 | * Clean up before the application exits |
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| 222 | */ |
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| 223 | |
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| 224 | void Clock_exit( void ) |
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| 225 | { |
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| 226 | unsigned8 temp8 = 0; |
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| 227 | |
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[0dd1d44] | 228 | /* turn off the timer interrupts */ |
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| 229 | /* set interrupt priority to 0 */ |
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| 230 | if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL) |
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| 231 | rtems_fatal_error_occurred( RTEMS_UNSATISFIED); |
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[4a238002] | 232 | |
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| 233 | /* |
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| 234 | * temp16 = read16( MTU_TIER0) & IPRC_MTU0_IRQMASK; |
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| 235 | * write16( temp16, MTU_TIER0); |
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| 236 | */ |
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| 237 | |
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[0dd1d44] | 238 | /* stop counter */ |
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| 239 | temp8 = read8( MTU_TSTR) & MTU0_STARTMASK; |
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| 240 | write8( temp8, MTU_TSTR); |
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[4a238002] | 241 | |
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[0dd1d44] | 242 | /* old vector shall not be installed */ |
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[4a238002] | 243 | } |
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| 244 | |
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| 245 | /* |
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| 246 | * Clock_initialize |
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| 247 | * |
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| 248 | * Device driver entry point for clock tick driver initialization. |
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| 249 | */ |
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| 250 | |
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| 251 | rtems_device_driver Clock_initialize( |
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| 252 | rtems_device_major_number major, |
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| 253 | rtems_device_minor_number minor, |
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| 254 | void *pargp |
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| 255 | ) |
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| 256 | { |
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| 257 | Install_clock( Clock_isr ); |
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| 258 | |
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| 259 | /* |
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| 260 | * make major/minor avail to others such as shared memory driver |
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| 261 | */ |
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| 262 | |
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| 263 | rtems_clock_major = major; |
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| 264 | rtems_clock_minor = minor; |
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| 265 | |
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| 266 | return RTEMS_SUCCESSFUL; |
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| 267 | } |
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| 268 | |
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| 269 | rtems_device_driver Clock_control( |
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| 270 | rtems_device_major_number major, |
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| 271 | rtems_device_minor_number minor, |
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| 272 | void *pargp |
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| 273 | ) |
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| 274 | { |
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| 275 | rtems_unsigned32 isrlevel; |
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| 276 | rtems_libio_ioctl_args_t *args = pargp; |
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| 277 | |
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| 278 | if (args != 0) |
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| 279 | { |
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| 280 | /* |
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| 281 | * This is hokey, but until we get a defined interface |
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| 282 | * to do this, it will just be this simple... |
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| 283 | */ |
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| 284 | |
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| 285 | if (args->command == rtems_build_name('I', 'S', 'R', ' ')) |
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| 286 | { |
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| 287 | Clock_isr(CLOCK_VECTOR); |
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| 288 | } |
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| 289 | else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) |
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| 290 | { |
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| 291 | rtems_isr_entry ignored ; |
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| 292 | rtems_interrupt_disable( isrlevel ); |
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| 293 | rtems_interrupt_catch( args->buffer, CLOCK_VECTOR, &ignored ); |
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| 294 | |
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| 295 | rtems_interrupt_enable( isrlevel ); |
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| 296 | } |
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| 297 | } |
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| 298 | return RTEMS_SUCCESSFUL; |
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| 299 | } |
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