1 | /** |
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2 | * @file |
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3 | * @brief Timer for the Hitachi SH 703X |
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4 | */ |
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5 | |
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6 | /* |
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7 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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8 | * Bernd Becker (becker@faw.uni-ulm.de) |
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9 | * |
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10 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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11 | * |
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12 | * This program is distributed in the hope that it will be useful, |
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13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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15 | * |
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16 | * COPYRIGHT (c) 1998. |
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17 | * On-Line Applications Research Corporation (OAR). |
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18 | * |
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19 | * The license and distribution terms for this file may be |
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20 | * found in the file LICENSE in this distribution or at |
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21 | * http://www.rtems.org/license/LICENSE. |
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22 | */ |
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23 | |
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24 | #include <rtems.h> |
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25 | #include <rtems/btimer.h> |
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26 | |
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27 | #include <rtems/score/sh_io.h> |
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28 | #include <rtems/score/ispsh7032.h> |
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29 | #include <rtems/score/iosh7032.h> |
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30 | |
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31 | extern uint32_t bsp_clicks_per_second; |
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32 | |
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33 | #define I_CLK_PHI_1 0 |
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34 | #define I_CLK_PHI_2 1 |
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35 | #define I_CLK_PHI_4 2 |
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36 | #define I_CLK_PHI_8 3 |
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37 | |
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38 | /* |
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39 | * Set I_CLK_PHI to one of the I_CLK_PHI_X values from above to choose |
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40 | * a PHI/X clock rate. |
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41 | */ |
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42 | |
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43 | #define I_CLK_PHI I_CLK_PHI_4 |
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44 | #define CLOCK_SCALE (1<<I_CLK_PHI) |
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45 | |
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46 | #define ITU1_STARTMASK 0xfd |
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47 | #define ITU1_SYNCMASK 0xfd |
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48 | #define ITU1_MODEMASK 0xfd |
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49 | #define ITU1_TCRMASK (0x00 | I_CLK_PHI) |
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50 | #define ITU1_TIORMASK 0x88 |
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51 | #define ITU1_STAT_MASK 0xf8 |
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52 | #define ITU1_TIERMASK 0xfc |
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53 | #define IPRC_ITU1_MASK 0xfff0 |
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54 | |
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55 | #ifndef ITU1_PRIO |
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56 | #define ITU1_PRIO 15 |
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57 | #endif |
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58 | |
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59 | #define ITU1_VECTOR OVI1_ISP_V |
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60 | |
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61 | extern rtems_isr timerisr(void); |
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62 | |
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63 | static uint32_t Timer_interrupts; |
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64 | |
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65 | bool benchmark_timer_find_average_overhead; |
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66 | |
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67 | static uint32_t Timer_HZ ; |
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68 | |
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69 | void benchmark_timer_initialize( void ) |
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70 | { |
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71 | uint8_t temp8; |
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72 | uint16_t temp16; |
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73 | rtems_interrupt_level level; |
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74 | rtems_isr *ignored; |
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75 | |
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76 | Timer_HZ = bsp_clicks_per_second / CLOCK_SCALE ; |
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77 | |
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78 | /* |
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79 | * Timer has never overflowed. This may not be necessary on some |
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80 | * implemenations of timer but .... |
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81 | */ |
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82 | |
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83 | Timer_interrupts /* .i */ = 0; |
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84 | rtems_interrupt_disable( level ); |
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85 | |
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86 | /* |
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87 | * Somehow start the timer |
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88 | */ |
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89 | /* stop Timer 1 */ |
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90 | temp8 = read8(ITU_TSTR) & ITU1_STARTMASK; |
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91 | write8( temp8, ITU_TSTR ); |
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92 | |
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93 | /* initialize counter 1 */ |
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94 | write16( 0, ITU_TCNT1 ); |
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95 | |
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96 | /* Timer 1 is independent of other timers */ |
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97 | temp8 = read8(ITU_TSNC) & ITU1_SYNCMASK; |
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98 | write8( temp8, ITU_TSNC ); |
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99 | |
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100 | /* Timer 1, normal mode */ |
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101 | temp8 = read8(ITU_TMDR) & ITU1_MODEMASK; |
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102 | write8( temp8, ITU_TMDR ); |
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103 | |
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104 | /* Use a Phi/X counter */ |
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105 | write8( ITU1_TCRMASK, ITU_TCR1 ); |
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106 | |
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107 | /* gra and grb are not used */ |
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108 | write8( ITU1_TIORMASK, ITU_TIOR1 ); |
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109 | |
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110 | /* reset all status flags */ |
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111 | temp8 = read8(ITU_TSR1) & ITU1_STAT_MASK; |
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112 | write8( temp8, ITU_TSR1 ); |
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113 | |
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114 | /* enable overflow interrupt */ |
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115 | write8( ITU1_TIERMASK, ITU_TIER1 ); |
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116 | |
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117 | /* set interrupt priority */ |
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118 | temp16 = read16(INTC_IPRC) & IPRC_ITU1_MASK; |
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119 | temp16 |= ITU1_PRIO; |
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120 | write16( temp16, INTC_IPRC ); |
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121 | |
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122 | /* initialize ISR */ |
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123 | _CPU_ISR_install_raw_handler( ITU1_VECTOR, timerisr, &ignored ); |
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124 | rtems_interrupt_enable( level ); |
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125 | |
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126 | /* start timer 1 */ |
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127 | temp8 = read8(ITU_TSTR) | ~ITU1_STARTMASK; |
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128 | write8( temp8, ITU_TSTR ); |
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129 | } |
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130 | |
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131 | /* |
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132 | * The following controls the behavior of benchmark_timer_read(). |
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133 | * |
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134 | * AVG_OVERHEAD is the overhead for starting and stopping the timer. It |
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135 | * is usually deducted from the number returned. |
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136 | * |
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137 | * LEAST_VALID is the lowest number this routine should trust. Numbers |
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138 | * below this are "noise" and zero is returned. |
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139 | */ |
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140 | |
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141 | #define AVG_OVERHEAD 1 /* It typically takes X.X microseconds */ |
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142 | /* (Y countdowns) to start/stop the timer. */ |
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143 | /* This value is in microseconds. */ |
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144 | #define LEAST_VALID 0 /* 20 */ /* Don't trust a clicks value lower than this */ |
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145 | |
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146 | benchmark_timer_t benchmark_timer_read( void ) |
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147 | { |
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148 | uint32_t cclicks; |
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149 | uint32_t total ; |
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150 | /* |
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151 | * Read the timer and see how many clicks it has been since we started. |
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152 | */ |
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153 | |
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154 | |
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155 | cclicks = read16( ITU_TCNT1 ); /* XXX: read some HW here */ |
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156 | |
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157 | /* |
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158 | * Total is calculated by taking into account the number of timer overflow |
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159 | * interrupts since the timer was initialized and clicks since the last |
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160 | * interrupts. |
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161 | */ |
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162 | |
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163 | total = cclicks + Timer_interrupts * 65536; |
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164 | |
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165 | if ( benchmark_timer_find_average_overhead ) |
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166 | return total / CLOCK_SCALE; /* in XXX microsecond units */ |
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167 | else |
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168 | { |
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169 | if ( total < LEAST_VALID ) |
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170 | return 0; /* below timer resolution */ |
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171 | /* |
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172 | * Somehow convert total into microseconds |
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173 | */ |
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174 | return (total / CLOCK_SCALE - AVG_OVERHEAD); |
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175 | } |
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176 | } |
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177 | |
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178 | void benchmark_timer_disable_subtracting_average_overhead(bool find_flag) |
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179 | { |
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180 | benchmark_timer_find_average_overhead = find_flag; |
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181 | } |
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182 | |
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183 | /* Timer 1 is used */ |
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184 | |
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185 | #pragma interrupt |
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186 | void timerisr( void ) |
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187 | { |
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188 | uint8_t temp8; |
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189 | |
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190 | /* reset the flags of the status register */ |
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191 | temp8 = read8(ITU_TSR1) & ITU1_STAT_MASK; |
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192 | write8( temp8, ITU_TSR1 ); |
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193 | |
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194 | Timer_interrupts += 1; |
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195 | } |
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