source: rtems/c/src/lib/libcpu/sh/sh7032/timer/timer.c @ 8fbe2e6

4.11
Last change on this file since 8fbe2e6 was 8fbe2e6, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 4, 2014 at 1:59:49 PM

Use correct prototype of benchmark_timer_read()

This change starts with removing the effectively empty file
timerdrv.h. The prototypes for benchmark_timer_XXX() were in
btimer.h which was not universally used. Thus every use of
timerdrv.h had to be changed to btimer.h. Then the prototypes
for benchmark_timer_read() had to be adjusted to return
benchmark_timer_t rather than int or uint32_t.

I took this opportunity to also correct the file headers to
separate the copyright from the file description comments which
is needed to ensure the copyright isn't propagated into Doxygen
output.

  • Property mode set to 100644
File size: 4.8 KB
Line 
1/**
2 * @file
3 * @brief Timer for the Hitachi SH 703X
4 */
5
6/*
7 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
8 *           Bernd Becker (becker@faw.uni-ulm.de)
9 *
10 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
11 *
12 *  This program is distributed in the hope that it will be useful,
13 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
14 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
15 *
16 *  COPYRIGHT (c) 1998.
17 *  On-Line Applications Research Corporation (OAR).
18 *
19 *  The license and distribution terms for this file may be
20 *  found in the file LICENSE in this distribution or at
21 *  http://www.rtems.org/license/LICENSE.
22 */
23
24#include <rtems.h>
25#include <rtems/btimer.h>
26
27#include <rtems/score/sh_io.h>
28#include <rtems/score/ispsh7032.h>
29#include <rtems/score/iosh7032.h>
30
31extern uint32_t bsp_clicks_per_second;
32
33#define I_CLK_PHI_1     0
34#define I_CLK_PHI_2     1
35#define I_CLK_PHI_4     2
36#define I_CLK_PHI_8     3
37
38/*
39 * Set I_CLK_PHI to one of the I_CLK_PHI_X values from above to choose
40 * a PHI/X clock rate.
41 */
42
43#define I_CLK_PHI       I_CLK_PHI_4
44#define CLOCK_SCALE     (1<<I_CLK_PHI)
45
46#define ITU1_STARTMASK  0xfd
47#define ITU1_SYNCMASK   0xfd
48#define ITU1_MODEMASK   0xfd
49#define ITU1_TCRMASK    (0x00 | I_CLK_PHI)
50#define ITU1_TIORMASK   0x88
51#define ITU1_STAT_MASK  0xf8
52#define ITU1_TIERMASK   0xfc
53#define IPRC_ITU1_MASK  0xfff0
54
55#ifndef ITU1_PRIO
56#define ITU1_PRIO 15
57#endif
58
59#define ITU1_VECTOR OVI1_ISP_V
60
61extern rtems_isr timerisr(void);
62
63static uint32_t   Timer_interrupts;
64
65bool benchmark_timer_find_average_overhead;
66
67static uint32_t   Timer_HZ ;
68
69void benchmark_timer_initialize( void )
70{
71  uint8_t                temp8;
72  uint16_t               temp16;
73  rtems_interrupt_level  level;
74  rtems_isr             *ignored;
75
76  Timer_HZ = bsp_clicks_per_second / CLOCK_SCALE ;
77
78  /*
79   *  Timer has never overflowed.  This may not be necessary on some
80   *  implemenations of timer but ....
81   */
82
83  Timer_interrupts /* .i */ = 0;
84  rtems_interrupt_disable( level );
85
86  /*
87   *  Somehow start the timer
88   */
89  /* stop Timer 1  */
90  temp8 = read8(ITU_TSTR) & ITU1_STARTMASK;
91  write8( temp8, ITU_TSTR );
92
93  /* initialize counter 1 */
94  write16( 0, ITU_TCNT1 );
95
96  /* Timer 1 is independent of other timers */
97  temp8 = read8(ITU_TSNC) & ITU1_SYNCMASK;
98  write8( temp8, ITU_TSNC );
99
100  /* Timer 1, normal mode */
101  temp8 = read8(ITU_TMDR) & ITU1_MODEMASK;
102  write8( temp8, ITU_TMDR );
103
104  /* Use a Phi/X counter */
105  write8( ITU1_TCRMASK, ITU_TCR1 );
106
107  /* gra and grb are not used */
108  write8( ITU1_TIORMASK, ITU_TIOR1 );
109
110  /* reset all status flags */
111  temp8 = read8(ITU_TSR1) & ITU1_STAT_MASK;
112  write8( temp8, ITU_TSR1 );
113
114  /* enable overflow interrupt */
115  write8( ITU1_TIERMASK, ITU_TIER1 );
116
117  /* set interrupt priority */
118  temp16 = read16(INTC_IPRC) & IPRC_ITU1_MASK;
119  temp16 |= ITU1_PRIO;
120  write16( temp16, INTC_IPRC );
121
122  /* initialize ISR */
123  _CPU_ISR_install_raw_handler( ITU1_VECTOR, timerisr, &ignored );
124  rtems_interrupt_enable( level );
125
126  /* start timer 1 */
127  temp8 = read8(ITU_TSTR) | ~ITU1_STARTMASK;
128  write8( temp8, ITU_TSTR );
129}
130
131/*
132 *  The following controls the behavior of benchmark_timer_read().
133 *
134 *  AVG_OVERHEAD is the overhead for starting and stopping the timer.  It
135 *  is usually deducted from the number returned.
136 *
137 *  LEAST_VALID is the lowest number this routine should trust.  Numbers
138 *  below this are "noise" and zero is returned.
139 */
140
141#define AVG_OVERHEAD      1  /* It typically takes X.X microseconds */
142                             /* (Y countdowns) to start/stop the timer. */
143                             /* This value is in microseconds. */
144#define LEAST_VALID       0 /* 20 */ /* Don't trust a clicks value lower than this */
145
146benchmark_timer_t benchmark_timer_read( void )
147{
148  uint32_t   cclicks;
149  uint32_t   total ;
150  /*
151   *  Read the timer and see how many clicks it has been since we started.
152   */
153
154
155  cclicks = read16( ITU_TCNT1 );    /* XXX: read some HW here */
156
157  /*
158   *  Total is calculated by taking into account the number of timer overflow
159   *  interrupts since the timer was initialized and clicks since the last
160   *  interrupts.
161   */
162
163  total = cclicks + Timer_interrupts * 65536;
164
165  if ( benchmark_timer_find_average_overhead )
166    return total / CLOCK_SCALE;          /* in XXX microsecond units */
167  else
168  {
169    if ( total < LEAST_VALID )
170      return 0;            /* below timer resolution */
171  /*
172   *  Somehow convert total into microseconds
173   */
174    return (total / CLOCK_SCALE - AVG_OVERHEAD);
175  }
176}
177
178void benchmark_timer_disable_subtracting_average_overhead(bool find_flag)
179{
180  benchmark_timer_find_average_overhead = find_flag;
181}
182
183/* Timer 1 is used */
184
185#pragma interrupt
186void timerisr( void )
187{
188  uint8_t   temp8;
189
190  /* reset the flags of the status register */
191  temp8 = read8(ITU_TSR1) & ITU1_STAT_MASK;
192  write8( temp8, ITU_TSR1 );
193
194  Timer_interrupts += 1;
195}
Note: See TracBrowser for help on using the repository browser.