[f8b27df9] | 1 | /* |
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| 2 | * timer for the Hitachi SH 703X |
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| 3 | * |
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| 4 | * This file manages the benchmark timer used by the RTEMS Timing Test |
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| 5 | * Suite. Each measured time period is demarcated by calls to |
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| 6 | * Timer_initialize() and Read_timer(). Read_timer() usually returns |
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| 7 | * the number of microseconds since Timer_initialize() exitted. |
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| 8 | * |
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| 9 | * NOTE: It is important that the timer start/stop overhead be |
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| 10 | * determined when porting or modifying this code. |
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| 11 | * |
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| 12 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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| 13 | * Bernd Becker (becker@faw.uni-ulm.de) |
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| 14 | * |
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| 15 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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| 16 | * |
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| 17 | * This program is distributed in the hope that it will be useful, |
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| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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| 20 | * |
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| 21 | * COPYRIGHT (c) 1998. |
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| 22 | * On-Line Applications Research Corporation (OAR). |
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| 23 | * Copyright assigned to U.S. Government, 1994. |
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| 24 | * |
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| 25 | * The license and distribution terms for this file may be |
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| 26 | * found in the file LICENSE in this distribution or at |
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| 27 | * http://www.OARcorp.com/rtems/license.html. |
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| 28 | * |
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| 29 | * $Id$ |
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| 30 | */ |
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| 31 | |
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[f817b02] | 32 | #include <rtems.h> |
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[f8b27df9] | 33 | |
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| 34 | #include <rtems/score/sh_io.h> |
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[4a238002] | 35 | #include <rtems/score/ispsh7032.h> |
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| 36 | #include <rtems/score/iosh7032.h> |
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| 37 | |
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| 38 | #define I_CLK_PHI_1 0 |
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| 39 | #define I_CLK_PHI_2 1 |
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| 40 | #define I_CLK_PHI_4 2 |
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| 41 | #define I_CLK_PHI_8 3 |
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[f8b27df9] | 42 | |
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| 43 | /* |
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[4a238002] | 44 | * Set I_CLK_PHI to one of the I_CLK_PHI_X values from above to choose |
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| 45 | * a PHI/X clock rate. |
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[f8b27df9] | 46 | */ |
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[4a238002] | 47 | |
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| 48 | #define I_CLK_PHI I_CLK_PHI_4 |
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| 49 | #define CLOCK_SCALE (1<<I_CLK_PHI) |
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[f8b27df9] | 50 | |
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| 51 | #define ITU1_STARTMASK 0xfd |
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| 52 | #define ITU1_SYNCMASK 0xfd |
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| 53 | #define ITU1_MODEMASK 0xfd |
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[4a238002] | 54 | #define ITU1_TCRMASK (0x00 | I_CLK_PHI) |
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[f8b27df9] | 55 | #define ITU1_TIORMASK 0x88 |
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| 56 | #define ITU1_STAT_MASK 0xf8 |
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| 57 | #define ITU1_TIERMASK 0xfc |
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| 58 | #define IPRC_ITU1_MASK 0xfff0 |
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| 59 | |
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| 60 | #ifndef ITU1_PRIO |
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| 61 | #define ITU1_PRIO 15 |
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| 62 | #endif |
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| 63 | |
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[4a238002] | 64 | #define ITU1_VECTOR OVI1_ISP_V |
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[f8b27df9] | 65 | |
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| 66 | rtems_isr timerisr(); |
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| 67 | |
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| 68 | static rtems_unsigned32 Timer_interrupts; |
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| 69 | |
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| 70 | rtems_boolean Timer_driver_Find_average_overhead; |
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| 71 | |
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[4a238002] | 72 | static rtems_unsigned32 Timer_HZ ; |
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| 73 | |
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[f8b27df9] | 74 | void Timer_initialize( void ) |
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| 75 | { |
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[21bfd93] | 76 | rtems_unsigned8 temp8; |
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[f8b27df9] | 77 | rtems_unsigned16 temp16; |
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| 78 | rtems_unsigned32 level; |
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[21bfd93] | 79 | rtems_isr *ignored; |
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[f8b27df9] | 80 | |
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[4a238002] | 81 | Timer_HZ = rtems_cpu_configuration_get_clicks_per_second() / CLOCK_SCALE ; |
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| 82 | |
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[f8b27df9] | 83 | /* |
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| 84 | * Timer has never overflowed. This may not be necessary on some |
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| 85 | * implemenations of timer but .... |
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| 86 | */ |
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| 87 | |
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| 88 | Timer_interrupts /* .i */ = 0; |
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| 89 | _CPU_ISR_Disable( level); |
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| 90 | |
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| 91 | /* |
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| 92 | * Somehow start the timer |
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| 93 | */ |
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| 94 | /* stop Timer 1 */ |
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| 95 | temp8 = read8( ITU_TSTR) & ITU1_STARTMASK; |
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| 96 | write8( temp8, ITU_TSTR); |
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| 97 | |
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| 98 | /* initialize counter 1 */ |
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| 99 | write16( 0, ITU_TCNT1); |
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| 100 | |
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| 101 | /* Timer 1 is independent of other timers */ |
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| 102 | temp8 = read8( ITU_TSNC) & ITU1_SYNCMASK; |
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| 103 | write8( temp8, ITU_TSNC); |
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| 104 | |
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| 105 | /* Timer 1, normal mode */ |
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| 106 | temp8 = read8( ITU_TMDR) & ITU1_MODEMASK; |
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| 107 | write8( temp8, ITU_TMDR); |
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| 108 | |
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[4a238002] | 109 | /* Use a Phi/X counter */ |
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[f8b27df9] | 110 | write8( ITU1_TCRMASK, ITU_TCR1); |
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| 111 | |
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| 112 | /* gra and grb are not used */ |
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| 113 | write8( ITU1_TIORMASK, ITU_TIOR1); |
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| 114 | |
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| 115 | /* reset all status flags */ |
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| 116 | temp8 = read8( ITU_TSR1) & ITU1_STAT_MASK; |
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| 117 | write8( temp8, ITU_TSR1); |
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| 118 | |
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| 119 | /* enable overflow interrupt */ |
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| 120 | write8( ITU1_TIERMASK, ITU_TIER1); |
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| 121 | |
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| 122 | /* set interrupt priority */ |
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| 123 | temp16 = read16( INTC_IPRC) & IPRC_ITU1_MASK; |
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| 124 | temp16 |= ITU1_PRIO; |
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| 125 | write16( temp16, INTC_IPRC); |
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| 126 | |
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| 127 | /* initialize ISR */ |
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[21bfd93] | 128 | _CPU_ISR_install_raw_handler( ITU1_VECTOR, timerisr, &ignored ); |
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[f8b27df9] | 129 | _CPU_ISR_Enable( level); |
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| 130 | |
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| 131 | /* start timer 1 */ |
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| 132 | temp8 = read8( ITU_TSTR) | ~ITU1_STARTMASK; |
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| 133 | write8( temp8, ITU_TSTR); |
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| 134 | } |
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| 135 | |
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| 136 | /* |
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| 137 | * The following controls the behavior of Read_timer(). |
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| 138 | * |
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| 139 | * AVG_OVERHEAD is the overhead for starting and stopping the timer. It |
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| 140 | * is usually deducted from the number returned. |
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| 141 | * |
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| 142 | * LEAST_VALID is the lowest number this routine should trust. Numbers |
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| 143 | * below this are "noise" and zero is returned. |
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| 144 | */ |
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| 145 | |
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| 146 | #define AVG_OVERHEAD 1 /* It typically takes X.X microseconds */ |
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| 147 | /* (Y countdowns) to start/stop the timer. */ |
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| 148 | /* This value is in microseconds. */ |
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| 149 | #define LEAST_VALID 0 /* 20 */ /* Don't trust a clicks value lower than this */ |
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| 150 | |
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| 151 | int Read_timer( void ) |
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| 152 | { |
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[4a238002] | 153 | rtems_unsigned32 cclicks; |
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[f8b27df9] | 154 | rtems_unsigned32 total ; |
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| 155 | /* |
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| 156 | * Read the timer and see how many clicks it has been since we started. |
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| 157 | */ |
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| 158 | |
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| 159 | |
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[4a238002] | 160 | cclicks = read16( ITU_TCNT1); /* XXX: read some HW here */ |
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[f8b27df9] | 161 | |
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| 162 | /* |
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| 163 | * Total is calculated by taking into account the number of timer overflow |
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| 164 | * interrupts since the timer was initialized and clicks since the last |
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| 165 | * interrupts. |
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| 166 | */ |
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| 167 | |
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[4a238002] | 168 | total = cclicks + Timer_interrupts * 65536 ; |
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[f8b27df9] | 169 | |
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| 170 | if ( Timer_driver_Find_average_overhead ) |
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[4a238002] | 171 | return total / CLOCK_SCALE; /* in XXX microsecond units */ |
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[f8b27df9] | 172 | else |
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| 173 | { |
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| 174 | if ( total < LEAST_VALID ) |
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| 175 | return 0; /* below timer resolution */ |
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| 176 | /* |
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| 177 | * Somehow convert total into microseconds |
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| 178 | */ |
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[4a238002] | 179 | return (total / CLOCK_SCALE - AVG_OVERHEAD) ; |
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[f8b27df9] | 180 | } |
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| 181 | } |
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| 182 | |
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| 183 | /* |
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| 184 | * Empty function call used in loops to measure basic cost of looping |
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| 185 | * in Timing Test Suite. |
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| 186 | */ |
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| 187 | |
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| 188 | rtems_status_code Empty_function( void ) |
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| 189 | { |
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| 190 | return RTEMS_SUCCESSFUL; |
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| 191 | } |
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| 192 | |
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| 193 | void Set_find_average_overhead( |
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| 194 | rtems_boolean find_flag |
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| 195 | ) |
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| 196 | { |
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| 197 | Timer_driver_Find_average_overhead = find_flag; |
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| 198 | } |
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| 199 | |
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| 200 | /* Timer 1 is used */ |
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| 201 | |
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| 202 | #pragma interrupt |
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| 203 | void timerisr( void ) |
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| 204 | { |
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| 205 | unsigned8 temp8; |
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| 206 | |
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| 207 | /* reset the flags of the status register */ |
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| 208 | temp8 = read8( ITU_TSR1) & ITU1_STAT_MASK; |
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| 209 | write8( temp8, ITU_TSR1); |
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| 210 | |
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| 211 | Timer_interrupts += 1; |
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| 212 | } |
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