source: rtems/c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c @ 4a238002

4.104.114.84.95
Last change on this file since 4a238002 was 4a238002, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 18, 1999 at 9:22:58 PM

Patch from "John M. Mills" <jmills@…> with subsequent cleanup from
Ralf Corsepius <corsepiu@…> that adds initial Hitachi SH-2
support to RTEMS. Ralf's comments are:

Changes:
------

  1. SH-Port:
  • Many files renamed.
  • CONSOLE_DEVNAME and MHZ defines removed from libcpu.
  • console.c moved to libbsp/sh/shared, build in libbsp/sh/<BSP>/console applying VPATH.
  • CONSOLE_DEVNAME made BSP-specific, replacement is defined in bsp.h
  • MHZ define replaced with HZ (extendent resolution) in custom/*.cfg
  • -DHZ=HZ used in bspstart.c, only
  • Makefile variable HZ used in bsp-dependent directories only.
  1. SH1-Port
  • clock-driver rewritten to provide better resolution for odd CPU frequencies. This driver is only partially tested on hardware, ie. sightly experimental, but I don't expect severe problems with it.
  • Polling SCI-driver added. This driver is experimental and completly untested yet. Therefore it is not yet used for the console (/dev/console is still pointing to /dev/null, cf. gensh1/bsp.h).
  • minor changes to the timer driver
  • SH1 specific delay()/CPU_delay() now is implemented as a function
  1. SH2-Port
  • Merged
  • IMO, the code is still in its infancy. Therefore I have interspersed comments (FIXME) it for items which I think John should look after.
  • sci and console drivers partially rewritten and extended (John, I hope you don't mind).
  • Copyright notices are not yet adapted
  • Property mode set to 100644
File size: 7.8 KB
Line 
1/*
2 * This file contains the isp frames for the user interrupts.
3 * From these procedures __ISR_Handler is called with the vector number
4 * as argument.
5 *
6 * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
7 * some releases of gcc doesn't properly handle #pragma interrupt, if a
8 * file contains both isrs and normal functions.
9 *
10 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
11 *           Bernd Becker (becker@faw.uni-ulm.de)
12 *
13 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
14 *
15 *  This program is distributed in the hope that it will be useful,
16 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
17 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
18 *
19 *
20 *  COPYRIGHT (c) 1998.
21 *  On-Line Applications Research Corporation (OAR).
22 *  Copyright assigned to U.S. Government, 1994.
23 *
24 *  The license and distribution terms for this file may be
25 *  found in the file LICENSE in this distribution or at
26 *  http://www.OARcorp.com/rtems/license.html.
27 *
28 *  $Id$
29 */
30
31#include <rtems/system.h>
32#include <rtems/score/shtypes.h>
33#include <rtems/score/ispsh7032.h>
34
35#if !defined(sh7032)
36#error Wrong CPU MODEL
37#endif
38
39/*
40 * This is an exception vector table
41 *
42 * It has the same structure like the actual vector table (vectab)
43 */
44proc_ptr _Hardware_isr_Table[256]={
45_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
46_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
47_dummy_isp, _dummy_isp, _dummy_isp,
48_nmi_isp, _usb_isp, 
49_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
50_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
51_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
52_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
53_dummy_isp, _dummy_isp, _dummy_isp, 
54/* trapa 0 -31 */
55_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
56_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
57_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
58_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
59_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
60_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
61_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
62_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
63/* irq 64 ... */
64_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp, 
65_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
66_dma0_isp, _dummy_isp, _dma1_isp, _dummy_isp, 
67_dma2_isp, _dummy_isp, _dma3_isp, _dummy_isp, 
68_imia0_isp, _imib0_isp, _ovi0_isp, _dummy_isp, 
69_imia1_isp, _imib1_isp, _ovi1_isp, _dummy_isp, 
70_imia2_isp, _imib2_isp, _ovi2_isp, _dummy_isp, 
71_imia3_isp, _imib3_isp, _ovi3_isp, _dummy_isp, 
72_imia4_isp, _imib4_isp, _ovi4_isp, _dummy_isp, 
73_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp,
74_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
75_prt_isp, _adu_isp, _dummy_isp, _dummy_isp, 
76_wdt_isp, 
77/* 113 */ _dref_isp
78};
79
80#define Str(a)#a
81
82/*
83 * Some versions of gcc and all version of egcs at least until egcs-1.1b
84 * are not able to handle #pragma interrupt correctly if more than 1 isr is
85 * contained in a file and when optimizing.
86 * We try to work around this problem by using the macro below.
87 */
88#define isp( name, number, func)\
89asm (".global _"Str(name)"\n\t" \
90     "_"Str(name)":       \n\t" \
91     "    mov.l r0,@-r15   \n\t" \
92     "    mov.l r1,@-r15   \n\t" \
93     "    mov.l r2,@-r15   \n\t" \
94     "    mov.l r3,@-r15   \n\t" \
95     "    mov.l r4,@-r15   \n\t" \
96     "    mov.l r5,@-r15   \n\t" \
97     "    mov.l r6,@-r15   \n\t" \
98     "    mov.l r7,@-r15   \n\t" \
99     "    mov.l r14,@-r15  \n\t" \
100     "    sts.l pr,@-r15   \n\t" \
101     "    sts.l mach,@-r15 \n\t" \
102     "    sts.l macl,@-r15 \n\t" \
103     "    mov r15,r14      \n\t" \
104     "    mov.l "Str(name)"_k, r1\n\t" \
105     "    jsr @r1           \n\t" \
106     "    mov #"Str(number)", r4\n\t" \
107     "    mov   r14,r15    \n\t" \
108     "    lds.l @r15+,macl \n\t" \
109     "    lds.l @r15+,mach \n\t" \
110     "    lds.l @r15+,pr   \n\t" \
111     "    mov.l @r15+,r14  \n\t" \
112     "    mov.l @r15+,r7   \n\t" \
113     "    mov.l @r15+,r6   \n\t" \
114     "    mov.l @r15+,r5   \n\t" \
115     "    mov.l @r15+,r4   \n\t" \
116     "    mov.l @r15+,r3   \n\t" \
117     "    mov.l @r15+,r2   \n\t" \
118     "    mov.l @r15+,r1   \n\t" \
119     "    mov.l @r15+,r0   \n\t" \
120     "    rte              \n\t" \
121     "    nop              \n\t" \
122     "    .align 2         \n\t" \
123     #name"_k: \n\t" \
124     ".long "Str(func));
125
126/************************************************
127 * Dummy interrupt service procedure for
128 * interrupts being not allowed --> Trap 34
129 ************************************************/
130asm(" .section .text
131.global __dummy_isp
132__dummy_isp:
133      mov.l r14,@-r15
134      mov   r15, r14
135      trapa #34
136      mov.l @r15+,r14
137      rte
138      nop");
139
140/*****************************
141 * Non maskable interrupt
142 *****************************/
143isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
144
145/*****************************
146 * User break controller
147 *****************************/
148isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
149
150/*****************************
151 *  External interrupts 0-7
152 *****************************/
153isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
154isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler);
155isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler);
156isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler);
157isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler);
158isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler);
159isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler);
160isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler);
161
162/*****************************
163 * DMA - controller
164 *****************************/
165isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
166isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler);
167isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler);
168isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler);
169
170
171/*****************************
172 * Interrupt timer unit
173 *****************************/
174
175/*****************************
176 * Timer 0
177 *****************************/
178isp( _imia0_isp, IMIA0_ISP_V, ___ISR_Handler);
179isp( _imib0_isp, IMIB0_ISP_V, ___ISR_Handler);
180isp( _ovi0_isp,  OVI0_ISP_V, ___ISR_Handler);
181
182/*****************************
183 * Timer 1
184 *****************************/
185isp( _imia1_isp, IMIA1_ISP_V, ___ISR_Handler);
186isp( _imib1_isp, IMIB1_ISP_V, ___ISR_Handler);
187isp( _ovi1_isp,  OVI1_ISP_V, ___ISR_Handler);
188
189/*****************************
190 * Timer 2
191 *****************************/
192isp( _imia2_isp, IMIA2_ISP_V, ___ISR_Handler);
193isp( _imib2_isp, IMIB2_ISP_V, ___ISR_Handler);
194isp( _ovi2_isp,  OVI2_ISP_V, ___ISR_Handler);
195
196/*****************************
197 * Timer 3
198 *****************************/
199isp( _imia3_isp, IMIA3_ISP_V, ___ISR_Handler);
200isp( _imib3_isp, IMIB3_ISP_V, ___ISR_Handler);
201isp( _ovi3_isp,  OVI3_ISP_V, ___ISR_Handler);
202
203/*****************************
204 * Timer 4
205 *****************************/
206isp( _imia4_isp, IMIA4_ISP_V, ___ISR_Handler);
207isp( _imib4_isp, IMIB4_ISP_V, ___ISR_Handler);
208isp( _ovi4_isp,  OVI4_ISP_V, ___ISR_Handler);
209
210
211/*****************************
212 * Serial interfaces
213 *****************************/
214
215/*****************************
216 * Serial interface 0
217 *****************************/
218isp( _eri0_isp,  ERI0_ISP_V, ___ISR_Handler);
219isp( _rxi0_isp,  RXI0_ISP_V, ___ISR_Handler);
220isp( _txi0_isp,  TXI0_ISP_V, ___ISR_Handler);
221isp( _tei0_isp,  TEI0_ISP_V, ___ISR_Handler);
222
223/*****************************
224 * Serial interface 1
225 *****************************/
226isp( _eri1_isp,  ERI1_ISP_V, ___ISR_Handler);
227isp( _rxi1_isp,  RXI1_ISP_V, ___ISR_Handler);
228isp( _txi1_isp,  TXI1_ISP_V, ___ISR_Handler);
229isp( _tei1_isp,  TEI1_ISP_V, ___ISR_Handler);
230
231
232/*****************************
233 * Parity control unit of
234 * the bus state controller
235 *****************************/
236isp( _prt_isp,  PRT_ISP_V, ___ISR_Handler);
237
238
239/******************************
240 * Analog digital converter
241 * ADC
242 ******************************/
243isp( _adu_isp,  ADU_ISP_V, ___ISR_Handler);
244
245
246/******************************
247 *  Watchdog timer
248 ******************************/
249isp( _wdt_isp,  WDT_ISP_V, ___ISR_Handler);
250
251
252/******************************
253 * DRAM refresh control unit
254 * of bus state controller
255 ******************************/
256isp( _dref_isp,  DREF_ISP_V, ___ISR_Handler);
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