source: rtems/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c @ ac815430

4.104.114.84.95
Last change on this file since ac815430 was ac815430, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 14, 2000 at 5:07:54 PM

Patch rtems-rc-20000614-sh.tar.gz from Ralf Corsepius
<corsepiu@…> that migrates the SH port to
multilib'ing. This patch involved moving a number of
files in the CVS repository, adding new files, and
deleting files from their previous location. Ralf
gave good instructions (not repeated here) and here
are his notes:

Note 1: In this version, I did not change the installation points of
the headers which are moved inside of the source-tree. This is a
temporary hack for not breaking compatibility with 4.5 based BSPs,
but will probably not last once having real multilibs (We would have
include file conflicts when several BSPs/CPU_MODELS share a common
installation prefix).

Note 2: I hope not to have broken too much, but I would not be
astonished if something goes wrong.

Note 3: There are more patches to come :)

  • Property mode set to 100644
File size: 6.8 KB
Line 
1/*
2 *  This file contains the basic algorithms for all assembly code used
3 *  in an specific CPU port of RTEMS.  These algorithms must be implemented
4 *  in assembly language
5 *
6 *  NOTE:  This port uses a C file with inline assembler instructions
7 *
8 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
9 *           Bernd Becker (becker@faw.uni-ulm.de)
10 *
11 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
12 *
13 *  This program is distributed in the hope that it will be useful,
14 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
15 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
16 *
17 *
18 *  COPYRIGHT (c) 1998.
19 *  On-Line Applications Research Corporation (OAR).
20 *  Copyright assigned to U.S. Government, 1994.
21 *
22 *  The license and distribution terms for this file may be
23 *  found in the file LICENSE in this distribution or at
24 *  http://www.OARcorp.com/rtems/license.html.
25 *
26 *  $Id$
27 *
28 *  This material may be reproduced by or for the U.S. Government pursuant
29 *  to the copyright license under the clause at DFARS 252.227-7013.  This
30 *  notice must appear in all copies of this file and its derivatives.
31 *
32 */
33
34/*
35 *  This is supposed to be an assembly file.  This means that system.h
36 *  and cpu.h should not be included in a "real" cpu_asm file.  An
37 *  implementation in assembly should include "cpu_asm.h"
38 */
39
40#include <rtems/system.h>
41#include <rtems/score/cpu.h>
42#include <rtems/score/isr.h>
43#include <rtems/score/thread.h>
44#include <rtems/score/sh.h>
45
46#include <rtems/score/ispsh7032.h>
47#include <rtems/score/iosh7032.h>
48#include <rtems/score/sh_io.h>
49
50/* from cpu_isps.c */
51extern proc_ptr         _Hardware_isr_Table[];
52
53#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
54  unsigned long    *_old_stack_ptr;
55#endif
56
57register unsigned long  *stack_ptr asm("r15"); 
58
59/*
60 * sh_set_irq_priority
61 *
62 * this function sets the interrupt level of the specified interrupt
63 *
64 * parameters:
65 *             - irq : interrupt number
66 *             - prio: priority to set for this interrupt number
67 *
68 * returns:    0 if ok
69 *             -1 on error
70 */
71
72unsigned int sh_set_irq_priority( 
73  unsigned int irq, 
74  unsigned int prio )
75{
76  unsigned32 shiftcount;
77  unsigned32 prioreg;
78  unsigned16 temp16;
79  unsigned32 level;
80
81  /*
82   * first check for valid interrupt
83   */
84  if(( irq > 113) || (_Hardware_isr_Table[irq] == _dummy_isp))
85    return -1;
86  /*
87   * check for valid irq priority
88   */
89  if( prio > 15 )
90    return -1;
91
92  /*
93   * look up appropriate interrupt priority register
94   */
95  if( irq > 71)
96    {
97      irq = irq - 72;
98      shiftcount = 12 - ((irq & ~0x03) % 16);
99     
100      switch( irq / 16)
101        {
102        case 0: { prioreg = INTC_IPRC; break;}
103        case 1: { prioreg = INTC_IPRD; break;}
104        case 2: { prioreg = INTC_IPRE; break;}
105        default: return -1;
106        }
107    }
108  else
109    {
110      shiftcount = 12 - 4 * ( irq % 4);
111      if( irq > 67)
112        prioreg = INTC_IPRB;
113      else
114        prioreg = INTC_IPRA;
115    }
116
117  /*
118   * Set the interrupt priority register
119   */
120  _CPU_ISR_Disable( level );
121
122  temp16 = read16( prioreg);
123  temp16 &= ~( 15 << shiftcount);
124  temp16 |= prio << shiftcount;
125  write16( temp16, prioreg);
126
127  _CPU_ISR_Enable( level );
128
129  return 0;
130}
131
132/*
133 *  _CPU_Context_save_fp_context
134 *
135 *  This routine is responsible for saving the FP context
136 *  at *fp_context_ptr.  If the point to load the FP context
137 *  from is changed then the pointer is modified by this routine.
138 *
139 *  Sometimes a macro implementation of this is in cpu.h which dereferences
140 *  the ** and a similarly named routine in this file is passed something
141 *  like a (Context_Control_fp *).  The general rule on making this decision
142 *  is to avoid writing assembly language.
143 */
144
145void _CPU_Context_save_fp(
146  void **fp_context_ptr
147)
148{
149}
150
151/*
152 *  _CPU_Context_restore_fp_context
153 *
154 *  This routine is responsible for restoring the FP context
155 *  at *fp_context_ptr.  If the point to load the FP context
156 *  from is changed then the pointer is modified by this routine.
157 *
158 *  Sometimes a macro implementation of this is in cpu.h which dereferences
159 *  the ** and a similarly named routine in this file is passed something
160 *  like a (Context_Control_fp *).  The general rule on making this decision
161 *  is to avoid writing assembly language.
162 */
163
164void _CPU_Context_restore_fp(
165  void **fp_context_ptr
166)
167{
168}
169
170/*  _CPU_Context_switch
171 *
172 *  This routine performs a normal non-FP context switch.
173 */
174
175/*  within __CPU_Context_switch:
176 *  _CPU_Context_switch
177 *  _CPU_Context_restore
178 *
179 *  This routine is generally used only to restart self in an
180 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
181 *
182 * NOTE: It should be safe not to store r4, r5
183 *
184 * NOTE: It is doubtful if r0 is really needed to be stored
185 *
186 * NOTE: gbr is added, but should not be necessary, as it is
187 *      only used globally in this port.
188 */
189
190/*
191 * FIXME: This is an ugly hack, but we wanted to avoid recalculating
192 *        the offset each time Context_Control is changed
193 */
194void __CPU_Context_switch(
195  Context_Control  *run,        /* r4 */
196  Context_Control  *heir        /* r5 */
197)
198{
199
200asm volatile("
201        .global __CPU_Context_switch
202__CPU_Context_switch:
203
204        add     %0,r4
205 
206        stc.l   sr,@-r4
207        stc.l   gbr,@-r4
208        mov.l   r0,@-r4
209        mov.l   r1,@-r4
210        mov.l   r2,@-r4
211        mov.l   r3,@-r4
212
213        mov.l   r6,@-r4
214        mov.l   r7,@-r4
215        mov.l   r8,@-r4
216        mov.l   r9,@-r4
217        mov.l   r10,@-r4
218        mov.l   r11,@-r4
219        mov.l   r12,@-r4
220        mov.l   r13,@-r4
221        mov.l   r14,@-r4
222        sts.l   pr,@-r4
223        sts.l   mach,@-r4
224        sts.l   macl,@-r4
225        mov.l   r15,@-r4
226
227        mov     r5, r4"
228  :: "I" (sizeof(Context_Control))
229  );
230
231  asm volatile("
232        .global __CPU_Context_restore
233__CPU_Context_restore:
234        mov.l   @r4+,r15
235        lds.l   @r4+,macl
236        lds.l   @r4+,mach
237        lds.l   @r4+,pr
238        mov.l   @r4+,r14
239        mov.l   @r4+,r13
240        mov.l   @r4+,r12
241        mov.l   @r4+,r11
242        mov.l   @r4+,r10
243        mov.l   @r4+,r9
244        mov.l   @r4+,r8
245        mov.l   @r4+,r7
246        mov.l   @r4+,r6
247
248        mov.l   @r4+,r3
249        mov.l   @r4+,r2
250        mov.l   @r4+,r1
251        mov.l   @r4+,r0
252        ldc.l   @r4+,gbr
253        ldc.l   @r4+,sr
254
255        rts
256        nop" );
257}
258
259/* 
260 *  This routine provides the RTEMS interrupt management.
261 */
262 
263void __ISR_Handler( unsigned32 vector)
264{
265  register unsigned32 level;
266
267  _CPU_ISR_Disable( level );
268
269  _Thread_Dispatch_disable_level++;
270
271#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
272  if( _ISR_Nest_level == 0 )
273    {
274      /* Install irq stack */
275      _old_stack_ptr = stack_ptr;
276      stack_ptr = _CPU_Interrupt_stack_high;
277    }
278
279#endif
280
281  _ISR_Nest_level++;
282
283  _CPU_ISR_Enable( level );
284
285  /* call isp */
286  if( _ISR_Vector_table[ vector])
287    (*_ISR_Vector_table[ vector ])( vector );
288
289  _CPU_ISR_Disable( level );
290
291  _ISR_Nest_level--;
292
293#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
294
295  if( _ISR_Nest_level == 0 )
296    /* restore old stack pointer */
297    stack_ptr = _old_stack_ptr; 
298#endif
299
300  _Thread_Dispatch_disable_level--;
301
302  _CPU_ISR_Enable( level );
303
304  if ( _Thread_Dispatch_disable_level == 0 )
305    {
306      if(( _Context_Switch_necessary) || (! _ISR_Signals_to_thread_executing))
307        {
308          _ISR_Signals_to_thread_executing = FALSE;
309          _Thread_Dispatch();
310        }
311  }
312}
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