source: rtems/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c @ 9518a5b

4.104.114.84.95
Last change on this file since 9518a5b was 9518a5b, checked in by Joel Sherrill <joel.sherrill@…>, on Feb 11, 2003 at 11:29:06 PM

2003-02-11 Joel Sherrill <joel@…>

  • score/cpu_asm.c: Rework logic that decides when to call _Thread_Dispatch. Analysis by Sergei Organov <osv@…> determined that _ISR_Signals_to_thread_executing was not being honored and/or cleared properly.
  • Property mode set to 100644
File size: 7.1 KB
Line 
1/*
2 *  This file contains the basic algorithms for all assembly code used
3 *  in an specific CPU port of RTEMS.  These algorithms must be implemented
4 *  in assembly language
5 *
6 *  NOTE:  This port uses a C file with inline assembler instructions
7 *
8 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
9 *           Bernd Becker (becker@faw.uni-ulm.de)
10 *
11 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
12 *
13 *  This program is distributed in the hope that it will be useful,
14 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
15 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
16 *
17 *
18 *  COPYRIGHT (c) 1998.
19 *  On-Line Applications Research Corporation (OAR).
20 *
21 *  The license and distribution terms for this file may be
22 *  found in the file LICENSE in this distribution or at
23 *  http://www.OARcorp.com/rtems/license.html.
24 *
25 *  $Id$
26 *
27 *  This material may be reproduced by or for the U.S. Government pursuant
28 *  to the copyright license under the clause at DFARS 252.227-7013.  This
29 *  notice must appear in all copies of this file and its derivatives.
30 *
31 */
32
33/*
34 *  This is supposed to be an assembly file.  This means that system.h
35 *  and cpu.h should not be included in a "real" cpu_asm file.  An
36 *  implementation in assembly should include "cpu_asm.h"
37 */
38
39#include <rtems/system.h>
40#include <rtems/score/cpu.h>
41#include <rtems/score/isr.h>
42#include <rtems/score/thread.h>
43#include <rtems/score/sh.h>
44
45#include <rtems/score/ispsh7032.h>
46#include <rtems/score/iosh7032.h>
47#include <rtems/score/sh_io.h>
48
49/* from cpu_isps.c */
50extern proc_ptr         _Hardware_isr_Table[];
51
52#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
53  unsigned long    *_old_stack_ptr;
54#endif
55
56register unsigned long  *stack_ptr asm("r15"); 
57
58/*
59 * sh_set_irq_priority
60 *
61 * this function sets the interrupt level of the specified interrupt
62 *
63 * parameters:
64 *             - irq : interrupt number
65 *             - prio: priority to set for this interrupt number
66 *
67 * returns:    0 if ok
68 *             -1 on error
69 */
70
71unsigned int sh_set_irq_priority( 
72  unsigned int irq, 
73  unsigned int prio )
74{
75  unsigned32 shiftcount;
76  unsigned32 prioreg;
77  unsigned16 temp16;
78  unsigned32 level;
79
80  /*
81   * first check for valid interrupt
82   */
83  if(( irq > 113) || (_Hardware_isr_Table[irq] == _dummy_isp))
84    return -1;
85  /*
86   * check for valid irq priority
87   */
88  if( prio > 15 )
89    return -1;
90
91  /*
92   * look up appropriate interrupt priority register
93   */
94  if( irq > 71)
95    {
96      irq = irq - 72;
97      shiftcount = 12 - ((irq & ~0x03) % 16);
98     
99      switch( irq / 16)
100        {
101        case 0: { prioreg = INTC_IPRC; break;}
102        case 1: { prioreg = INTC_IPRD; break;}
103        case 2: { prioreg = INTC_IPRE; break;}
104        default: return -1;
105        }
106    }
107  else
108    {
109      shiftcount = 12 - 4 * ( irq % 4);
110      if( irq > 67)
111        prioreg = INTC_IPRB;
112      else
113        prioreg = INTC_IPRA;
114    }
115
116  /*
117   * Set the interrupt priority register
118   */
119  _CPU_ISR_Disable( level );
120
121  temp16 = read16( prioreg);
122  temp16 &= ~( 15 << shiftcount);
123  temp16 |= prio << shiftcount;
124  write16( temp16, prioreg);
125
126  _CPU_ISR_Enable( level );
127
128  return 0;
129}
130
131/*
132 *  _CPU_Context_save_fp_context
133 *
134 *  This routine is responsible for saving the FP context
135 *  at *fp_context_ptr.  If the point to load the FP context
136 *  from is changed then the pointer is modified by this routine.
137 *
138 *  Sometimes a macro implementation of this is in cpu.h which dereferences
139 *  the ** and a similarly named routine in this file is passed something
140 *  like a (Context_Control_fp *).  The general rule on making this decision
141 *  is to avoid writing assembly language.
142 */
143
144void _CPU_Context_save_fp(
145  void **fp_context_ptr
146)
147{
148}
149
150/*
151 *  _CPU_Context_restore_fp_context
152 *
153 *  This routine is responsible for restoring the FP context
154 *  at *fp_context_ptr.  If the point to load the FP context
155 *  from is changed then the pointer is modified by this routine.
156 *
157 *  Sometimes a macro implementation of this is in cpu.h which dereferences
158 *  the ** and a similarly named routine in this file is passed something
159 *  like a (Context_Control_fp *).  The general rule on making this decision
160 *  is to avoid writing assembly language.
161 */
162
163void _CPU_Context_restore_fp(
164  void **fp_context_ptr
165)
166{
167}
168
169/*  _CPU_Context_switch
170 *
171 *  This routine performs a normal non-FP context switch.
172 */
173
174/*  within __CPU_Context_switch:
175 *  _CPU_Context_switch
176 *  _CPU_Context_restore
177 *
178 *  This routine is generally used only to restart self in an
179 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
180 *
181 * NOTE: It should be safe not to store r4, r5
182 *
183 * NOTE: It is doubtful if r0 is really needed to be stored
184 *
185 * NOTE: gbr is added, but should not be necessary, as it is
186 *      only used globally in this port.
187 */
188
189/*
190 * FIXME: This is an ugly hack, but we wanted to avoid recalculating
191 *        the offset each time Context_Control is changed
192 */
193void __CPU_Context_switch(
194  Context_Control  *run,        /* r4 */
195  Context_Control  *heir        /* r5 */
196)
197{
198
199asm volatile(
200        ".global __CPU_Context_switch\n"
201"__CPU_Context_switch:\n"
202
203"       add     %0,r4\n"
204 
205"       stc.l   sr,@-r4\n"
206"       stc.l   gbr,@-r4\n"
207"       mov.l   r0,@-r4\n"
208"       mov.l   r1,@-r4\n"
209"       mov.l   r2,@-r4\n"
210"       mov.l   r3,@-r4\n"
211
212"       mov.l   r6,@-r4\n"
213"       mov.l   r7,@-r4\n"
214"       mov.l   r8,@-r4\n"
215"       mov.l   r9,@-r4\n"
216"       mov.l   r10,@-r4\n"
217"       mov.l   r11,@-r4\n"
218"       mov.l   r12,@-r4\n"
219"       mov.l   r13,@-r4\n"
220"       mov.l   r14,@-r4\n"
221"       sts.l   pr,@-r4\n"
222"       sts.l   mach,@-r4\n"
223"       sts.l   macl,@-r4\n"
224"       mov.l   r15,@-r4\n"
225
226"       mov     r5, r4\n"
227  :: "I" (sizeof(Context_Control))
228  );
229
230  asm volatile(
231        ".global __CPU_Context_restore\n"
232"__CPU_Context_restore:\n"
233"       mov.l   @r4+,r15\n"
234"       lds.l   @r4+,macl\n"
235"       lds.l   @r4+,mach\n"
236"       lds.l   @r4+,pr\n"
237"       mov.l   @r4+,r14\n"
238"       mov.l   @r4+,r13\n"
239"       mov.l   @r4+,r12\n"
240"       mov.l   @r4+,r11\n"
241"       mov.l   @r4+,r10\n"
242"       mov.l   @r4+,r9\n"
243"       mov.l   @r4+,r8\n"
244"       mov.l   @r4+,r7\n"
245"       mov.l   @r4+,r6\n"
246
247"       mov.l   @r4+,r3\n"
248"       mov.l   @r4+,r2\n"
249"       mov.l   @r4+,r1\n"
250"       mov.l   @r4+,r0\n"
251"       ldc.l   @r4+,gbr\n"
252"       ldc.l   @r4+,sr\n"
253
254"       rts\n"
255"       nop\n" );
256}
257
258/* 
259 *  This routine provides the RTEMS interrupt management.
260 */
261 
262void __ISR_Handler( unsigned32 vector)
263{
264  register unsigned32 level;
265
266  _CPU_ISR_Disable( level );
267
268  _Thread_Dispatch_disable_level++;
269
270#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
271  if( _ISR_Nest_level == 0 )
272    {
273      /* Install irq stack */
274      _old_stack_ptr = stack_ptr;
275      stack_ptr = _CPU_Interrupt_stack_high;
276    }
277
278#endif
279
280  _ISR_Nest_level++;
281
282  _CPU_ISR_Enable( level );
283
284  /* call isp */
285  if( _ISR_Vector_table[ vector])
286    (*_ISR_Vector_table[ vector ])( vector );
287
288  _CPU_ISR_Disable( level );
289
290  _Thread_Dispatch_disable_level--;
291
292  _ISR_Nest_level--;
293
294#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
295
296  if( _ISR_Nest_level == 0 )
297    /* restore old stack pointer */
298    stack_ptr = _old_stack_ptr; 
299#endif
300
301  _CPU_ISR_Enable( level );
302
303  if ( _ISR_Nest_level )
304    return;
305
306  if ( _Thread_Dispatch_disable_level ) {
307    _ISR_Signals_to_thread_executing = FALSE;
308    return;
309  }
310
311  if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
312    _ISR_Signals_to_thread_executing = FALSE;
313    _Thread_Dispatch();
314  }
315}
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