1 | /* |
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2 | * This file contains the basic algorithms for all assembly code used |
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3 | * in an specific CPU port of RTEMS. These algorithms must be implemented |
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4 | * in assembly language |
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5 | * |
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6 | * NOTE: This port uses a C file with inline assembler instructions |
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7 | * |
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8 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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9 | * Bernd Becker (becker@faw.uni-ulm.de) |
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10 | * |
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11 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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12 | * |
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13 | * This program is distributed in the hope that it will be useful, |
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14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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16 | * |
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17 | * |
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18 | * COPYRIGHT (c) 1998. |
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19 | * On-Line Applications Research Corporation (OAR). |
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20 | * |
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21 | * The license and distribution terms for this file may be |
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22 | * found in the file LICENSE in this distribution or at |
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23 | * http://www.rtems.com/license/LICENSE. |
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24 | * |
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25 | * $Id$ |
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26 | * |
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27 | */ |
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28 | |
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29 | /* |
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30 | * This is supposed to be an assembly file. This means that system.h |
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31 | * and cpu.h should not be included in a "real" cpu_asm file. An |
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32 | * implementation in assembly should include "cpu_asm.h" |
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33 | */ |
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34 | |
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35 | #include <rtems/system.h> |
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36 | #include <rtems/score/cpu.h> |
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37 | #include <rtems/score/isr.h> |
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38 | #include <rtems/score/thread.h> |
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39 | #include <rtems/score/sh.h> |
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40 | |
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41 | #include <rtems/score/ispsh7032.h> |
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42 | #include <rtems/score/iosh7032.h> |
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43 | #include <rtems/score/sh_io.h> |
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44 | |
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45 | /* from cpu_isps.c */ |
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46 | extern proc_ptr _Hardware_isr_Table[]; |
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47 | |
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48 | #if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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49 | unsigned long *_old_stack_ptr; |
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50 | #endif |
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51 | |
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52 | register unsigned long *stack_ptr asm("r15"); |
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53 | |
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54 | /* |
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55 | * sh_set_irq_priority |
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56 | * |
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57 | * this function sets the interrupt level of the specified interrupt |
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58 | * |
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59 | * parameters: |
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60 | * - irq : interrupt number |
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61 | * - prio: priority to set for this interrupt number |
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62 | * |
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63 | * returns: 0 if ok |
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64 | * -1 on error |
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65 | */ |
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66 | |
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67 | unsigned int sh_set_irq_priority( |
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68 | unsigned int irq, |
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69 | unsigned int prio ) |
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70 | { |
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71 | uint32_t shiftcount; |
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72 | uint32_t prioreg; |
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73 | uint16_t temp16; |
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74 | ISR_Level level; |
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75 | |
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76 | /* |
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77 | * first check for valid interrupt |
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78 | */ |
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79 | if (( irq > 113) || (_Hardware_isr_Table[irq] == _dummy_isp)) |
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80 | return -1; |
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81 | /* |
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82 | * check for valid irq priority |
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83 | */ |
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84 | if ( prio > 15 ) |
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85 | return -1; |
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86 | |
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87 | /* |
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88 | * look up appropriate interrupt priority register |
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89 | */ |
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90 | if ( irq > 71) |
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91 | { |
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92 | irq = irq - 72; |
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93 | shiftcount = 12 - ((irq & ~0x03) % 16); |
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94 | |
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95 | switch( irq / 16) |
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96 | { |
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97 | case 0: { prioreg = INTC_IPRC; break;} |
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98 | case 1: { prioreg = INTC_IPRD; break;} |
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99 | case 2: { prioreg = INTC_IPRE; break;} |
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100 | default: return -1; |
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101 | } |
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102 | } |
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103 | else |
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104 | { |
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105 | shiftcount = 12 - 4 * ( irq % 4); |
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106 | if ( irq > 67) |
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107 | prioreg = INTC_IPRB; |
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108 | else |
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109 | prioreg = INTC_IPRA; |
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110 | } |
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111 | |
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112 | /* |
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113 | * Set the interrupt priority register |
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114 | */ |
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115 | _ISR_Disable( level ); |
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116 | |
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117 | temp16 = read16( prioreg); |
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118 | temp16 &= ~( 15 << shiftcount); |
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119 | temp16 |= prio << shiftcount; |
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120 | write16( temp16, prioreg); |
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121 | |
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122 | _ISR_Enable( level ); |
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123 | |
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124 | return 0; |
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125 | } |
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126 | |
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127 | /* |
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128 | * This routine provides the RTEMS interrupt management. |
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129 | */ |
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130 | |
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131 | void __ISR_Handler( uint32_t vector) |
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132 | { |
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133 | ISR_Level level; |
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134 | |
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135 | _ISR_Disable( level ); |
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136 | |
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137 | _Thread_Dispatch_disable_level++; |
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138 | |
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139 | #if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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140 | if ( _ISR_Nest_level == 0 ) |
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141 | { |
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142 | /* Install irq stack */ |
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143 | _old_stack_ptr = stack_ptr; |
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144 | stack_ptr = _CPU_Interrupt_stack_high; |
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145 | } |
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146 | |
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147 | #endif |
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148 | |
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149 | _ISR_Nest_level++; |
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150 | |
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151 | _ISR_Enable( level ); |
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152 | |
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153 | /* call isp */ |
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154 | if ( _ISR_Vector_table[ vector]) |
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155 | (*_ISR_Vector_table[ vector ])( vector ); |
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156 | |
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157 | _ISR_Disable( level ); |
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158 | |
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159 | _Thread_Dispatch_disable_level--; |
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160 | |
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161 | _ISR_Nest_level--; |
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162 | |
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163 | #if(CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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164 | |
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165 | if ( _ISR_Nest_level == 0 ) |
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166 | /* restore old stack pointer */ |
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167 | stack_ptr = _old_stack_ptr; |
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168 | #endif |
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169 | |
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170 | _ISR_Enable( level ); |
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171 | |
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172 | if ( _ISR_Nest_level ) |
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173 | return; |
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174 | |
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175 | if ( _Thread_Dispatch_disable_level ) { |
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176 | return; |
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177 | } |
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178 | |
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179 | if ( _Context_Switch_necessary ) { |
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180 | _Thread_Dispatch(); |
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181 | } |
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182 | } |
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