source: rtems/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c @ 4a238002

4.104.114.84.95
Last change on this file since 4a238002 was 4a238002, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 18, 1999 at 9:22:58 PM

Patch from "John M. Mills" <jmills@…> with subsequent cleanup from
Ralf Corsepius <corsepiu@…> that adds initial Hitachi SH-2
support to RTEMS. Ralf's comments are:

Changes:
------

  1. SH-Port:
  • Many files renamed.
  • CONSOLE_DEVNAME and MHZ defines removed from libcpu.
  • console.c moved to libbsp/sh/shared, build in libbsp/sh/<BSP>/console applying VPATH.
  • CONSOLE_DEVNAME made BSP-specific, replacement is defined in bsp.h
  • MHZ define replaced with HZ (extendent resolution) in custom/*.cfg
  • -DHZ=HZ used in bspstart.c, only
  • Makefile variable HZ used in bsp-dependent directories only.
  1. SH1-Port
  • clock-driver rewritten to provide better resolution for odd CPU frequencies. This driver is only partially tested on hardware, ie. sightly experimental, but I don't expect severe problems with it.
  • Polling SCI-driver added. This driver is experimental and completly untested yet. Therefore it is not yet used for the console (/dev/console is still pointing to /dev/null, cf. gensh1/bsp.h).
  • minor changes to the timer driver
  • SH1 specific delay()/CPU_delay() now is implemented as a function
  1. SH2-Port
  • Merged
  • IMO, the code is still in its infancy. Therefore I have interspersed comments (FIXME) it for items which I think John should look after.
  • sci and console drivers partially rewritten and extended (John, I hope you don't mind).
  • Copyright notices are not yet adapted
  • Property mode set to 100644
File size: 7.0 KB
Line 
1/*
2 *  This file contains the basic algorithms for all assembly code used
3 *  in an specific CPU port of RTEMS.  These algorithms must be implemented
4 *  in assembly language
5 *
6 *  NOTE:  This port uses a C file with inline assembler instructions
7 *
8 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
9 *           Bernd Becker (becker@faw.uni-ulm.de)
10 *
11 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
12 *
13 *  This program is distributed in the hope that it will be useful,
14 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
15 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
16 *
17 *
18 *  COPYRIGHT (c) 1998.
19 *  On-Line Applications Research Corporation (OAR).
20 *  Copyright assigned to U.S. Government, 1994.
21 *
22 *  The license and distribution terms for this file may be
23 *  found in the file LICENSE in this distribution or at
24 *  http://www.OARcorp.com/rtems/license.html.
25 *
26 *  $Id$
27 *
28 *  This material may be reproduced by or for the U.S. Government pursuant
29 *  to the copyright license under the clause at DFARS 252.227-7013.  This
30 *  notice must appear in all copies of this file and its derivatives.
31 *
32 */
33
34/*
35 *  This is supposed to be an assembly file.  This means that system.h
36 *  and cpu.h should not be included in a "real" cpu_asm file.  An
37 *  implementation in assembly should include "cpu_asm.h"
38 */
39
40#include <rtems/system.h>
41#include <rtems/score/cpu.h>
42#include <rtems/score/isr.h>
43#include <rtems/score/thread.h>
44#include <rtems/score/sh.h>
45
46#if defined(sh7032)
47#include <rtems/score/ispsh7032.h>
48#include <rtems/score/iosh7032.h>
49#elif defined (sh7045)
50#include <rtems/score/ispsh7045.h>
51#include <rtems/score/iosh7045.h>
52#endif
53
54#include <rtems/score/sh_io.h>
55
56/* from cpu_isps.c */
57extern proc_ptr         _Hardware_isr_Table[];
58
59#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
60  unsigned long    *_old_stack_ptr;
61#endif
62
63register unsigned long  *stack_ptr asm("r15"); 
64
65/*
66 * sh_set_irq_priority
67 *
68 * this function sets the interrupt level of the specified interrupt
69 *
70 * parameters:
71 *             - irq : interrupt number
72 *             - prio: priority to set for this interrupt number
73 *
74 * returns:    0 if ok
75 *             -1 on error
76 */
77
78unsigned int sh_set_irq_priority( 
79  unsigned int irq, 
80  unsigned int prio )
81{
82  unsigned32 shiftcount;
83  unsigned32 prioreg;
84  unsigned16 temp16;
85  unsigned32 level;
86
87  /*
88   * first check for valid interrupt
89   */
90  if(( irq > 113) || (_Hardware_isr_Table[irq] == _dummy_isp))
91    return -1;
92  /*
93   * check for valid irq priority
94   */
95  if( prio > 15 )
96    return -1;
97
98  /*
99   * look up appropriate interrupt priority register
100   */
101  if( irq > 71)
102    {
103      irq = irq - 72;
104      shiftcount = 12 - ((irq & ~0x03) % 16);
105     
106      switch( irq / 16)
107        {
108        case 0: { prioreg = INTC_IPRC; break;}
109        case 1: { prioreg = INTC_IPRD; break;}
110        case 2: { prioreg = INTC_IPRE; break;}
111        default: return -1;
112        }
113    }
114  else
115    {
116      shiftcount = 12 - 4 * ( irq % 4);
117      if( irq > 67)
118        prioreg = INTC_IPRB;
119      else
120        prioreg = INTC_IPRA;
121    }
122
123  /*
124   * Set the interrupt priority register
125   */
126  _CPU_ISR_Disable( level );
127
128  temp16 = read16( prioreg);
129  temp16 &= ~( 15 << shiftcount);
130  temp16 |= prio << shiftcount;
131  write16( temp16, prioreg);
132
133  _CPU_ISR_Enable( level );
134
135  return 0;
136}
137
138/*
139 *  _CPU_Context_save_fp_context
140 *
141 *  This routine is responsible for saving the FP context
142 *  at *fp_context_ptr.  If the point to load the FP context
143 *  from is changed then the pointer is modified by this routine.
144 *
145 *  Sometimes a macro implementation of this is in cpu.h which dereferences
146 *  the ** and a similarly named routine in this file is passed something
147 *  like a (Context_Control_fp *).  The general rule on making this decision
148 *  is to avoid writing assembly language.
149 */
150
151void _CPU_Context_save_fp(
152  void **fp_context_ptr
153)
154{
155}
156
157/*
158 *  _CPU_Context_restore_fp_context
159 *
160 *  This routine is responsible for restoring the FP context
161 *  at *fp_context_ptr.  If the point to load the FP context
162 *  from is changed then the pointer is modified by this routine.
163 *
164 *  Sometimes a macro implementation of this is in cpu.h which dereferences
165 *  the ** and a similarly named routine in this file is passed something
166 *  like a (Context_Control_fp *).  The general rule on making this decision
167 *  is to avoid writing assembly language.
168 */
169
170void _CPU_Context_restore_fp(
171  void **fp_context_ptr
172)
173{
174}
175
176/*  _CPU_Context_switch
177 *
178 *  This routine performs a normal non-FP context switch.
179 */
180
181/*  within __CPU_Context_switch:
182 *  _CPU_Context_switch
183 *  _CPU_Context_restore
184 *
185 *  This routine is generally used only to restart self in an
186 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
187 *
188 * NOTE: It should be safe not to store r4, r5
189 *
190 * NOTE: It is doubtful if r0 is really needed to be stored
191 *
192 * NOTE: gbr is added, but should not be necessary, as it is
193 *      only used globally in this port.
194 */
195
196/*
197 * FIXME: This is an ugly hack, but we wanted to avoid recalculating
198 *        the offset each time Context_Control is changed
199 */
200void __CPU_Context_switch(
201  Context_Control  *run,        /* r4 */
202  Context_Control  *heir        /* r5 */
203)
204{
205
206asm volatile("
207        .global __CPU_Context_switch
208__CPU_Context_switch:
209
210        add     %0,r4
211 
212        stc.l   sr,@-r4
213        stc.l   gbr,@-r4
214        mov.l   r0,@-r4
215        mov.l   r1,@-r4
216        mov.l   r2,@-r4
217        mov.l   r3,@-r4
218
219        mov.l   r6,@-r4
220        mov.l   r7,@-r4
221        mov.l   r8,@-r4
222        mov.l   r9,@-r4
223        mov.l   r10,@-r4
224        mov.l   r11,@-r4
225        mov.l   r12,@-r4
226        mov.l   r13,@-r4
227        mov.l   r14,@-r4
228        sts.l   pr,@-r4
229        sts.l   mach,@-r4
230        sts.l   macl,@-r4
231        mov.l   r15,@-r4
232
233        mov     r5, r4"
234  :: "I" (sizeof(Context_Control))
235  );
236
237  asm volatile("
238        .global __CPU_Context_restore
239__CPU_Context_restore:
240        mov.l   @r4+,r15
241        lds.l   @r4+,macl
242        lds.l   @r4+,mach
243        lds.l   @r4+,pr
244        mov.l   @r4+,r14
245        mov.l   @r4+,r13
246        mov.l   @r4+,r12
247        mov.l   @r4+,r11
248        mov.l   @r4+,r10
249        mov.l   @r4+,r9
250        mov.l   @r4+,r8
251        mov.l   @r4+,r7
252        mov.l   @r4+,r6
253
254        mov.l   @r4+,r3
255        mov.l   @r4+,r2
256        mov.l   @r4+,r1
257        mov.l   @r4+,r0
258        ldc.l   @r4+,gbr
259        ldc.l   @r4+,sr
260
261        rts
262        nop" );
263}
264
265/* 
266 *  This routine provides the RTEMS interrupt management.
267 */
268 
269void __ISR_Handler( unsigned32 vector)
270{
271  register unsigned32 level;
272
273  _CPU_ISR_Disable( level );
274
275  _Thread_Dispatch_disable_level++;
276
277#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
278  if( _ISR_Nest_level == 0 )
279    {
280      /* Install irq stack */
281      _old_stack_ptr = stack_ptr;
282      stack_ptr = _CPU_Interrupt_stack_high;
283    }
284
285#endif
286
287  _ISR_Nest_level++;
288
289  _CPU_ISR_Enable( level );
290
291  /* call isp */
292  if( _ISR_Vector_table[ vector])
293    (*_ISR_Vector_table[ vector ])( vector );
294
295  _CPU_ISR_Disable( level );
296
297  _ISR_Nest_level--;
298
299#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
300
301  if( _ISR_Nest_level == 0 )
302    /* restore old stack pointer */
303    stack_ptr = _old_stack_ptr; 
304#endif
305
306  _Thread_Dispatch_disable_level--;
307
308  _CPU_ISR_Enable( level );
309
310  if ( _Thread_Dispatch_disable_level == 0 )
311    {
312      if(( _Context_Switch_necessary) || (! _ISR_Signals_to_thread_executing))
313        {
314          _ISR_Signals_to_thread_executing = FALSE;
315          _Thread_Dispatch();
316        }
317  }
318}
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