[50cf94da] | 1 | /* |
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| 2 | * This file contains the basic algorithms for all assembly code used |
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| 3 | * in an specific CPU port of RTEMS. These algorithms must be implemented |
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| 4 | * in assembly language |
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| 5 | * |
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| 6 | * NOTE: This port uses a C file with inline assembler instructions |
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| 7 | * |
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| 8 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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| 9 | * Bernd Becker (becker@faw.uni-ulm.de) |
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| 10 | * |
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| 11 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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| 12 | * |
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| 13 | * This program is distributed in the hope that it will be useful, |
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| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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[3906b3ea] | 16 | * |
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[50cf94da] | 17 | * |
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| 18 | * COPYRIGHT (c) 1998. |
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| 19 | * On-Line Applications Research Corporation (OAR). |
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| 20 | * |
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| 21 | * The license and distribution terms for this file may be |
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| 22 | * found in the file LICENSE in this distribution or at |
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[2f399d6] | 23 | * http://www.rtems.com/license/LICENSE. |
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[50cf94da] | 24 | * |
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| 25 | * $Id$ |
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| 26 | * |
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| 27 | */ |
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| 28 | |
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| 29 | /* |
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| 30 | * This is supposed to be an assembly file. This means that system.h |
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| 31 | * and cpu.h should not be included in a "real" cpu_asm file. An |
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| 32 | * implementation in assembly should include "cpu_asm.h" |
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| 33 | */ |
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| 34 | |
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| 35 | #include <rtems/system.h> |
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| 36 | #include <rtems/score/cpu.h> |
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| 37 | #include <rtems/score/isr.h> |
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| 38 | #include <rtems/score/thread.h> |
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| 39 | #include <rtems/score/sh.h> |
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[4a238002] | 40 | |
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| 41 | #include <rtems/score/ispsh7032.h> |
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| 42 | #include <rtems/score/iosh7032.h> |
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| 43 | #include <rtems/score/sh_io.h> |
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[50cf94da] | 44 | |
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| 45 | /* from cpu_isps.c */ |
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| 46 | extern proc_ptr _Hardware_isr_Table[]; |
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| 47 | |
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| 48 | #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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| 49 | unsigned long *_old_stack_ptr; |
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| 50 | #endif |
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| 51 | |
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[3906b3ea] | 52 | register unsigned long *stack_ptr asm("r15"); |
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[50cf94da] | 53 | |
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[3906b3ea] | 54 | /* |
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[50cf94da] | 55 | * sh_set_irq_priority |
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[3906b3ea] | 56 | * |
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[50cf94da] | 57 | * this function sets the interrupt level of the specified interrupt |
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| 58 | * |
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| 59 | * parameters: |
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[3906b3ea] | 60 | * - irq : interrupt number |
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[50cf94da] | 61 | * - prio: priority to set for this interrupt number |
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| 62 | * |
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| 63 | * returns: 0 if ok |
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| 64 | * -1 on error |
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| 65 | */ |
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| 66 | |
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[3906b3ea] | 67 | unsigned int sh_set_irq_priority( |
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| 68 | unsigned int irq, |
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[50cf94da] | 69 | unsigned int prio ) |
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| 70 | { |
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[e96a950b] | 71 | uint32_t shiftcount; |
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| 72 | uint32_t prioreg; |
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| 73 | uint16_t temp16; |
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| 74 | uint32_t level; |
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[50cf94da] | 75 | |
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| 76 | /* |
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| 77 | * first check for valid interrupt |
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| 78 | */ |
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| 79 | if(( irq > 113) || (_Hardware_isr_Table[irq] == _dummy_isp)) |
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| 80 | return -1; |
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| 81 | /* |
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| 82 | * check for valid irq priority |
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| 83 | */ |
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| 84 | if( prio > 15 ) |
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| 85 | return -1; |
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| 86 | |
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| 87 | /* |
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| 88 | * look up appropriate interrupt priority register |
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| 89 | */ |
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| 90 | if( irq > 71) |
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| 91 | { |
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| 92 | irq = irq - 72; |
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| 93 | shiftcount = 12 - ((irq & ~0x03) % 16); |
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[3906b3ea] | 94 | |
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[50cf94da] | 95 | switch( irq / 16) |
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| 96 | { |
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| 97 | case 0: { prioreg = INTC_IPRC; break;} |
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| 98 | case 1: { prioreg = INTC_IPRD; break;} |
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| 99 | case 2: { prioreg = INTC_IPRE; break;} |
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| 100 | default: return -1; |
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| 101 | } |
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| 102 | } |
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| 103 | else |
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| 104 | { |
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| 105 | shiftcount = 12 - 4 * ( irq % 4); |
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| 106 | if( irq > 67) |
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| 107 | prioreg = INTC_IPRB; |
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| 108 | else |
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| 109 | prioreg = INTC_IPRA; |
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| 110 | } |
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| 111 | |
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| 112 | /* |
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| 113 | * Set the interrupt priority register |
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| 114 | */ |
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| 115 | _CPU_ISR_Disable( level ); |
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| 116 | |
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| 117 | temp16 = read16( prioreg); |
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| 118 | temp16 &= ~( 15 << shiftcount); |
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| 119 | temp16 |= prio << shiftcount; |
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| 120 | write16( temp16, prioreg); |
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| 121 | |
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| 122 | _CPU_ISR_Enable( level ); |
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| 123 | |
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| 124 | return 0; |
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| 125 | } |
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| 126 | |
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| 127 | /* |
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| 128 | * _CPU_Context_save_fp_context |
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| 129 | * |
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| 130 | * This routine is responsible for saving the FP context |
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| 131 | * at *fp_context_ptr. If the point to load the FP context |
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| 132 | * from is changed then the pointer is modified by this routine. |
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| 133 | * |
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| 134 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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| 135 | * the ** and a similarly named routine in this file is passed something |
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| 136 | * like a (Context_Control_fp *). The general rule on making this decision |
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| 137 | * is to avoid writing assembly language. |
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| 138 | */ |
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| 139 | |
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| 140 | void _CPU_Context_save_fp( |
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| 141 | void **fp_context_ptr |
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| 142 | ) |
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| 143 | { |
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| 144 | } |
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| 145 | |
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| 146 | /* |
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| 147 | * _CPU_Context_restore_fp_context |
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| 148 | * |
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| 149 | * This routine is responsible for restoring the FP context |
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| 150 | * at *fp_context_ptr. If the point to load the FP context |
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| 151 | * from is changed then the pointer is modified by this routine. |
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| 152 | * |
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| 153 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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| 154 | * the ** and a similarly named routine in this file is passed something |
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| 155 | * like a (Context_Control_fp *). The general rule on making this decision |
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| 156 | * is to avoid writing assembly language. |
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| 157 | */ |
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| 158 | |
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| 159 | void _CPU_Context_restore_fp( |
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| 160 | void **fp_context_ptr |
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| 161 | ) |
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| 162 | { |
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| 163 | } |
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| 164 | |
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| 165 | /* _CPU_Context_switch |
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| 166 | * |
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| 167 | * This routine performs a normal non-FP context switch. |
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| 168 | */ |
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| 169 | |
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| 170 | /* within __CPU_Context_switch: |
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| 171 | * _CPU_Context_switch |
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| 172 | * _CPU_Context_restore |
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| 173 | * |
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| 174 | * This routine is generally used only to restart self in an |
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| 175 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
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| 176 | * |
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| 177 | * NOTE: It should be safe not to store r4, r5 |
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| 178 | * |
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| 179 | * NOTE: It is doubtful if r0 is really needed to be stored |
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| 180 | * |
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| 181 | * NOTE: gbr is added, but should not be necessary, as it is |
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| 182 | * only used globally in this port. |
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| 183 | */ |
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| 184 | |
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| 185 | /* |
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[3906b3ea] | 186 | * FIXME: This is an ugly hack, but we wanted to avoid recalculating |
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[50cf94da] | 187 | * the offset each time Context_Control is changed |
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| 188 | */ |
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| 189 | void __CPU_Context_switch( |
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| 190 | Context_Control *run, /* r4 */ |
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| 191 | Context_Control *heir /* r5 */ |
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| 192 | ) |
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| 193 | { |
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| 194 | |
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[f206b46] | 195 | asm volatile( |
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| 196 | ".global __CPU_Context_switch\n" |
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| 197 | "__CPU_Context_switch:\n" |
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[50cf94da] | 198 | |
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[f206b46] | 199 | " add %0,r4\n" |
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[3906b3ea] | 200 | |
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[f206b46] | 201 | " stc.l sr,@-r4\n" |
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| 202 | " stc.l gbr,@-r4\n" |
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| 203 | " mov.l r0,@-r4\n" |
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| 204 | " mov.l r1,@-r4\n" |
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| 205 | " mov.l r2,@-r4\n" |
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| 206 | " mov.l r3,@-r4\n" |
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[50cf94da] | 207 | |
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[f206b46] | 208 | " mov.l r6,@-r4\n" |
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| 209 | " mov.l r7,@-r4\n" |
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| 210 | " mov.l r8,@-r4\n" |
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| 211 | " mov.l r9,@-r4\n" |
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| 212 | " mov.l r10,@-r4\n" |
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| 213 | " mov.l r11,@-r4\n" |
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| 214 | " mov.l r12,@-r4\n" |
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| 215 | " mov.l r13,@-r4\n" |
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| 216 | " mov.l r14,@-r4\n" |
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| 217 | " sts.l pr,@-r4\n" |
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| 218 | " sts.l mach,@-r4\n" |
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| 219 | " sts.l macl,@-r4\n" |
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| 220 | " mov.l r15,@-r4\n" |
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[50cf94da] | 221 | |
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[f206b46] | 222 | " mov r5, r4\n" |
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[e63a784c] | 223 | :: "i" (sizeof(Context_Control)) |
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[50cf94da] | 224 | ); |
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| 225 | |
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[f206b46] | 226 | asm volatile( |
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| 227 | ".global __CPU_Context_restore\n" |
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| 228 | "__CPU_Context_restore:\n" |
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| 229 | " mov.l @r4+,r15\n" |
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| 230 | " lds.l @r4+,macl\n" |
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| 231 | " lds.l @r4+,mach\n" |
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| 232 | " lds.l @r4+,pr\n" |
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| 233 | " mov.l @r4+,r14\n" |
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| 234 | " mov.l @r4+,r13\n" |
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| 235 | " mov.l @r4+,r12\n" |
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| 236 | " mov.l @r4+,r11\n" |
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| 237 | " mov.l @r4+,r10\n" |
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| 238 | " mov.l @r4+,r9\n" |
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| 239 | " mov.l @r4+,r8\n" |
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| 240 | " mov.l @r4+,r7\n" |
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| 241 | " mov.l @r4+,r6\n" |
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[50cf94da] | 242 | |
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[f206b46] | 243 | " mov.l @r4+,r3\n" |
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| 244 | " mov.l @r4+,r2\n" |
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| 245 | " mov.l @r4+,r1\n" |
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| 246 | " mov.l @r4+,r0\n" |
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| 247 | " ldc.l @r4+,gbr\n" |
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| 248 | " ldc.l @r4+,sr\n" |
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[50cf94da] | 249 | |
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[f206b46] | 250 | " rts\n" |
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| 251 | " nop\n" ); |
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[50cf94da] | 252 | } |
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| 253 | |
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[3906b3ea] | 254 | /* |
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[50cf94da] | 255 | * This routine provides the RTEMS interrupt management. |
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| 256 | */ |
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[3906b3ea] | 257 | |
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[e96a950b] | 258 | void __ISR_Handler( uint32_t vector) |
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[50cf94da] | 259 | { |
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[e96a950b] | 260 | register uint32_t level; |
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[50cf94da] | 261 | |
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| 262 | _CPU_ISR_Disable( level ); |
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| 263 | |
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| 264 | _Thread_Dispatch_disable_level++; |
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| 265 | |
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| 266 | #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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| 267 | if( _ISR_Nest_level == 0 ) |
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| 268 | { |
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| 269 | /* Install irq stack */ |
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| 270 | _old_stack_ptr = stack_ptr; |
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| 271 | stack_ptr = _CPU_Interrupt_stack_high; |
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| 272 | } |
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| 273 | |
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| 274 | #endif |
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| 275 | |
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| 276 | _ISR_Nest_level++; |
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| 277 | |
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| 278 | _CPU_ISR_Enable( level ); |
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| 279 | |
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| 280 | /* call isp */ |
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| 281 | if( _ISR_Vector_table[ vector]) |
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| 282 | (*_ISR_Vector_table[ vector ])( vector ); |
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| 283 | |
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| 284 | _CPU_ISR_Disable( level ); |
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| 285 | |
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[9518a5b] | 286 | _Thread_Dispatch_disable_level--; |
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| 287 | |
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[50cf94da] | 288 | _ISR_Nest_level--; |
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| 289 | |
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| 290 | #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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| 291 | |
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| 292 | if( _ISR_Nest_level == 0 ) |
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| 293 | /* restore old stack pointer */ |
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[3906b3ea] | 294 | stack_ptr = _old_stack_ptr; |
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[50cf94da] | 295 | #endif |
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| 296 | |
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| 297 | _CPU_ISR_Enable( level ); |
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| 298 | |
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[9518a5b] | 299 | if ( _ISR_Nest_level ) |
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| 300 | return; |
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| 301 | |
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| 302 | if ( _Thread_Dispatch_disable_level ) { |
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| 303 | _ISR_Signals_to_thread_executing = FALSE; |
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| 304 | return; |
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| 305 | } |
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| 306 | |
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| 307 | if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) { |
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| 308 | _ISR_Signals_to_thread_executing = FALSE; |
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| 309 | _Thread_Dispatch(); |
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[50cf94da] | 310 | } |
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| 311 | } |
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