source: rtems/c/src/lib/libcpu/sh/sh7032/include/sh7_sci.h @ c8f3e82

Last change on this file since c8f3e82 was 650a5397, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 12, 2001 at 9:01:15 PM

2001-10-12 Joel Sherrill <joel@…>

  • clock/ckinit.c, delay/delay.c, include/iosh7032.h, include/ispsh7032.h, include/sci.h, include/sh7_pfc.h, include/sh7_sci.h, sci/sci.c, score/cpu_asm.c, score/ispsh7032.c, timer/timer.c: Fixed typo.
  • Property mode set to 100644
File size: 2.6 KB
Line 
1/*
2 * Bit values for the serial control registers of the Hitachi SH703X
3 *
4 * From Hitachi tutorials
5 *
6 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
7 *           Bernd Becker (becker@faw.uni-ulm.de)
8 *
9 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
10 *
11 *  This program is distributed in the hope that it will be useful,
12 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
13 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14 *
15 *
16 *  COPYRIGHT (c) 1998.
17 *  On-Line Applications Research Corporation (OAR).
18 *
19 *  The license and distribution terms for this file may be
20 *  found in the file LICENSE in this distribution or at
21 *  http://www.OARcorp.com/rtems/license.html.
22 *
23 *  $Id$
24 */
25
26#ifndef _sh7_sci_h
27#define _sh7_sci_h
28
29#include <rtems/score/iosh7032.h>
30
31/*
32 * Serial mode register bits
33 */
34
35#define SCI_SYNC_MODE               0x80
36#define SCI_SEVEN_BIT_DATA          0x40
37#define SCI_PARITY_ON               0x20
38#define SCI_ODD_PARITY              0x10
39#define SCI_STOP_BITS_2             0x08
40#define SCI_ENABLE_MULTIP           0x04
41#define SCI_PHI_64                  0x03
42#define SCI_PHI_16                  0x02
43#define SCI_PHI_4                   0x01
44#define SCI_PHI_0                   0x00
45
46/*
47 * Serial register offsets, relative to SCI0_SMR or SCI1_SMR
48 */
49
50#define SCI_SMR                 0x00
51#define SCI_BRR                 0x01
52#define SCI_SCR                 0x02
53#define SCI_TDR                 0x03
54#define SCI_SSR                 0x04
55#define SCI_RDR                 0x05
56
57/*
58 * Serial control register bits
59 */
60#define SCI_TIE                 0x80    /* Transmit interrupt enable */
61#define SCI_RIE                 0x40    /* Receive interrupt enable */
62#define SCI_TE                  0x20    /* Transmit enable */
63#define SCI_RE                  0x10    /* Receive enable */
64#define SCI_MPIE                0x08    /* Multiprocessor interrupt enable */
65#define SCI_TEIE                0x04    /* Transmit end interrupt enable */
66#define SCI_CKE1                0x02    /* Clock enable 1 */
67#define SCI_CKE0                0x01    /* Clock enable 0 */
68
69/*
70 * Serial status register bits
71 */
72#define SCI_TDRE                0x80    /* Transmit data register empty */
73#define SCI_RDRF                0x40    /* Receive data register full */
74#define SCI_ORER                0x20    /* Overrun error */
75#define SCI_FER                 0x10    /* Framing error */
76#define SCI_PER                 0x08    /* Parity error */
77#define SCI_TEND                0x04    /* Transmit end */
78#define SCI_MPB                 0x02    /* Multiprocessor bit */
79#define SCI_MPBT                0x01    /* Multiprocessor bit transfer */
80
81#endif /* _sh7_sci_h */
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