1 | /* |
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2 | * Bit values for the pin function controller of the Hitachi SH703X |
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3 | * |
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4 | * From Hitachi tutorials |
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5 | * |
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6 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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7 | * Bernd Becker (becker@faw.uni-ulm.de) |
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8 | * |
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9 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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10 | * |
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11 | * This program is distributed in the hope that it will be useful, |
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12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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14 | * |
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15 | * |
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16 | * COPYRIGHT (c) 1998. |
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17 | * On-Line Applications Research Corporation (OAR). |
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18 | * Copyright assigned to U.S. Government, 1994. |
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19 | * |
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20 | * The license and distribution terms for this file may be |
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21 | * found in the file LICENSE in this distribution or at |
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22 | * http://www.OARcorp.com/rtems/license.html. |
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23 | * |
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24 | * $Id$ |
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25 | */ |
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26 | |
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27 | #ifndef _sh7_pfc_h |
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28 | #define _sh7_pfc_h |
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29 | |
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30 | #include <rtems/score/iosh7030.h> |
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31 | |
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32 | /* |
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33 | * Port B IO Register (PBIOR) |
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34 | */ |
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35 | #define PBIOR PFC_PBIOR |
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36 | #define PB15IOR 0x8000 |
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37 | #define PB14IOR 0x4000 |
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38 | #define PB13IOR 0x2000 |
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39 | #define PB12IOR 0x1000 |
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40 | #define PB11IOR 0x0800 |
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41 | #define PB10IOR 0x0400 |
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42 | #define PB9IOR 0x0200 |
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43 | #define PB8IOR 0x0100 |
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44 | #define PB7IOR 0x0080 |
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45 | #define PB6IOR 0x0040 |
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46 | #define PB5IOR 0x0020 |
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47 | #define PB4IOR 0x0010 |
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48 | #define PB3IOR 0x0008 |
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49 | #define PB2IOR 0x0004 |
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50 | #define PB1IOR 0x0002 |
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51 | #define PB0IOR 0x0001 |
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52 | |
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53 | /* |
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54 | * Port B Control Register (PBCR1) |
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55 | */ |
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56 | #define PBCR1 PFC_PBCR1 |
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57 | #define PB15MD1 0x8000 |
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58 | #define PB15MD0 0x4000 |
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59 | #define PB14MD1 0x2000 |
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60 | #define PB14MD0 0x1000 |
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61 | #define PB13MD1 0x0800 |
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62 | #define PB13MD0 0x0400 |
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63 | #define PB12MD1 0x0200 |
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64 | #define PB12MD0 0x0100 |
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65 | #define PB11MD1 0x0080 |
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66 | #define PB11MD0 0x0040 |
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67 | #define PB10MD1 0x0020 |
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68 | #define PB10MD0 0x0010 |
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69 | #define PB9MD1 0x0008 |
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70 | #define PB9MD0 0x0004 |
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71 | #define PB8MD1 0x0002 |
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72 | #define PB8MD0 0x0001 |
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73 | |
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74 | #define PB15MD PB15MD1|PB14MD0 |
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75 | #define PB14MD PB14MD1|PB14MD0 |
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76 | #define PB13MD PB13MD1|PB13MD0 |
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77 | #define PB12MD PB12MD1|PB12MD0 |
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78 | #define PB11MD PB11MD1|PB11MD0 |
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79 | #define PB10MD PB10MD1|PB10MD0 |
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80 | #define PB9MD PB9MD1|PB9MD0 |
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81 | #define PB8MD PB8MD1|PB8MD0 |
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82 | |
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83 | #define PB_TXD1 PB11MD1 |
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84 | #define PB_RXD1 PB10MD1 |
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85 | #define PB_TXD0 PB9MD1 |
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86 | #define PB_RXD0 PB8MD1 |
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87 | |
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88 | /* |
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89 | * Port B Control Register (PBCR2) |
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90 | */ |
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91 | #define PBCR2 PFC_PBCR2 |
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92 | #define PB7MD1 0x8000 |
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93 | #define PB7MD0 0x4000 |
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94 | #define PB6MD1 0x2000 |
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95 | #define PB6MD0 0x1000 |
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96 | #define PB5MD1 0x0800 |
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97 | #define PB5MD0 0x0400 |
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98 | #define PB4MD1 0x0200 |
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99 | #define PB4MD0 0x0100 |
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100 | #define PB3MD1 0x0080 |
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101 | #define PB3MD0 0x0040 |
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102 | #define PB2MD1 0x0020 |
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103 | #define PB2MD0 0x0010 |
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104 | #define PB1MD1 0x0008 |
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105 | #define PB1MD0 0x0004 |
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106 | #define PB0MD1 0x0002 |
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107 | #define PB0MD0 0x0001 |
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108 | |
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109 | #define PB7MD PB7MD1|PB7MD0 |
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110 | #define PB6MD PB6MD1|PB6MD0 |
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111 | #define PB5MD PB5MD1|PB5MD0 |
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112 | #define PB4MD PB4MD1|PB4MD0 |
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113 | #define PB3MD PB3MD1|PB3MD0 |
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114 | #define PB2MD PB2MD1|PB2MD0 |
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115 | #define PB1MD PB1MD1|PB1MD0 |
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116 | #define PB0MD PB0MD1|PB0MD0 |
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117 | |
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118 | #endif /* _sh7_pfc_h */ |
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