source: rtems/c/src/lib/libcpu/sh/sh7032/include/sh7_pfc.h @ cf59d56b

4.104.114.84.95
Last change on this file since cf59d56b was f8b27df9, checked in by Joel Sherrill <joel.sherrill@…>, on 03/20/98 at 17:20:45

New port from Ralf Corsepius <corsepiu@…>.

  • Property mode set to 100644
File size: 3.1 KB
Line 
1/*
2 * Bit values for the pin function controller of the Hitachi SH703X
3 *
4 * From Hitachi tutorials
5 *
6 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
7 *           Bernd Becker (becker@faw.uni-ulm.de)
8 *
9 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
10 *
11 *  This program is distributed in the hope that it will be useful,
12 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
13 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14 *
15 *
16 *  COPYRIGHT (c) 1998.
17 *  On-Line Applications Research Corporation (OAR).
18 *  Copyright assigned to U.S. Government, 1994.
19 *
20 *  The license and distribution terms for this file may be
21 *  found in the file LICENSE in this distribution or at
22 *  http://www.OARcorp.com/rtems/license.html.
23 *
24 *  $Id$
25 */
26
27#ifndef _sh7_pfc_h
28#define _sh7_pfc_h
29
30#include <rtems/score/iosh7030.h>
31
32/*
33 * Port B IO Register (PBIOR)
34 */
35#define PBIOR           PFC_PBIOR
36#define PB15IOR         0x8000
37#define PB14IOR         0x4000
38#define PB13IOR         0x2000
39#define PB12IOR         0x1000
40#define PB11IOR         0x0800
41#define PB10IOR         0x0400
42#define PB9IOR          0x0200
43#define PB8IOR          0x0100
44#define PB7IOR          0x0080
45#define PB6IOR          0x0040
46#define PB5IOR          0x0020
47#define PB4IOR          0x0010
48#define PB3IOR          0x0008
49#define PB2IOR          0x0004
50#define PB1IOR          0x0002
51#define PB0IOR          0x0001
52
53/*
54 * Port B Control Register (PBCR1)
55 */
56#define PBCR1           PFC_PBCR1
57#define PB15MD1         0x8000
58#define PB15MD0         0x4000
59#define PB14MD1         0x2000
60#define PB14MD0         0x1000
61#define PB13MD1         0x0800
62#define PB13MD0         0x0400
63#define PB12MD1         0x0200
64#define PB12MD0         0x0100
65#define PB11MD1         0x0080
66#define PB11MD0         0x0040
67#define PB10MD1         0x0020
68#define PB10MD0         0x0010
69#define PB9MD1          0x0008
70#define PB9MD0          0x0004
71#define PB8MD1          0x0002
72#define PB8MD0          0x0001
73
74#define PB15MD          PB15MD1|PB14MD0
75#define PB14MD          PB14MD1|PB14MD0
76#define PB13MD          PB13MD1|PB13MD0
77#define PB12MD          PB12MD1|PB12MD0
78#define PB11MD          PB11MD1|PB11MD0
79#define PB10MD          PB10MD1|PB10MD0
80#define PB9MD           PB9MD1|PB9MD0
81#define PB8MD           PB8MD1|PB8MD0
82
83#define PB_TXD1         PB11MD1
84#define PB_RXD1         PB10MD1
85#define PB_TXD0         PB9MD1
86#define PB_RXD0         PB8MD1
87
88/*
89 * Port B Control Register (PBCR2)
90 */
91#define PBCR2   PFC_PBCR2
92#define PB7MD1  0x8000
93#define PB7MD0  0x4000
94#define PB6MD1  0x2000
95#define PB6MD0  0x1000
96#define PB5MD1  0x0800
97#define PB5MD0  0x0400
98#define PB4MD1  0x0200
99#define PB4MD0  0x0100
100#define PB3MD1  0x0080
101#define PB3MD0  0x0040
102#define PB2MD1  0x0020
103#define PB2MD0  0x0010
104#define PB1MD1  0x0008
105#define PB1MD0  0x0004
106#define PB0MD1  0x0002
107#define PB0MD0  0x0001
108       
109#define PB7MD   PB7MD1|PB7MD0
110#define PB6MD   PB6MD1|PB6MD0
111#define PB5MD   PB5MD1|PB5MD0
112#define PB4MD   PB4MD1|PB4MD0
113#define PB3MD   PB3MD1|PB3MD0
114#define PB2MD   PB2MD1|PB2MD0
115#define PB1MD   PB1MD1|PB1MD0
116#define PB0MD   PB0MD1|PB0MD0
117
118#endif /* _sh7_pfc_h */
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