source: rtems/c/src/lib/libcpu/sh/sh7032/include/sh7_pfc.h @ c8f3e82

Last change on this file since c8f3e82 was 650a5397, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 12, 2001 at 9:01:15 PM

2001-10-12 Joel Sherrill <joel@…>

  • clock/ckinit.c, delay/delay.c, include/iosh7032.h, include/ispsh7032.h, include/sci.h, include/sh7_pfc.h, include/sh7_sci.h, sci/sci.c, score/cpu_asm.c, score/ispsh7032.c, timer/timer.c: Fixed typo.
  • Property mode set to 100644
File size: 3.0 KB
Line 
1/*
2 * Bit values for the pin function controller of the Hitachi SH703X
3 *
4 * From Hitachi tutorials
5 *
6 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
7 *           Bernd Becker (becker@faw.uni-ulm.de)
8 *
9 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
10 *
11 *  This program is distributed in the hope that it will be useful,
12 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
13 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14 *
15 *
16 *  COPYRIGHT (c) 1998.
17 *  On-Line Applications Research Corporation (OAR).
18 *
19 *  The license and distribution terms for this file may be
20 *  found in the file LICENSE in this distribution or at
21 *  http://www.OARcorp.com/rtems/license.html.
22 *
23 *  $Id$
24 */
25
26#ifndef _sh7_pfc_h
27#define _sh7_pfc_h
28
29#include <rtems/score/iosh7032.h>
30
31/*
32 * Port B IO Register (PBIOR)
33 */
34#define PBIOR           PFC_PBIOR
35#define PB15IOR         0x8000
36#define PB14IOR         0x4000
37#define PB13IOR         0x2000
38#define PB12IOR         0x1000
39#define PB11IOR         0x0800
40#define PB10IOR         0x0400
41#define PB9IOR          0x0200
42#define PB8IOR          0x0100
43#define PB7IOR          0x0080
44#define PB6IOR          0x0040
45#define PB5IOR          0x0020
46#define PB4IOR          0x0010
47#define PB3IOR          0x0008
48#define PB2IOR          0x0004
49#define PB1IOR          0x0002
50#define PB0IOR          0x0001
51
52/*
53 * Port B Control Register (PBCR1)
54 */
55#define PBCR1           PFC_PBCR1
56#define PB15MD1         0x8000
57#define PB15MD0         0x4000
58#define PB14MD1         0x2000
59#define PB14MD0         0x1000
60#define PB13MD1         0x0800
61#define PB13MD0         0x0400
62#define PB12MD1         0x0200
63#define PB12MD0         0x0100
64#define PB11MD1         0x0080
65#define PB11MD0         0x0040
66#define PB10MD1         0x0020
67#define PB10MD0         0x0010
68#define PB9MD1          0x0008
69#define PB9MD0          0x0004
70#define PB8MD1          0x0002
71#define PB8MD0          0x0001
72
73#define PB15MD          PB15MD1|PB14MD0
74#define PB14MD          PB14MD1|PB14MD0
75#define PB13MD          PB13MD1|PB13MD0
76#define PB12MD          PB12MD1|PB12MD0
77#define PB11MD          PB11MD1|PB11MD0
78#define PB10MD          PB10MD1|PB10MD0
79#define PB9MD           PB9MD1|PB9MD0
80#define PB8MD           PB8MD1|PB8MD0
81
82#define PB_TXD1         PB11MD1
83#define PB_RXD1         PB10MD1
84#define PB_TXD0         PB9MD1
85#define PB_RXD0         PB8MD1
86
87/*
88 * Port B Control Register (PBCR2)
89 */
90#define PBCR2   PFC_PBCR2
91#define PB7MD1  0x8000
92#define PB7MD0  0x4000
93#define PB6MD1  0x2000
94#define PB6MD0  0x1000
95#define PB5MD1  0x0800
96#define PB5MD0  0x0400
97#define PB4MD1  0x0200
98#define PB4MD0  0x0100
99#define PB3MD1  0x0080
100#define PB3MD0  0x0040
101#define PB2MD1  0x0020
102#define PB2MD0  0x0010
103#define PB1MD1  0x0008
104#define PB1MD0  0x0004
105#define PB0MD1  0x0002
106#define PB0MD0  0x0001
107       
108#define PB7MD   PB7MD1|PB7MD0
109#define PB6MD   PB6MD1|PB6MD0
110#define PB5MD   PB5MD1|PB5MD0
111#define PB4MD   PB4MD1|PB4MD0
112#define PB3MD   PB3MD1|PB3MD0
113#define PB2MD   PB2MD1|PB2MD0
114#define PB1MD   PB1MD1|PB1MD0
115#define PB0MD   PB0MD1|PB0MD0
116
117#endif /* _sh7_pfc_h */
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