source: rtems/c/src/lib/libcpu/sh/sh7032/include/ispsh7032.h @ c8f3e82

Last change on this file since c8f3e82 was 49d52e0, checked in by Joel Sherrill <joel.sherrill@…>, on Apr 3, 2002 at 2:09:09 PM

2001-04-03 Joel Sherrill <joel@…>

  • Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
  • include/ispsh7032.h, score/ispsh7032.c: Account for name change.
  • Property mode set to 100644
File size: 3.5 KB
Line 
1/*
2 *  This include file contains information pertaining to the Hitachi SH
3 *  processor.
4 *
5 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
6 *           Bernd Becker (becker@faw.uni-ulm.de)
7 *
8 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
9 *
10 *  This program is distributed in the hope that it will be useful,
11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 *
15 *  COPYRIGHT (c) 1998.
16 *  On-Line Applications Research Corporation (OAR).
17 *
18 *  The license and distribution terms for this file may be
19 *  found in the file LICENSE in this distribution or at
20 *  http://www.OARcorp.com/rtems/license.html.
21 *
22 *  $Id$
23 */
24
25#ifndef __CPU_ISPS_H
26#define __CPU_ISPS_H
27
28#ifdef __cplusplus
29extern "C" {
30#endif
31
32#include <rtems/score/types.h>
33
34extern void __ISR_Handler( unsigned32 vector );
35
36
37/*
38 * interrupt vector table offsets
39 */
40#define NMI_ISP_V 11
41#define USB_ISP_V 12
42#define IRQ0_ISP_V 64
43#define IRQ1_ISP_V 65
44#define IRQ2_ISP_V 66
45#define IRQ3_ISP_V 67
46#define IRQ4_ISP_V 68
47#define IRQ5_ISP_V 69
48#define IRQ6_ISP_V 70
49#define IRQ7_ISP_V 71
50#define DMA0_ISP_V 72
51#define DMA1_ISP_V 74
52#define DMA2_ISP_V 76
53#define DMA3_ISP_V 78
54
55#define IMIA0_ISP_V 80
56#define IMIB0_ISP_V 81
57#define OVI0_ISP_V 82
58
59#define IMIA1_ISP_V 84
60#define IMIB1_ISP_V 85
61#define OVI1_ISP_V 86
62
63#define IMIA2_ISP_V 88
64#define IMIB2_ISP_V 89
65#define OVI2_ISP_V 90
66
67#define IMIA3_ISP_V 92
68#define IMIB3_ISP_V 93
69#define OVI3_ISP_V 94
70
71#define IMIA4_ISP_V 96
72#define IMIB4_ISP_V 97
73#define OVI4_ISP_V 98
74
75#define ERI0_ISP_V 100
76#define RXI0_ISP_V 101
77#define TXI0_ISP_V 102
78#define TEI0_ISP_V 103
79
80#define ERI1_ISP_V 104
81#define RXI1_ISP_V 105
82#define TXI1_ISP_V 106
83#define TEI1_ISP_V 107
84
85#define PRT_ISP_V 108
86#define ADU_ISP_V 109
87#define WDT_ISP_V 112
88#define DREF_ISP_V 113
89
90
91/* dummy ISP */
92extern void _dummy_isp( void );
93
94/* Non Maskable Interrupt */
95extern void _nmi_isp( void );
96
97/* User Break Controller */
98extern void _usb_isp( void );
99
100/* External interrupts 0-7 */
101extern void _irq0_isp( void );
102extern void _irq1_isp( void );
103extern void _irq2_isp( void );
104extern void _irq3_isp( void );
105extern void _irq4_isp( void );
106extern void _irq5_isp( void );
107extern void _irq6_isp( void );
108extern void _irq7_isp( void );
109
110/* DMA - Controller */
111extern void _dma0_isp( void );
112extern void _dma1_isp( void );
113extern void _dma2_isp( void );
114extern void _dma3_isp( void );
115
116/* Interrupt Timer Unit */
117/* Timer 0 */
118extern void _imia0_isp( void );
119extern void _imib0_isp( void );
120extern void _ovi0_isp( void );
121/* Timer 1 */
122extern void _imia1_isp( void );
123extern void _imib1_isp( void );
124extern void _ovi1_isp( void );
125/* Timer 2 */
126extern void _imia2_isp( void );
127extern void _imib2_isp( void );
128extern void _ovi2_isp( void );
129/* Timer 3 */
130extern void _imia3_isp( void );
131extern void _imib3_isp( void );
132extern void _ovi3_isp( void );
133/* Timer 4 */
134extern void _imia4_isp( void );
135extern void _imib4_isp( void );
136extern void _ovi4_isp( void );
137
138/* seriell interfaces */
139extern void _eri0_isp( void );
140extern void _rxi0_isp( void );
141extern void _txi0_isp( void );
142extern void _tei0_isp( void );
143extern void _eri1_isp( void );
144extern void _rxi1_isp( void );
145extern void _txi1_isp( void );
146extern void _tei1_isp( void );
147
148/* Parity Control Unit of the Bus State Controllers */
149extern void _prt_isp( void );
150
151/* ADC */
152extern void _adu_isp( void );
153
154/* Watchdog Timer */
155extern void _wdt_isp( void );
156
157/* DRAM refresh control unit of bus state controller */
158extern void _dref_isp( void );
159
160#ifdef __cplusplus
161}
162#endif
163
164#endif
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