source: rtems/c/src/lib/libcpu/sh/sh7032/include/iosh7032.h @ c8f3e82

Last change on this file since c8f3e82 was 650a5397, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 12, 2001 at 9:01:15 PM

2001-10-12 Joel Sherrill <joel@…>

  • clock/ckinit.c, delay/delay.c, include/iosh7032.h, include/ispsh7032.h, include/sci.h, include/sh7_pfc.h, include/sh7_sci.h, sci/sci.c, score/cpu_asm.c, score/ispsh7032.c, timer/timer.c: Fixed typo.
  • Property mode set to 100644
File size: 7.0 KB
Line 
1/*
2 *  This include file contains information pertaining to the Hitachi SH
3 *  processor.
4 *
5 *  NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
6 *
7 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
8 *           Bernd Becker (becker@faw.uni-ulm.de)
9 *
10 *  Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
11 *  contained no copyright notice.
12 *
13 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
14 *
15 *  This program is distributed in the hope that it will be useful,
16 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
17 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
18 *
19 *
20 *  COPYRIGHT (c) 1998.
21 *  On-Line Applications Research Corporation (OAR).
22 *
23 *  The license and distribution terms for this file may be
24 *  found in the file LICENSE in this distribution or at
25 *  http://www.OARcorp.com/rtems/license.html.
26 *
27 *  $Id$
28 */
29
30#ifndef __IOSH7030_H
31#define __IOSH7030_H
32
33/*
34 * After each line is explained whether the access is char short or long.
35 * The functions read/writeb, w, l, 8, 16, 32 can be found
36 * in exec/score/cpu/sh/sh_io.h
37 *
38 * 8 bit  == char     ( readb, writeb, read8, write8)
39 * 16 bit == short    ( readw, writew, read16, write16 )
40 * 32 bit == long     ( readl, writel, read32, write32 )
41 */
42
43#define SCI0_SMR        0x05fffec0 /* char  */
44#define SCI0_BRR        0x05fffec1 /* char  */
45#define SCI0_SCR        0x05fffec2 /* char  */
46#define SCI0_TDR        0x05fffec3 /* char  */
47#define SCI0_SSR        0x05fffec4 /* char  */
48#define SCI0_RDR        0x05fffec5 /* char  */
49
50#define SCI1_SMR        0x05fffec8 /* char  */
51#define SCI1_BRR        0x05fffec9 /* char  */
52#define SCI1_SCR        0x05fffeca /* char  */
53#define SCI1_TDR        0x05fffecb /* char  */
54#define SCI1_SSR        0x05fffecc /* char  */
55#define SCI1_RDR        0x05fffecd /* char  */
56
57
58#define ADDRAH          0x05fffee0 /* char  */
59#define ADDRAL          0x05fffee1 /* char  */
60#define ADDRBH          0x05fffee2 /* char  */
61#define ADDRBL          0x05fffee3 /* char  */
62#define ADDRCH          0x05fffee4 /* char  */
63#define ADDRCL          0x05fffee5 /* char  */
64#define ADDRDH          0x05fffee6 /* char  */
65#define ADDRDL          0x05fffee7 /* char  */
66#define AD_DRA          0x05fffee0 /* short */
67#define AD_DRB          0x05fffee2 /* short */
68#define AD_DRC          0x05fffee4 /* short */
69#define AD_DRD          0x05fffee6 /* short */
70#define ADCSR           0x05fffee8 /* char  */
71#define ADCR            0x05fffee9 /* char  */
72
73/*ITU SHARED*/
74#define ITU_TSTR        0x05ffff00 /* char  */
75#define ITU_TSNC        0x05ffff01 /* char  */
76#define ITU_TMDR        0x05ffff02 /* char  */
77#define ITU_TFCR        0x05ffff03 /* char  */
78
79/*ITU CHANNEL 0*/
80#define ITU_TCR0        0x05ffff04 /* char  */
81#define ITU_TIOR0       0x05ffff05 /* char  */
82#define ITU_TIER0       0x05ffff06 /* char  */
83#define ITU_TSR0        0x05ffff07 /* char  */
84#define ITU_TCNT0       0x05ffff08 /* short */
85#define ITU_GRA0        0x05ffff0a /* short */
86#define ITU_GRB0        0x05ffff0c /* short */
87
88 /*ITU CHANNEL 1*/
89#define ITU_TCR1        0x05ffff0E /* char  */
90#define ITU_TIOR1       0x05ffff0F /* char  */
91#define ITU_TIER1       0x05ffff10 /* char  */
92#define ITU_TSR1        0x05ffff11 /* char  */
93#define ITU_TCNT1       0x05ffff12 /* short */
94#define ITU_GRA1        0x05ffff14 /* short */
95#define ITU_GRB1        0x05ffff16 /* short */
96
97
98 /*ITU CHANNEL 2*/
99#define ITU_TCR2        0x05ffff18 /* char  */
100#define ITU_TIOR2       0x05ffff19 /* char  */
101#define ITU_TIER2       0x05ffff1A /* char  */
102#define ITU_TSR2        0x05ffff1B /* char  */
103#define ITU_TCNT2       0x05ffff1C /* short */
104#define ITU_GRA2        0x05ffff1E /* short */
105#define ITU_GRB2        0x05ffff20 /* short */
106
107 /*ITU CHANNEL 3*/
108#define ITU_TCR3        0x05ffff22 /* char  */
109#define ITU_TIOR3       0x05ffff23 /* char  */
110#define ITU_TIER3       0x05ffff24 /* char  */
111#define ITU_TSR3        0x05ffff25 /* char  */
112#define ITU_TCNT3       0x05ffff26 /* short */
113#define ITU_GRA3        0x05ffff28 /* short */
114#define ITU_GRB3        0x05ffff2A /* short */
115#define ITU_BRA3        0x05ffff2C /* short */
116#define ITU_BRB3        0x05ffff2E /* short */
117
118 /*ITU CHANNELS 0-4 SHARED*/
119#define ITU_TOCR        0x05ffff31 /* char  */
120
121 /*ITU CHANNEL 4*/
122#define ITU_TCR4        0x05ffff32 /* char  */
123#define ITU_TIOR4       0x05ffff33 /* char  */
124#define ITU_TIER4       0x05ffff34 /* char  */
125#define ITU_TSR4        0x05ffff35 /* char  */
126#define ITU_TCNT4       0x05ffff36 /* short */
127#define ITU_GRA4        0x05ffff38 /* short */
128#define ITU_GRB4        0x05ffff3A /* short */
129#define ITU_BRA4        0x05ffff3C /* short */
130#define ITU_BRB4        0x05ffff3E /* short */
131
132 /*DMAC CHANNELS 0-3 SHARED*/
133#define DMAOR           0x05ffff48 /* short */
134
135 /*DMAC CHANNEL 0*/
136#define DMA_SAR0        0x05ffff40 /* long  */
137#define DMA_DAR0        0x05ffff44 /* long  */
138#define DMA_TCR0        0x05ffff4a /* short */
139#define DMA_CHCR0       0x05ffff4e /* short */
140
141 /*DMAC CHANNEL 1*/
142#define DMA_SAR1        0x05ffff50 /* long  */
143#define DMA_DAR1        0x05ffff54 /* long  */
144#define DMA_TCR1        0x05fffF5a /* short */
145#define DMA_CHCR1       0x05ffff5e /* short */
146
147 /*DMAC CHANNEL 3*/
148#define DMA_SAR3        0x05ffff60 /* long  */
149#define DMA_DAR3        0x05ffff64 /* long  */
150#define DMA_TCR3        0x05fffF6a /* short */
151#define DMA_CHCR3       0x05ffff6e /* short */
152
153/*DMAC CHANNEL 4*/
154#define DMA_SAR4        0x05ffff70 /* long  */
155#define DMA_DAR4        0x05ffff74 /* long  */
156#define DMA_TCR4        0x05fffF7a /* short */
157#define DMA_CHCR4       0x05ffff7e /* short */
158
159/*INTC*/
160#define INTC_IPRA       0x05ffff84 /* short */
161#define INTC_IPRB       0x05ffff86 /* short */
162#define INTC_IPRC       0x05ffff88 /* short */
163#define INTC_IPRD       0x05ffff8A /* short */
164#define INTC_IPRE       0x05ffff8C /* short */
165#define INTC_ICR        0x05ffff8E /* short */
166
167/*UBC*/
168#define UBC_BARH        0x05ffff90 /* short */
169#define UBC_BARL        0x05ffff92 /* short */
170#define UBC_BAMRH       0x05ffff94 /* short */
171#define UBC_BAMRL       0x05ffff96 /* short */
172#define UBC_BBR         0x05ffff98 /* short */
173
174/*BSC*/
175#define BSC_BCR         0x05ffffA0 /* short */
176#define BSC_WCR1        0x05ffffA2 /* short */
177#define BSC_WCR2        0x05ffffA4 /* short */
178#define BSC_WCR3        0x05ffffA6 /* short */
179#define BSC_DCR         0x05ffffA8 /* short */
180#define BSC_PCR         0x05ffffAA /* short */
181#define BSC_RCR         0x05ffffAC /* short */
182#define BSC_RTCSR       0x05ffffAE /* short */
183#define BSC_RTCNT       0x05ffffB0 /* short */
184#define BSC_RTCOR       0x05ffffB2 /* short */
185
186/*WDT*/
187#define WDT_TCSR        0x05ffffB8 /* char  */
188#define WDT_TCNT        0x05ffffB9 /* char  */
189#define WDT_RSTCSR      0x05ffffBB /* char  */
190
191/*POWER DOWN STATE*/
192#define PDT_SBYCR       0x05ffffBC /* char  */
193
194/*PORT A*/
195#define PADR            0x05ffffC0 /* short */
196
197/*PORT B*/
198#define PBDR            0x05ffffC2 /* short */
199
200 /*PORT C*/
201#define PCDR            0x05ffffD0 /* short */
202
203/*PFC*/
204#define PFC_PAIOR       0x05ffffC4 /* short */
205#define PFC_PBIOR       0x05ffffC6 /* short */
206#define PFC_PACR1       0x05ffffC8 /* short */
207#define PFC_PACR2       0x05ffffCA /* short */
208#define PFC_PBCR1       0x05ffffCC /* short */
209#define PFC_PBCR2       0x05ffffCE /* short */
210#define PFC_CASCR       0x05ffffEE /* short */
211
212/*TPC*/
213#define TPC_TPMR        0x05ffffF0 /* short */
214#define TPC_TPCR        0x05ffffF1 /* short */
215#define TPC_NDERH       0x05ffffF2 /* short */
216#define TPC_NDERL       0x05ffffF3 /* short */
217#define TPC_NDRB        0x05ffffF4 /* char  */
218#define TPC_NDRA        0x05ffffF5 /* char  */
219#define TPC_NDRB1       0x05ffffF6 /* char  */
220#define TPC_NDRA1       0x05ffffF7 /* char  */
221
222#endif
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