source: rtems/c/src/lib/libcpu/sh/sh7032/clock/ckinit.c @ c8f3e82

Last change on this file since c8f3e82 was 650a5397, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 12, 2001 at 9:01:15 PM

2001-10-12 Joel Sherrill <joel@…>

  • clock/ckinit.c, delay/delay.c, include/iosh7032.h, include/ispsh7032.h, include/sci.h, include/sh7_pfc.h, include/sh7_sci.h, sci/sci.c, score/cpu_asm.c, score/ispsh7032.c, timer/timer.c: Fixed typo.
  • Property mode set to 100644
File size: 8.4 KB
Line 
1/*
2 *  This file contains the clock driver the Hitachi SH 703X
3 *
4 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
5 *           Bernd Becker (becker@faw.uni-ulm.de)
6 *
7 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
8 *
9 *  This program is distributed in the hope that it will be useful,
10 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
11 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
12 *
13 *
14 *  COPYRIGHT (c) 1998.
15 *  On-Line Applications Research Corporation (OAR).
16 *
17 *  The license and distribution terms for this file may be
18 *  found in the file LICENSE in this distribution or at
19 *  http://www.OARcorp.com/rtems/license.html.
20 *
21 *  $Id$
22 */
23
24#include <rtems.h>
25
26#include <stdlib.h>
27
28#include <rtems/libio.h>
29#include <rtems/score/sh_io.h>
30#include <rtems/score/sh.h>
31#include <rtems/score/ispsh7032.h>
32#include <rtems/score/iosh7032.h>
33
34#ifndef CLOCKPRIO
35#define CLOCKPRIO 10
36#endif
37
38#define I_CLK_PHI_1     0
39#define I_CLK_PHI_2     1
40#define I_CLK_PHI_4     2
41#define I_CLK_PHI_8     3
42
43/*
44 * Set I_CLK_PHI to one of the I_CLK_PHI_X values from above to choose
45 * a PHI/X clock rate.
46 */
47 
48#define I_CLK_PHI       I_CLK_PHI_4
49#define CLOCK_SCALE     (1<<I_CLK_PHI)
50
51#define ITU0_STARTMASK  0xfe
52#define ITU0_SYNCMASK   0xfe
53#define ITU0_MODEMASK   0xfe
54#define ITU0_TCRMASK    (0x20 | I_CLK_PHI)
55#define ITU_STAT_MASK   0xf8
56#define ITU0_IRQMASK    0xfe
57#define ITU0_TIERMASK   0x01
58#define IPRC_ITU0_MASK  0xff0f
59#define ITU0_TIORVAL    0x08
60
61/*
62 * clicks_per_tick := clicks_per_sec * usec_per_tick
63 *
64 * This is a very expensive function ;-)
65 *
66 * Below are two variants:
67 * 1. A variant applying integer arithmetics, only.
68 * 2. A variant applying floating point arithmetics
69 *
70 * The floating point variant pulls in the fmath routines when linking,
71 * resulting in slightly larger executables for applications that do not
72 * apply fmath otherwise. However, the imath variant is significantly slower
73 * than the fmath variant and more complex.
74 *
75 * Assuming that most applications will not use fmath, but are critical
76 * in memory size constraints, we apply the integer variant.
77 *
78 * To the sake of simplicity, we might abandon one of both variants in
79 * future.
80 */
81static unsigned int sh_clicks_per_tick( 
82  unsigned int clicks_per_sec,
83  unsigned int usec_per_tick )
84{
85#if 1
86  unsigned int clicks_per_tick = 0 ;
87 
88  unsigned int b = clicks_per_sec ;
89  unsigned int c = 1000000 ;
90  unsigned int d = 1 ;
91  unsigned int a = ( ( b / c ) * usec_per_tick ) / d;
92
93  clicks_per_tick += a ;
94
95  while ( ( b %= c ) > 0 )
96  {
97    c /= 10 ;
98    d *= 10 ;
99    a = ( ( b / c ) * usec_per_tick ) / d ;
100    clicks_per_tick += a ;
101  } 
102  return clicks_per_tick ;
103#else
104  double fclicks_per_tick = 
105    ((double) clicks_per_sec * (double) usec_per_tick) / 1000000.0 ;
106  return (unsigned32) fclicks_per_tick ;
107#endif
108}
109
110/*
111 *  The interrupt vector number associated with the clock tick device
112 *  driver.
113 */
114
115#define CLOCK_VECTOR IMIA0_ISP_V
116
117/*
118 *  Clock_driver_ticks is a monotonically increasing counter of the
119 *  number of clock ticks since the driver was initialized.
120 */
121
122volatile rtems_unsigned32 Clock_driver_ticks;
123
124static void Clock_exit( void );
125static rtems_isr Clock_isr( rtems_vector_number vector );
126
127/*
128 *  Clock_isrs is the number of clock ISRs until the next invocation of
129 *  the RTEMS clock tick routine.  The clock tick device driver
130 *  gets an interrupt once a millisecond and counts down until the
131 *  length of time between the user configured microseconds per tick
132 *  has passed.
133 */
134
135rtems_unsigned32 Clock_isrs;              /* ISRs until next tick */
136static rtems_unsigned32 Clock_isrs_const;        /* only calculated once */
137
138/*
139 * These are set by clock driver during its init
140 */
141 
142rtems_device_major_number rtems_clock_major = ~0;
143rtems_device_minor_number rtems_clock_minor;
144
145/*
146 *  The previous ISR on this clock tick interrupt vector.
147 */
148
149rtems_isr_entry  Old_ticker;
150
151/*
152 *  Isr Handler
153 */
154
155rtems_isr Clock_isr(
156  rtems_vector_number vector
157)
158{
159  /*
160   * bump the number of clock driver ticks since initialization
161   *
162   * determine if it is time to announce the passing of tick as configured
163   * to RTEMS through the rtems_clock_tick directive
164   *
165   * perform any timer dependent tasks
166   */
167  unsigned8 temp;
168
169  /* reset the flags of the status register */
170  temp = read8( ITU_TSR0) & ITU_STAT_MASK;
171  write8( temp, ITU_TSR0);
172
173  Clock_driver_ticks++ ;
174
175  if( Clock_isrs == 1)
176    {
177      rtems_clock_tick();
178      Clock_isrs = Clock_isrs_const;
179    }
180  else
181    {
182      Clock_isrs-- ;
183    }
184}
185
186/*
187 *  Install_clock
188 *
189 *  Install a clock tick handler and reprograms the chip.  This
190 *  is used to initially establish the clock tick.
191 */
192
193void Install_clock(
194  rtems_isr_entry clock_isr
195)
196{
197  unsigned8 temp8 = 0;
198  unsigned32 microseconds_per_tick ;
199  unsigned32 cclicks_per_tick ;
200  unsigned16 Clock_limit ;
201 
202  /*
203   *  Initialize the clock tick device driver variables
204   */
205
206  Clock_driver_ticks = 0;
207   
208  if ( rtems_configuration_get_microseconds_per_tick() != 0 )
209    microseconds_per_tick = rtems_configuration_get_microseconds_per_tick() ;
210  else
211    microseconds_per_tick = 10000 ; /* 10000 us */
212
213  /* clock clicks per tick */
214  cclicks_per_tick = 
215    sh_clicks_per_tick(
216      rtems_cpu_configuration_get_clicks_per_second() / CLOCK_SCALE,
217      microseconds_per_tick );
218
219  Clock_isrs_const = cclicks_per_tick >> 16 ;
220  if ( ( cclicks_per_tick | 0xffff ) > 0 ) 
221    Clock_isrs_const++ ;
222  Clock_limit = cclicks_per_tick / Clock_isrs_const ;
223  Clock_isrs = Clock_isrs_const;
224
225  rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker );
226  /*
227   *  Hardware specific initialize goes here
228   */
229 
230  /* stop Timer 0 */
231  temp8 = read8( ITU_TSTR) & ITU0_STARTMASK;
232  write8( temp8, ITU_TSTR);
233
234  /* set initial counter value to 0 */
235  write16( 0, ITU_TCNT0);
236
237  /* Timer 0 runs independent */
238  temp8 = read8( ITU_TSNC) & ITU0_SYNCMASK;
239  write8( temp8, ITU_TSNC);
240
241  /* Timer 0 normal mode */
242  temp8 = read8( ITU_TMDR) & ITU0_MODEMASK;
243  write8( temp8, ITU_TMDR);
244
245  /* TCNT is cleared by GRA ; internal clock /4 */
246  write8( ITU0_TCRMASK , ITU_TCR0);
247
248  /* use GRA without I/O - pins  */
249  write8( ITU0_TIORVAL, ITU_TIOR0); 
250   
251  /* reset flags of the status register */
252  temp8 = read8( ITU_TSR0) & ITU_STAT_MASK;
253  write8( temp8, ITU_TSR0);
254
255  /* Irq if is equal GRA */
256  temp8 = read8( ITU_TIER0) | ITU0_TIERMASK;
257  write8( temp8, ITU_TIER0);
258
259  /* set interrupt priority */
260  if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL)
261    rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
262
263  /* set counter limits */
264  write16( Clock_limit, ITU_GRA0);
265   
266  /* start counter */
267  temp8 = read8( ITU_TSTR) |~ITU0_STARTMASK;
268  write8( temp8, ITU_TSTR);
269
270  /*
271   *  Schedule the clock cleanup routine to execute if the application exits.
272   */
273
274  atexit( Clock_exit );
275}
276
277/*
278 *  Clean up before the application exits
279 */
280
281void Clock_exit( void )
282{
283  unsigned8 temp8 = 0;
284
285  /* turn off the timer interrupts */
286  /* set interrupt priority to 0 */
287  if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL)
288    rtems_fatal_error_occurred( RTEMS_UNSATISFIED);
289
290/*
291 *   temp16 = read16( ITU_TIER0) & IPRC_ITU0_IRQMASK;
292 *   write16( temp16, ITU_TIER0);
293 */
294
295  /* stop counter */
296  temp8 = read8( ITU_TSTR) & ITU0_STARTMASK;
297  write8( temp8, ITU_TSTR);
298
299  /* old vector shall not be installed */
300}
301
302/*
303 *  Clock_initialize
304 *
305 *  Device driver entry point for clock tick driver initialization.
306 */
307
308rtems_device_driver Clock_initialize(
309  rtems_device_major_number major,
310  rtems_device_minor_number minor,
311  void *pargp
312)
313{
314  Install_clock( Clock_isr );
315 
316  /*
317   * make major/minor avail to others such as shared memory driver
318   */
319 
320  rtems_clock_major = major;
321  rtems_clock_minor = minor;
322 
323  return RTEMS_SUCCESSFUL;
324}
325
326rtems_device_driver Clock_control(
327  rtems_device_major_number major,
328  rtems_device_minor_number minor,
329  void *pargp
330)
331{
332  rtems_unsigned32 isrlevel;
333  rtems_libio_ioctl_args_t *args = pargp;
334 
335  if (args != 0)
336    {
337      /*
338       * This is hokey, but until we get a defined interface
339       * to do this, it will just be this simple...
340       */
341     
342      if (args->command == rtems_build_name('I', 'S', 'R', ' '))
343        {
344          Clock_isr(CLOCK_VECTOR);
345        }
346      else if (args->command == rtems_build_name('N', 'E', 'W', ' '))
347        {
348          rtems_isr_entry       ignored ;
349          rtems_interrupt_disable( isrlevel );
350          rtems_interrupt_catch( args->buffer, CLOCK_VECTOR, &ignored );
351         
352          rtems_interrupt_enable( isrlevel );
353        }
354    }
355  return RTEMS_SUCCESSFUL;
356}
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