1 | /* |
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2 | * This file contains the clock driver the Hitachi SH 703X |
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3 | * |
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4 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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5 | * Bernd Becker (becker@faw.uni-ulm.de) |
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6 | * |
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7 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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8 | * |
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9 | * This program is distributed in the hope that it will be useful, |
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10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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12 | * |
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13 | * |
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14 | * COPYRIGHT (c) 1998. |
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15 | * On-Line Applications Research Corporation (OAR). |
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16 | * |
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17 | * The license and distribution terms for this file may be |
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18 | * found in the file LICENSE in this distribution or at |
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19 | * http://www.rtems.com/license/LICENSE. |
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20 | * |
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21 | * $Id$ |
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22 | */ |
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23 | |
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24 | #include <rtems.h> |
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25 | |
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26 | #include <stdlib.h> |
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27 | |
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28 | #include <rtems/libio.h> |
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29 | #include <rtems/score/sh_io.h> |
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30 | #include <rtems/score/sh.h> |
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31 | #include <rtems/score/ispsh7032.h> |
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32 | #include <rtems/score/iosh7032.h> |
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33 | |
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34 | extern uint32_t bsp_clicks_per_second; |
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35 | |
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36 | #ifndef CLOCKPRIO |
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37 | #define CLOCKPRIO 10 |
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38 | #endif |
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39 | |
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40 | #define I_CLK_PHI_1 0 |
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41 | #define I_CLK_PHI_2 1 |
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42 | #define I_CLK_PHI_4 2 |
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43 | #define I_CLK_PHI_8 3 |
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44 | |
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45 | /* |
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46 | * Set I_CLK_PHI to one of the I_CLK_PHI_X values from above to choose |
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47 | * a PHI/X clock rate. |
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48 | */ |
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49 | |
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50 | #define I_CLK_PHI I_CLK_PHI_4 |
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51 | #define CLOCK_SCALE (1<<I_CLK_PHI) |
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52 | |
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53 | #define ITU0_STARTMASK 0xfe |
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54 | #define ITU0_SYNCMASK 0xfe |
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55 | #define ITU0_MODEMASK 0xfe |
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56 | #define ITU0_TCRMASK (0x20 | I_CLK_PHI) |
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57 | #define ITU_STAT_MASK 0xf8 |
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58 | #define ITU0_IRQMASK 0xfe |
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59 | #define ITU0_TIERMASK 0x01 |
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60 | #define IPRC_ITU0_MASK 0xff0f |
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61 | #define ITU0_TIORVAL 0x08 |
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62 | |
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63 | /* |
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64 | * clicks_per_tick := clicks_per_sec * usec_per_tick |
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65 | * |
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66 | * This is a very expensive function ;-) |
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67 | * |
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68 | * Below are two variants: |
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69 | * 1. A variant applying integer arithmetics, only. |
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70 | * 2. A variant applying floating point arithmetics |
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71 | * |
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72 | * The floating point variant pulls in the fmath routines when linking, |
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73 | * resulting in slightly larger executables for applications that do not |
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74 | * apply fmath otherwise. However, the imath variant is significantly slower |
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75 | * than the fmath variant and more complex. |
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76 | * |
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77 | * Assuming that most applications will not use fmath, but are critical |
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78 | * in memory size constraints, we apply the integer variant. |
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79 | * |
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80 | * To the sake of simplicity, we might abandon one of both variants in |
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81 | * future. |
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82 | */ |
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83 | static unsigned int sh_clicks_per_tick( |
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84 | unsigned int clicks_per_sec, |
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85 | unsigned int usec_per_tick |
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86 | ) |
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87 | { |
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88 | #if 1 |
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89 | unsigned int clicks_per_tick = 0 ; |
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90 | |
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91 | unsigned int b = clicks_per_sec ; |
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92 | unsigned int c = 1000000 ; |
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93 | unsigned int d = 1 ; |
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94 | unsigned int a = ( ( b / c ) * usec_per_tick ) / d; |
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95 | |
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96 | clicks_per_tick += a ; |
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97 | |
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98 | while ( ( b %= c ) > 0 ) |
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99 | { |
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100 | c /= 10 ; |
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101 | d *= 10 ; |
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102 | a = ( ( b / c ) * usec_per_tick ) / d ; |
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103 | clicks_per_tick += a ; |
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104 | } |
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105 | return clicks_per_tick ; |
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106 | #else |
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107 | double fclicks_per_tick = |
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108 | ((double) clicks_per_sec * (double) usec_per_tick) / 1000000.0 ; |
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109 | return (uint32_t) fclicks_per_tick ; |
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110 | #endif |
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111 | } |
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112 | |
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113 | /* |
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114 | * The interrupt vector number associated with the clock tick device |
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115 | * driver. |
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116 | */ |
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117 | |
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118 | #define CLOCK_VECTOR IMIA0_ISP_V |
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119 | |
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120 | /* |
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121 | * Clock_driver_ticks is a monotonically increasing counter of the |
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122 | * number of clock ticks since the driver was initialized. |
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123 | */ |
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124 | |
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125 | volatile uint32_t Clock_driver_ticks; |
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126 | |
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127 | static void Clock_exit( void ); |
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128 | static rtems_isr Clock_isr( rtems_vector_number vector ); |
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129 | |
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130 | /* |
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131 | * Clock_isrs is the number of clock ISRs until the next invocation of |
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132 | * the RTEMS clock tick routine. The clock tick device driver |
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133 | * gets an interrupt once a millisecond and counts down until the |
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134 | * length of time between the user configured microseconds per tick |
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135 | * has passed. |
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136 | */ |
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137 | |
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138 | uint32_t Clock_isrs; /* ISRs until next tick */ |
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139 | static uint32_t Clock_isrs_const; /* only calculated once */ |
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140 | |
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141 | /* |
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142 | * These are set by clock driver during its init |
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143 | */ |
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144 | |
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145 | rtems_device_major_number rtems_clock_major = ~0; |
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146 | rtems_device_minor_number rtems_clock_minor; |
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147 | |
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148 | /* |
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149 | * The previous ISR on this clock tick interrupt vector. |
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150 | */ |
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151 | |
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152 | rtems_isr_entry Old_ticker; |
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153 | |
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154 | /* |
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155 | * Isr Handler |
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156 | */ |
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157 | |
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158 | rtems_isr Clock_isr( |
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159 | rtems_vector_number vector |
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160 | ) |
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161 | { |
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162 | /* |
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163 | * bump the number of clock driver ticks since initialization |
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164 | * |
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165 | * determine if it is time to announce the passing of tick as configured |
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166 | * to RTEMS through the rtems_clock_tick directive |
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167 | * |
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168 | * perform any timer dependent tasks |
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169 | */ |
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170 | uint8_t temp; |
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171 | |
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172 | /* reset the flags of the status register */ |
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173 | temp = read8( ITU_TSR0) & ITU_STAT_MASK; |
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174 | write8( temp, ITU_TSR0); |
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175 | |
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176 | Clock_driver_ticks++ ; |
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177 | |
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178 | if( Clock_isrs == 1) |
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179 | { |
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180 | rtems_clock_tick(); |
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181 | Clock_isrs = Clock_isrs_const; |
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182 | } |
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183 | else |
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184 | { |
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185 | Clock_isrs-- ; |
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186 | } |
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187 | } |
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188 | |
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189 | /* |
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190 | * Install_clock |
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191 | * |
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192 | * Install a clock tick handler and reprograms the chip. This |
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193 | * is used to initially establish the clock tick. |
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194 | */ |
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195 | |
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196 | void Install_clock( |
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197 | rtems_isr_entry clock_isr |
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198 | ) |
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199 | { |
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200 | uint8_t temp8 = 0; |
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201 | uint32_t microseconds_per_tick; |
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202 | uint32_t cclicks_per_tick; |
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203 | uint16_t Clock_limit; |
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204 | |
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205 | /* |
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206 | * Initialize the clock tick device driver variables |
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207 | */ |
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208 | |
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209 | Clock_driver_ticks = 0; |
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210 | |
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211 | if ( rtems_configuration_get_microseconds_per_tick() != 0 ) |
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212 | microseconds_per_tick = rtems_configuration_get_microseconds_per_tick() ; |
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213 | else |
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214 | microseconds_per_tick = 10000 ; /* 10000 us */ |
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215 | |
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216 | /* clock clicks per tick */ |
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217 | cclicks_per_tick = sh_clicks_per_tick( |
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218 | bsp_clicks_per_second / CLOCK_SCALE, microseconds_per_tick ); |
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219 | |
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220 | Clock_isrs_const = cclicks_per_tick >> 16 ; |
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221 | if ( ( cclicks_per_tick | 0xffff ) > 0 ) |
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222 | Clock_isrs_const++ ; |
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223 | Clock_limit = cclicks_per_tick / Clock_isrs_const ; |
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224 | Clock_isrs = Clock_isrs_const; |
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225 | |
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226 | rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker ); |
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227 | /* |
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228 | * Hardware specific initialize goes here |
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229 | */ |
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230 | |
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231 | /* stop Timer 0 */ |
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232 | temp8 = read8( ITU_TSTR) & ITU0_STARTMASK; |
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233 | write8( temp8, ITU_TSTR); |
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234 | |
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235 | /* set initial counter value to 0 */ |
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236 | write16( 0, ITU_TCNT0); |
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237 | |
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238 | /* Timer 0 runs independent */ |
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239 | temp8 = read8( ITU_TSNC) & ITU0_SYNCMASK; |
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240 | write8( temp8, ITU_TSNC); |
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241 | |
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242 | /* Timer 0 normal mode */ |
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243 | temp8 = read8( ITU_TMDR) & ITU0_MODEMASK; |
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244 | write8( temp8, ITU_TMDR); |
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245 | |
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246 | /* TCNT is cleared by GRA ; internal clock /4 */ |
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247 | write8( ITU0_TCRMASK , ITU_TCR0); |
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248 | |
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249 | /* use GRA without I/O - pins */ |
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250 | write8( ITU0_TIORVAL, ITU_TIOR0); |
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251 | |
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252 | /* reset flags of the status register */ |
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253 | temp8 = read8( ITU_TSR0) & ITU_STAT_MASK; |
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254 | write8( temp8, ITU_TSR0); |
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255 | |
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256 | /* Irq if is equal GRA */ |
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257 | temp8 = read8( ITU_TIER0) | ITU0_TIERMASK; |
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258 | write8( temp8, ITU_TIER0); |
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259 | |
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260 | /* set interrupt priority */ |
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261 | if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL) |
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262 | rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); |
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263 | |
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264 | /* set counter limits */ |
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265 | write16( Clock_limit, ITU_GRA0); |
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266 | |
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267 | /* start counter */ |
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268 | temp8 = read8( ITU_TSTR) |~ITU0_STARTMASK; |
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269 | write8( temp8, ITU_TSTR); |
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270 | |
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271 | /* |
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272 | * Schedule the clock cleanup routine to execute if the application exits. |
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273 | */ |
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274 | |
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275 | atexit( Clock_exit ); |
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276 | } |
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277 | |
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278 | /* |
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279 | * Clean up before the application exits |
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280 | */ |
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281 | |
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282 | void Clock_exit( void ) |
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283 | { |
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284 | uint8_t temp8 = 0; |
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285 | |
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286 | /* turn off the timer interrupts */ |
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287 | /* set interrupt priority to 0 */ |
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288 | if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL) |
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289 | rtems_fatal_error_occurred( RTEMS_UNSATISFIED); |
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290 | |
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291 | /* |
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292 | * temp16 = read16( ITU_TIER0) & IPRC_ITU0_IRQMASK; |
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293 | * write16( temp16, ITU_TIER0); |
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294 | */ |
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295 | |
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296 | /* stop counter */ |
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297 | temp8 = read8( ITU_TSTR) & ITU0_STARTMASK; |
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298 | write8( temp8, ITU_TSTR); |
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299 | |
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300 | /* old vector shall not be installed */ |
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301 | } |
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302 | |
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303 | /* |
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304 | * Clock_initialize |
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305 | * |
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306 | * Device driver entry point for clock tick driver initialization. |
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307 | */ |
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308 | |
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309 | rtems_device_driver Clock_initialize( |
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310 | rtems_device_major_number major, |
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311 | rtems_device_minor_number minor, |
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312 | void *pargp |
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313 | ) |
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314 | { |
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315 | Install_clock( Clock_isr ); |
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316 | |
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317 | /* |
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318 | * make major/minor avail to others such as shared memory driver |
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319 | */ |
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320 | |
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321 | rtems_clock_major = major; |
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322 | rtems_clock_minor = minor; |
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323 | |
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324 | return RTEMS_SUCCESSFUL; |
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325 | } |
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326 | |
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327 | rtems_device_driver Clock_control( |
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328 | rtems_device_major_number major, |
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329 | rtems_device_minor_number minor, |
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330 | void *pargp |
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331 | ) |
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332 | { |
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333 | uint32_t isrlevel; |
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334 | rtems_libio_ioctl_args_t *args = pargp; |
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335 | |
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336 | if (args != 0) |
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337 | { |
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338 | /* |
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339 | * This is hokey, but until we get a defined interface |
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340 | * to do this, it will just be this simple... |
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341 | */ |
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342 | |
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343 | if (args->command == rtems_build_name('I', 'S', 'R', ' ')) |
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344 | { |
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345 | Clock_isr(CLOCK_VECTOR); |
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346 | } |
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347 | else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) |
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348 | { |
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349 | rtems_isr_entry ignored ; |
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350 | rtems_interrupt_disable( isrlevel ); |
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351 | rtems_interrupt_catch( args->buffer, CLOCK_VECTOR, &ignored ); |
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352 | |
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353 | rtems_interrupt_enable( isrlevel ); |
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354 | } |
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355 | } |
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356 | return RTEMS_SUCCESSFUL; |
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357 | } |
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