[f8b27df9] | 1 | /* |
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| 2 | * This file contains the clock driver the Hitachi SH 703X |
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| 3 | * |
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| 4 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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| 5 | * Bernd Becker (becker@faw.uni-ulm.de) |
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| 6 | * |
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| 7 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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| 8 | * |
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| 9 | * This program is distributed in the hope that it will be useful, |
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| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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| 12 | * |
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| 13 | * |
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| 14 | * COPYRIGHT (c) 1998. |
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| 15 | * On-Line Applications Research Corporation (OAR). |
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| 16 | * Copyright assigned to U.S. Government, 1994. |
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| 17 | * |
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| 18 | * The license and distribution terms for this file may be |
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| 19 | * found in the file LICENSE in this distribution or at |
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| 20 | * http://www.OARcorp.com/rtems/license.html. |
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| 21 | * |
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| 22 | * $Id$ |
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| 23 | */ |
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| 24 | |
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| 25 | #include <bsp.h> |
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| 26 | |
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| 27 | #include <stdlib.h> |
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| 28 | |
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| 29 | #include <rtems/libio.h> |
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| 30 | #include <rtems/score/sh_io.h> |
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| 31 | #include <rtems/score/sh.h> |
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| 32 | #include <rtems/score/cpu_isps.h> |
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| 33 | #include <rtems/score/iosh7030.h> |
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| 34 | |
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| 35 | #define _ITU_COUNTER0_MICROSECOND (MHZ/4) |
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| 36 | |
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| 37 | #ifndef CLOCKPRIO |
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| 38 | #define CLOCKPRIO 10 |
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| 39 | #endif |
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| 40 | |
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| 41 | #define ITU0_STARTMASK 0xfe |
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| 42 | #define ITU0_SYNCMASK 0xfe |
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| 43 | #define ITU0_MODEMASK 0xfe |
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| 44 | #define ITU0_TCRMASK 0x22 |
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| 45 | #define ITU_STAT_MASK 0xf8 |
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| 46 | #define ITU0_IRQMASK 0xfe |
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| 47 | #define ITU0_TIERMASK 0x01 |
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| 48 | #define IPRC_ITU0_MASK 0xff0f |
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| 49 | #define ITU0_TIORVAL 0x08 |
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| 50 | |
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| 51 | /* |
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| 52 | * The interrupt vector number associated with the clock tick device |
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| 53 | * driver. |
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| 54 | */ |
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| 55 | |
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| 56 | #define CLOCK_VECTOR IMIA0_ISP_V |
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| 57 | |
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| 58 | /* |
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| 59 | * Clock_driver_ticks is a monotonically increasing counter of the |
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| 60 | * number of clock ticks since the driver was initialized. |
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| 61 | */ |
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| 62 | |
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| 63 | volatile rtems_unsigned32 Clock_driver_ticks; |
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| 64 | |
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| 65 | static void Clock_exit( void ); |
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| 66 | static rtems_isr Clock_isr( rtems_vector_number vector ); |
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| 67 | |
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| 68 | /* |
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| 69 | * Clock_isrs is the number of clock ISRs until the next invocation of |
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| 70 | * the RTEMS clock tick routine. The clock tick device driver |
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| 71 | * gets an interrupt once a millisecond and counts down until the |
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| 72 | * length of time between the user configured microseconds per tick |
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| 73 | * has passed. |
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| 74 | */ |
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| 75 | |
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| 76 | rtems_unsigned32 Clock_isrs; /* ISRs until next tick */ |
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| 77 | static rtems_unsigned32 Clock_isrs_const; /* only calculated once */ |
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| 78 | |
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| 79 | /* |
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| 80 | * These are set by clock driver during its init |
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| 81 | */ |
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| 82 | |
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| 83 | rtems_device_major_number rtems_clock_major = ~0; |
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| 84 | rtems_device_minor_number rtems_clock_minor; |
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| 85 | |
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| 86 | /* |
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| 87 | * The previous ISR on this clock tick interrupt vector. |
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| 88 | */ |
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| 89 | |
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| 90 | rtems_isr_entry Old_ticker; |
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| 91 | |
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| 92 | /* |
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| 93 | * Isr Handler |
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| 94 | */ |
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| 95 | |
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| 96 | rtems_isr Clock_isr( |
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| 97 | rtems_vector_number vector |
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| 98 | ) |
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| 99 | { |
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| 100 | /* |
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| 101 | * bump the number of clock driver ticks since initialization |
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| 102 | * |
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| 103 | |
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| 104 | * determine if it is time to announce the passing of tick as configured |
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| 105 | * to RTEMS through the rtems_clock_tick directive |
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| 106 | * |
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| 107 | * perform any timer dependent tasks |
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| 108 | */ |
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| 109 | unsigned8 temp; |
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| 110 | |
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| 111 | /* reset the flags of the status register */ |
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| 112 | temp = read8( ITU_TSR0) & ITU_STAT_MASK; |
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| 113 | write8( temp, ITU_TSR0); |
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| 114 | |
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| 115 | Clock_driver_ticks++ ; |
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| 116 | |
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| 117 | if( Clock_isrs == 1) |
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| 118 | { |
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| 119 | rtems_clock_tick(); |
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| 120 | Clock_isrs = Clock_isrs_const; |
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| 121 | } |
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| 122 | else |
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| 123 | { |
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| 124 | Clock_isrs-- ; |
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| 125 | } |
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| 126 | } |
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| 127 | |
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| 128 | /* |
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| 129 | * Install_clock |
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| 130 | * |
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| 131 | * Install a clock tick handler and reprograms the chip. This |
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| 132 | * is used to initially establish the clock tick. |
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| 133 | */ |
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| 134 | |
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| 135 | void Install_clock( |
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| 136 | rtems_isr_entry clock_isr |
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| 137 | ) |
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| 138 | { |
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| 139 | unsigned8 temp8 = 0; |
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| 140 | |
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| 141 | /* |
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| 142 | * Initialize the clock tick device driver variables |
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| 143 | */ |
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| 144 | |
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| 145 | Clock_driver_ticks = 0; |
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| 146 | Clock_isrs_const = BSP_Configuration.microseconds_per_tick / 10000; |
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| 147 | Clock_isrs = Clock_isrs_const; |
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| 148 | |
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| 149 | /* |
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| 150 | * If ticks_per_timeslice is configured as non-zero, then the user |
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| 151 | * wants a clock tick. |
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| 152 | */ |
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| 153 | |
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| 154 | if ( BSP_Configuration.ticks_per_timeslice ) { |
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[21bfd93] | 155 | rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker ); |
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[f8b27df9] | 156 | /* |
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| 157 | * Hardware specific initialize goes here |
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| 158 | */ |
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| 159 | |
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| 160 | /* stop Timer 0 */ |
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| 161 | temp8 = read8( ITU_TSTR) & ITU0_STARTMASK; |
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| 162 | write8( temp8, ITU_TSTR); |
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| 163 | |
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| 164 | /* set initial counter value to 0 */ |
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| 165 | write16( 0, ITU_TCNT0); |
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| 166 | |
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| 167 | /* Timer 0 runs independent */ |
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| 168 | temp8 = read8( ITU_TSNC) & ITU0_SYNCMASK; |
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| 169 | write8( temp8, ITU_TSNC); |
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| 170 | |
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| 171 | /* Timer 0 normal mode */ |
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| 172 | temp8 = read8( ITU_TMDR) & ITU0_MODEMASK; |
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| 173 | write8( temp8, ITU_TMDR); |
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| 174 | |
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| 175 | /* TCNT is cleared by GRA ; internal clock /4 */ |
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| 176 | write8( ITU0_TCRMASK , ITU_TCR0); |
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| 177 | |
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| 178 | /* use GRA without I/O - pins */ |
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| 179 | write8( ITU0_TIORVAL, ITU_TIOR0); |
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| 180 | |
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| 181 | /* reset flags of the status register */ |
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| 182 | temp8 = read8( ITU_TSR0) & ITU_STAT_MASK; |
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| 183 | write8( temp8, ITU_TSR0); |
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| 184 | |
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| 185 | /* Irq if is equal GRA */ |
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| 186 | temp8 = read8( ITU_TIER0) | ITU0_TIERMASK; |
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| 187 | write8( temp8, ITU_TIER0); |
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| 188 | |
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| 189 | /* set interrupt priority */ |
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| 190 | if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL) |
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| 191 | rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); |
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| 192 | |
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| 193 | /* set counter limits */ |
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| 194 | write16( _ITU_COUNTER0_MICROSECOND * BSP_Configuration.microseconds_per_tick, |
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| 195 | ITU_GRA0); |
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| 196 | |
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| 197 | /* start counter */ |
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| 198 | temp8 = read8( ITU_TSTR) |~ITU0_STARTMASK; |
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| 199 | write8( temp8, ITU_TSTR); |
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| 200 | |
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| 201 | } |
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| 202 | |
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| 203 | /* |
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| 204 | * Schedule the clock cleanup routine to execute if the application exits. |
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| 205 | */ |
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| 206 | |
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| 207 | atexit( Clock_exit ); |
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| 208 | } |
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| 209 | |
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| 210 | /* |
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| 211 | * Clean up before the application exits |
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| 212 | */ |
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| 213 | |
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| 214 | void Clock_exit( void ) |
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| 215 | { |
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| 216 | unsigned8 temp8 = 0; |
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| 217 | if ( BSP_Configuration.ticks_per_timeslice ) { |
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| 218 | |
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| 219 | /* turn off the timer interrupts */ |
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| 220 | /* set interrupt priority to 0 */ |
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| 221 | if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL) |
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| 222 | rtems_fatal_error_occurred( RTEMS_UNSATISFIED); |
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| 223 | |
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| 224 | /* |
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| 225 | * temp16 = read16( ITU_TIER0) & IPRC_ITU0_IRQMASK; |
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| 226 | * write16( temp16, ITU_TIER0); |
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| 227 | */ |
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| 228 | |
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| 229 | /* stop counter */ |
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| 230 | temp8 = read8( ITU_TSTR) & ITU0_STARTMASK; |
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| 231 | write8( temp8, ITU_TSTR); |
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| 232 | |
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| 233 | /* old vector shall not be installed */ |
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| 234 | } |
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| 235 | } |
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| 236 | |
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| 237 | /* |
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| 238 | * Clock_initialize |
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| 239 | * |
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| 240 | * Device driver entry point for clock tick driver initialization. |
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| 241 | */ |
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| 242 | |
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| 243 | rtems_device_driver Clock_initialize( |
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| 244 | rtems_device_major_number major, |
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| 245 | rtems_device_minor_number minor, |
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| 246 | void *pargp |
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| 247 | ) |
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| 248 | { |
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| 249 | Install_clock( Clock_isr ); |
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| 250 | |
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| 251 | /* |
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| 252 | * make major/minor avail to others such as shared memory driver |
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| 253 | */ |
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| 254 | |
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| 255 | rtems_clock_major = major; |
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| 256 | rtems_clock_minor = minor; |
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| 257 | |
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| 258 | return RTEMS_SUCCESSFUL; |
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| 259 | } |
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| 260 | |
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| 261 | rtems_device_driver Clock_control( |
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| 262 | rtems_device_major_number major, |
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| 263 | rtems_device_minor_number minor, |
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| 264 | void *pargp |
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| 265 | ) |
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| 266 | { |
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| 267 | rtems_unsigned32 isrlevel; |
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| 268 | rtems_libio_ioctl_args_t *args = pargp; |
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| 269 | |
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| 270 | if (args != 0) |
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| 271 | { |
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| 272 | /* |
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| 273 | * This is hokey, but until we get a defined interface |
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| 274 | * to do this, it will just be this simple... |
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| 275 | */ |
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| 276 | |
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| 277 | if (args->command == rtems_build_name('I', 'S', 'R', ' ')) |
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| 278 | { |
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| 279 | Clock_isr(CLOCK_VECTOR); |
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| 280 | } |
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| 281 | else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) |
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| 282 | { |
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[21bfd93] | 283 | rtems_isr_entry ignored ; |
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[f8b27df9] | 284 | rtems_interrupt_disable( isrlevel ); |
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[21bfd93] | 285 | rtems_interrupt_catch( args->buffer, CLOCK_VECTOR, &ignored ); |
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| 286 | |
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[f8b27df9] | 287 | rtems_interrupt_enable( isrlevel ); |
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| 288 | } |
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| 289 | } |
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| 290 | return RTEMS_SUCCESSFUL; |
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| 291 | } |
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