source: rtems/c/src/lib/libcpu/powerpc/shared/src/cache.c @ d3d9ef37

4.104.114.84.95
Last change on this file since d3d9ef37 was 66c373bf, checked in by Ralf Corsepius <ralf.corsepius@…>, on Mar 31, 2004 at 2:04:00 AM

2004-03-30 Ralf Corsepius <ralf_corsepius@…>

  • mpc505/timer/timer.c, mpc5xx/timer/timer.c, mpc6xx/clock/c_clock.c, mpc6xx/timer/timer.c, mpc8260/clock/clock.c, mpc8260/console-generic/console-generic.c, mpc8260/cpm/cp.c, mpc8260/cpm/dpram.c, mpc8260/include/cpm.h, mpc8260/include/mmu.h, mpc8260/include/mpc8260.h, mpc8260/mmu/mmu.c, mpc8260/timer/timer.c, mpc8xx/clock/clock.c, mpc8xx/console-generic/console-generic.c, mpc8xx/cpm/cp.c, mpc8xx/cpm/dpram.c, mpc8xx/include/cpm.h, mpc8xx/include/mmu.h, mpc8xx/include/mpc8xx.h, mpc8xx/mmu/mmu.c, mpc8xx/timer/timer.c, ppc403/clock/clock.c, ppc403/console/console.c, ppc403/console/console405.c, ppc403/ictrl/ictrl.c, ppc403/ictrl/ictrl.h, ppc403/timer/timer.c, ppc403/tty_drv/tty_drv.c, rtems/powerpc/cache.h, shared/src/cache.c: Convert to using c99 fixed size types.
  • Property mode set to 100644
File size: 3.2 KB
Line 
1/*
2 *  Cache Management Support Routines for the MC68040
3 * Modified for MPC8260 Andy Dachs <a.dachs@sstl.co.uk>
4 * Surrey Satellite Technology Limited (SSTL), 2001
5 *
6 *  $Id$
7 */
8
9#include <rtems.h>
10#include "cache_.h"
11
12
13/*
14 * CACHE MANAGER: The following functions are CPU-specific.
15 * They provide the basic implementation for the rtems_* cache
16 * management routines. If a given function has no meaning for the CPU,
17 * it does nothing by default.
18 *
19 * FIXME: Some functions simply have not been implemented.
20 */
21 
22#if defined(ppc603) || defined(mpc8260)    /* And possibly others */
23
24/* Helpful macros */
25#define PPC_Get_HID0( _value ) \
26  do { \
27      _value = 0;        /* to avoid warnings */ \
28      asm volatile( \
29          "mfspr %0, 0x3f0;"     /* get HID0 */ \
30          "isync" \
31          : "=r" (_value) \
32          : "0" (_value) \
33      ); \
34  } while (0)
35
36#define PPC_Set_HID0( _value ) \
37  do { \
38      asm volatile( \
39          "isync;" \
40          "mtspr 0x3f0, %0;"     /* load HID0 */ \
41          "isync" \
42          : "=r" (_value) \
43          : "0" (_value) \
44      ); \
45  } while (0)
46
47void _CPU_cache_enable_data (
48        void )
49{
50  uint32_t   value;
51  PPC_Get_HID0( value );
52  value |= 0x00004000;        /* set DCE bit */
53  PPC_Set_HID0( value );
54}
55
56void _CPU_cache_disable_data (
57        void )
58{
59  uint32_t   value;
60  PPC_Get_HID0( value );
61  value &= 0xFFFFBFFF;        /* clear DCE bit */
62  PPC_Set_HID0( value );
63}
64
65void _CPU_cache_enable_instruction (
66        void )
67{
68  uint32_t   value;
69  PPC_Get_HID0( value );
70  value |= 0x00008000;       /* Set ICE bit */
71  PPC_Set_HID0( value );
72}
73
74void _CPU_cache_disable_instruction (
75        void )
76{
77  uint32_t   value;
78  PPC_Get_HID0( value );
79  value &= 0xFFFF7FFF;       /* Clear ICE bit */
80  PPC_Set_HID0( value );
81}
82
83#elif ( defined(mpx8xx) || defined(mpc860) || defined(mpc821) )
84
85#define mtspr(_spr,_reg) \
86  __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) )
87#define isync \
88  __asm__ volatile ("isync\n"::)
89
90void _CPU_cache_flush_1_data_line(
91        const void * _address )
92{
93  register const void *__address = _address;
94  asm volatile ( "dcbf 0,%0" :: "r" (__address) );
95}
96
97void _CPU_cache_invalidate_1_data_line(
98        const void * _address )
99{
100  register const void *__address = _address;
101  asm volatile ( "dcbi 0,%0" :: "r" (__address) );
102}
103
104void _CPU_cache_flush_entire_data ( void ) {}
105void _CPU_cache_invalidate_entire_data ( void ) {}
106void _CPU_cache_freeze_data ( void ) {}
107void _CPU_cache_unfreeze_data ( void ) {}
108
109void _CPU_cache_enable_data ( void )
110{
111  uint32_t   r1;
112  r1 = (0x2<<24);
113  mtspr( 568, r1 );
114  isync;
115}
116
117void _CPU_cache_disable_data ( void )
118{
119  uint32_t   r1;
120  r1 = (0x4<<24);
121  mtspr( 568, r1 );
122  isync;
123}
124
125void _CPU_cache_invalidate_1_instruction_line(
126        const void * _address )
127{
128  register const void *__address = _address;
129  asm volatile ( "icbi 0,%0" :: "r" (__address) );
130}
131
132void _CPU_cache_invalidate_entire_instruction ( void ) {}
133void _CPU_cache_freeze_instruction ( void ) {}
134void _CPU_cache_unfreeze_instruction ( void ) {}
135
136void _CPU_cache_enable_instruction ( void )
137{
138  uint32_t   r1;
139  r1 = (0x2<<24);
140  mtspr( 560, r1 );
141  isync;
142}
143
144void _CPU_cache_disable_instruction ( void )
145{
146  uint32_t   r1;
147  r1 = (0x4<<24);
148  mtspr( 560, r1 );
149  isync;
150}
151#endif
152
153/* end of file */
Note: See TracBrowser for help on using the repository browser.