1 | /* |
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2 | * Cache Management Support Routines for the MC68040 |
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3 | * |
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4 | * $Id$ |
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5 | */ |
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6 | |
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7 | #include <rtems.h> |
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8 | #include "cache_.h" |
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9 | |
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10 | |
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11 | /* |
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12 | * CACHE MANAGER: The following functions are CPU-specific. |
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13 | * They provide the basic implementation for the rtems_* cache |
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14 | * management routines. If a given function has no meaning for the CPU, |
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15 | * it does nothing by default. |
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16 | * |
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17 | * FIXME: Some functions simply have not been implemented. |
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18 | */ |
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19 | |
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20 | #if defined(ppc603) /* And possibly others */ |
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21 | |
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22 | /* Helpful macros */ |
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23 | #define PPC_Get_HID0( _value ) \ |
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24 | do { \ |
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25 | _value = 0; /* to avoid warnings */ \ |
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26 | asm volatile( \ |
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27 | "mfspr %0, 0x3f0;" /* get HID0 */ \ |
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28 | "isync" \ |
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29 | : "=r" (_value) \ |
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30 | : "0" (_value) \ |
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31 | ); \ |
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32 | } while (0) |
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33 | |
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34 | #define PPC_Set_HID0( _value ) \ |
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35 | do { \ |
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36 | asm volatile( \ |
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37 | "isync;" \ |
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38 | "mtspr 0x3f0, %0;" /* load HID0 */ \ |
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39 | "isync" \ |
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40 | : "=r" (_value) \ |
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41 | : "0" (_value) \ |
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42 | ); \ |
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43 | } while (0) |
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44 | |
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45 | void _CPU_cache_enable_data ( |
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46 | void ) |
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47 | { |
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48 | unsigned32 value; |
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49 | PPC_Get_HID0( value ); |
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50 | value |= 0x00004000; /* set DCE bit */ |
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51 | PPC_Set_HID0( value ); |
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52 | } |
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53 | |
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54 | void _CPU_cache_disable_data ( |
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55 | void ) |
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56 | { |
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57 | unsigned32 value; |
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58 | PPC_Get_HID0( value ); |
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59 | value &= 0xFFFFBFFF; /* clear DCE bit */ |
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60 | PPC_Set_HID0( value ); |
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61 | } |
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62 | |
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63 | void _CPU_cache_enable_inst ( |
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64 | void ) |
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65 | { |
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66 | unsigned32 value; |
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67 | PPC_Get_HID0( value ); |
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68 | value |= 0x00008000; /* Set ICE bit */ |
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69 | PPC_Set_HID0( value ); |
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70 | } |
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71 | |
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72 | void _CPU_cache_disable_inst ( |
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73 | void ) |
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74 | { |
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75 | unsigned32 value; |
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76 | PPC_Get_HID0( value ); |
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77 | value &= 0xFFFF7FFF; /* Clear ICE bit */ |
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78 | PPC_Set_HID0( value ); |
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79 | } |
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80 | |
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81 | #elif ( defined(mpc860) || defined(mpc821) ) |
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82 | |
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83 | #define mtspr(_spr,_reg) \ |
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84 | __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) ) |
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85 | #define isync \ |
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86 | __asm__ volatile ("isync\n"::) |
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87 | |
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88 | void _CPU_cache_flush_1_data_line( |
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89 | const void * _address ) |
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90 | { |
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91 | register const void *__address = _address; |
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92 | asm volatile ( "dcbf 0,%0" :: "r" (__address) ); |
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93 | } |
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94 | |
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95 | void _CPU_cache_invalidate_1_data_line( |
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96 | const void * _address ) |
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97 | { |
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98 | register const void *__address = _address; |
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99 | asm volatile ( "dcbi 0,%0" :: "r" (__address) ); |
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100 | } |
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101 | |
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102 | void _CPU_cache_flush_entire_data ( void ) {} |
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103 | void _CPU_cache_invalidate_entire_data ( void ) {} |
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104 | void _CPU_cache_freeze_data ( void ) {} |
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105 | void _CPU_cache_unfreeze_data ( void ) {} |
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106 | |
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107 | void _CPU_cache_enable_data ( void ) |
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108 | { |
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109 | unsigned32 r1; |
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110 | r1 = (0x2<<24); |
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111 | mtspr( 568, r1 ); |
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112 | isync; |
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113 | } |
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114 | |
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115 | void _CPU_cache_disable_data ( void ) |
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116 | { |
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117 | unsigned32 r1; |
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118 | r1 = (0x4<<24); |
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119 | mtspr( 568, r1 ); |
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120 | isync; |
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121 | } |
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122 | |
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123 | void _CPU_cache_invalidate_1_inst_line( |
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124 | const void * _address ) |
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125 | { |
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126 | register const void *__address = _address; |
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127 | asm volatile ( "icbi 0,%0" :: "r" (__address) ); |
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128 | } |
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129 | |
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130 | void _CPU_cache_invalidate_entire_inst ( void ) {} |
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131 | void _CPU_cache_freeze_inst ( void ) {} |
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132 | void _CPU_cache_unfreeze_inst ( void ) {} |
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133 | |
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134 | void _CPU_cache_enable_inst ( void ) |
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135 | { |
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136 | unsigned32 r1; |
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137 | r1 = (0x2<<24); |
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138 | mtspr( 560, r1 ); |
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139 | isync; |
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140 | } |
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141 | |
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142 | void _CPU_cache_disable_inst ( void ) |
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143 | { |
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144 | unsigned32 r1; |
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145 | r1 = (0x4<<24); |
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146 | mtspr( 560, r1 ); |
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147 | isync; |
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148 | } |
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149 | #endif |
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150 | |
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151 | /* end of file */ |
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