source: rtems/c/src/lib/libcpu/powerpc/shared/src/cache.c @ 0a18747

4.104.114.84.95
Last change on this file since 0a18747 was 0a18747, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 14, 2000 at 3:39:31 PM

New files containing cache manager functionality stripped from
score/cpu/powerpc.

  • Property mode set to 100644
File size: 3.0 KB
Line 
1/*
2 *  Cache Management Support Routines for the MC68040
3 *
4 *  $Id$
5 */
6
7#include <rtems.h>
8#include "cache_.h"
9
10
11/*
12 * CACHE MANAGER: The following functions are CPU-specific.
13 * They provide the basic implementation for the rtems_* cache
14 * management routines. If a given function has no meaning for the CPU,
15 * it does nothing by default.
16 *
17 * FIXME: Some functions simply have not been implemented.
18 */
19 
20#if defined(ppc603)                     /* And possibly others */
21
22/* Helpful macros */
23#define PPC_Get_HID0( _value ) \
24  do { \
25      _value = 0;        /* to avoid warnings */ \
26      asm volatile( \
27          "mfspr %0, 0x3f0;"     /* get HID0 */ \
28          "isync" \
29          : "=r" (_value) \
30          : "0" (_value) \
31      ); \
32  } while (0)
33
34#define PPC_Set_HID0( _value ) \
35  do { \
36      asm volatile( \
37          "isync;" \
38          "mtspr 0x3f0, %0;"     /* load HID0 */ \
39          "isync" \
40          : "=r" (_value) \
41          : "0" (_value) \
42      ); \
43  } while (0)
44
45void _CPU_enable_data_cache (
46        void )
47{
48  unsigned32 value;
49  PPC_Get_HID0( value );
50  value |= 0x00004000;        /* set DCE bit */
51  PPC_Set_HID0( value );
52}
53
54void _CPU_disable_data_cache (
55        void )
56{
57  unsigned32 value;
58  PPC_Get_HID0( value );
59  value &= 0xFFFFBFFF;        /* clear DCE bit */
60  PPC_Set_HID0( value );
61}
62
63void _CPU_enable_inst_cache (
64        void )
65{
66  unsigned32 value;
67  PPC_Get_HID0( value );
68  value |= 0x00008000;       /* Set ICE bit */
69  PPC_Set_HID0( value );
70}
71
72void _CPU_disable_inst_cache (
73        void )
74{
75  unsigned32 value;
76  PPC_Get_HID0( value );
77  value &= 0xFFFF7FFF;       /* Clear ICE bit */
78  PPC_Set_HID0( value );
79}
80
81#elif ( defined(mpc860) || defined(mpc821) )
82
83#define mtspr(_spr,_reg) \
84  __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) )
85#define isync \
86  __asm__ volatile ("isync\n"::)
87
88void _CPU_flush_1_data_cache_line(
89        const void * _address )
90{
91  register const void *__address = _address;
92  asm volatile ( "dcbf 0,%0" :: "r" (__address) );
93}
94
95void _CPU_invalidate_1_data_cache_line(
96        const void * _address )
97{
98  register const void *__address = _address;
99  asm volatile ( "dcbi 0,%0" :: "r" (__address) );
100}
101
102void _CPU_flush_entire_data_cache ( void ) {}
103void _CPU_invalidate_entire_data_cache ( void ) {}
104void _CPU_freeze_data_cache ( void ) {}
105void _CPU_unfreeze_data_cache ( void ) {}
106
107void _CPU_enable_data_cache ( void )
108{
109  unsigned32 r1;
110  r1 = (0x2<<24);
111  mtspr( 568, r1 );
112  isync;
113}
114
115void _CPU_disable_data_cache ( void )
116{
117  unsigned32 r1;
118  r1 = (0x4<<24);
119  mtspr( 568, r1 );
120  isync;
121}
122
123void _CPU_invalidate_1_inst_cache_line(
124        const void * _address )
125{
126  register const void *__address = _address;
127  asm volatile ( "icbi 0,%0" :: "r" (__address) );
128}
129
130void _CPU_invalidate_entire_inst_cache ( void ) {}
131void _CPU_freeze_inst_cache ( void ) {}
132void _CPU_unfreeze_inst_cache ( void ) {}
133
134void _CPU_enable_inst_cache ( void )
135{
136  unsigned32 r1;
137  r1 = (0x2<<24);
138  mtspr( 560, r1 );
139  isync;
140}
141
142void _CPU_disable_inst_cache ( void )
143{
144  unsigned32 r1;
145  r1 = (0x4<<24);
146  mtspr( 560, r1 );
147  isync;
148}
149#endif
150
151/* end of file */
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